Am I correct in understanding that the chip shuttle will be a full P2, not just the frame???
My reading is the test chip shuttle scheduled for September 15th, is the P2 Custom PAD frame, ie excludes final synthesis or core logic, but includes the full custom Analog PAD Ring and all Analog/Fuse/PinIO support, and PLLs and Dividers and PFC and RC Oscs.
Details of how that is bonded for test access, or if this will allow full speed IO testing, are sparse.
Maybe it's a 144 or 176 pin package ?
Correct. Just the pad frame circuits bonded into a 128-pin package, same as before.
How much can be tested, and to what speeds ?
This has the new RC Osc designs, so you can check Temperature and Vcc deviations & confirm fNom ?
Does the PLL include all VCO/FPD/Dividers, so you can check that works ?
I've seen many a fast rising signal overshoot briefly to around 4v, doesn't seem to cause any lasting damage.
We're heading for the realm of statistical distributions I guess. But 4.5 v for ~1ms would be fine I suspect.
I've seen many a fast rising signal overshoot briefly to around 4v, doesn't seem to cause any lasting damage.
We're heading for the realm of statistical distributions I guess. But 4.5 v for ~1ms would be fine I suspect.
The point is that 4.5V DC, will overshoot as the current collapses, just from parasitic supply inductance.
Chip, would the whole supply need to go 4.5v, or just the Vdd in the local pin group?
I think each Vio pin has some small number of associated fuses, but it is more complex to ripple each pin separately, than to just raise Vdd.
Fuse are blown one at a time.
Chip, would the whole supply need to go 4.5v, or just the Vdd in the local pin group?
Only the particular VIO that contains the four currently-getting-blown fuses needs to be raised, but it would be easier to design a single supply that connects to all of the VIO's.
Am I correct in understanding that the chip shuttle will be a full P2, not just the frame???
My reading is the test chip shuttle scheduled for September 15th, is the P2 Custom PAD frame, ie excludes final synthesis or core logic, but includes the full custom Analog PAD Ring and all Analog/Fuse/PinIO support, and PLLs and Dividers and PFC and RC Oscs.
Details of how that is bonded for test access, or if this will allow full speed IO testing, are sparse.
Maybe it's a 144 or 176 pin package ?
Correct. Just the pad frame circuits bonded into a 128-pin package, same as before.
How much can be tested, and to what speeds ?
This has the new RC Osc designs, so you can check Temperature and Vcc deviations & confirm fNom ?
Does the PLL include all VCO/FPD/Dividers, so you can check that works ?
The I/O pins got some minor resistor-length adjustments.
The clock pad, though, had extensive changes, with its own active power supply to feed the internal RC oscillator and the PLL. Plus, all those divider circuits are in there.
The reset pin had its power-on-reset detector reduced so that it operates more quickly.
Only the particular VIO that contains the four currently-getting-blown fuses needs to be raised, but it would be easier to design a single supply that connects to all of the VIO's.
Are these one-at-a-time blown, or up to 4 in parallel ?
The I/O pins got some minor resistor-length adjustments.
The clock pad, though, had extensive changes, with its own active power supply to feed the internal RC oscillator and the PLL. Plus, all those divider circuits are in there.
The reset pin had its power-on-reset detector reduced so that it operates more quickly.
I think these are all low-risk changes.
Cool, so you will be able to get MHz/Vcc/Temp plots on oscillators, as well as exercise the PLL with various signal sources, right up to (above) the 180MHz target ?
I doubt I would ever use the fuses for any of my projects, but it seems really crazy to me to have to build a special circuit (or whatever) just to program the fuses.
Either you have a special board with a special expensive socket in it to allow you to program all your P2s fuses before placing them on final boards, or you build the special circuit into every board just for blowing the fuses the first time and then never use it again.
Both options seem like completely awful solutions for anyone doing mass production, they increase the cost or time or both. Seems like you need to find a solution that doesn't require special circuitry external to the chip, or you just scrap fuses (because the people that want the security aren't going to jump through those hoops to get it... it's too much....)
I think what's being proposed is pretty simple. Many regulators have a voltage divider to form their setpoint, and potentially all that needs to happen is the midpoint of the divider is temporarily modified by a smart pin (which has good dac control). So for many designs it may be just a single smart pin connected to the right node.
For designs with interconnected ics that must be protected, decoupling/clamps/bank segregation/second reg strategies might apply. But that's not impossible
Tubular, so you lose a whole smart pin forever just to be able to blow fuses once?
And wouldn't that require you to always setup the smart pin properly at startup? That's not a workable solution when you have the potential for that pin to never be set right due to software. Could even lead to feeding too much power for extended periods... sizzle.
The right solution is the one that does not require anything special.
Seriously, Chip, this can't be an acceptable thing. You have to either drop the feature entirely or fix it properly. This will be considered a flaw, and it will cost potential sales.
For designs with interconnected ics that must be protected, decoupling/clamps/bank segregation/second reg strategies might apply. But that's not impossible
Not impossible but a whole load of extra stuff on the BOM.
For us hobby folks it's not a big deal at all, I agree.
For commercial designs, particularly for mass productions, it's what will make many opt out of P2. "Your design has to handle 4.5 VDC spikes on the 3.3 VDC lines in order to set fuses, or you have to make a rig to set fuses on the chips before placing them on the boards." I suspect many potential commercial users that want security will see those requirements and pass on the chip for that reason alone. Those kinds of things can cost a lot of extra money in manufacturing.
It's definitely not ideal, but in this case Parallax could potentially ask Parallax. If we were to make a product requiring security (e.g. I assume that the basicstamp uses some sort of fuses for protection, so there is some experience) then what would it cost in production to use the Prop2 fuses given the constraints?
For commercial designs, particularly for mass productions, it's what will make many opt out of P2. "Your design has to handle 4.5 VDC spikes on the 3.3 VDC lines in order to set fuses, or you have to make a rig to set fuses on the chips before placing them on the boards." I suspect many potential commercial users that want security will see those requirements and pass on the chip for that reason alone. Those kinds of things can cost a lot of extra money in manufacturing.
Exactly and even that 4.5V has fish-hooks aplenty...
If you target a nominal 4.5V, you need to check tolerances which may mean 5% of headroom, and then you need to check the Dynamic Load performance of your regulator, under fuse-blow conditions. add maybe 100~200mV of additional spike, and you need parts spec'd to 4.875V
Parallax may need to provide a fuse current model, (likely needs tight Cap specs), as the user is not going to want to consume chips for testing...
Maybe with the new shuttle run, some better statistical data can be gleaned on just what Vcc really IS needed to blow fuses, in real cumulative percentage curves,
(and that will need some Capp specs too)
The sample size thus far, seems too small to be useful.
Heh, Parallax, could sell them already blown. I'm kidding. Mostly.
Many vendors do offer factory Programming, and that does solve some issues, but not all.
Moderately paranoid customers are ok with giving a vendor fuse info, highly paranoids ones less so.
It also means part codes and labeling need more resources.
Isn't it worth asking onsemi about shaving these fuses down?
ISTR they already are the min-width ?
An OTP cell is probably the next-easiest step.
Of course, Non-OTP is nicer, but that may have process/area costs ?
IMHO this will mean only the most hardened customers will use fuses. Many customers will consider the P2 a failed chip with this impediment, and won't even use it even if they don't want the fuses anyway. At least that's the way I would consider it if I were considering the P2 in a commercial design.
There are already enough reasons to use another "more standard" chip that the P2. This will give the designes just another reason to bypass the P2.
Add to this, the requirement for an external Flash chip, and maybe an external crystal. It is just not a chip of 2017 !!!
How difficult is it to have a smartpin create a square wave and with a couple of components create a boost converter to achieve the 5V. This could be done with a jumper at the time of blowing the fuse.
How difficult is it to have a smartpin create a square wave and with a couple of components create a boost converter to achieve the 5V. This could be done with a jumper at the time of blowing the fuse.
The problem there, is the fuse blow is quite literally that - this is not some low charge Vpp pin - it needs to appear on the FET Gate and the fuse load, to ensure enough energy hits the fuse to actually make it fuse.
Well just to scare or reassure further, depending on your preference, here's an unloaded P1 pin shooting to 4.52v before settling at 3v3.
That ringing is an artifact of the way the signal is being probed -- probably too long of a ground-clip lead -- not the P1's actual output.
-Phil
Overshoot is *real*, Phil!. Yes, there are certainly probe artifacts present but my point is things keep running even after being probed, subjected to jumper wires etc. I don't believe for a minute 4.5v peaks are going to cause us trouble.
IMHO this will mean only the most hardened customers will use fuses. Many customers will consider the P2 a failed chip with this impediment, and won't even use it even if they don't want the fuses anyway. At least that's the way I would consider it if I were considering the P2 in a commercial design.
There are already enough reasons to use another "more standard" chip that the P2. This will give the designes just another reason to bypass the P2.
Add to this, the requirement for an external Flash chip, and maybe an external crystal. It is just not a chip of 2017 !!!
That I agree less with, as there ARE chips with external Crystals and external flash - the WiFi parts do this.
The P2 may be able to have a Cal OSC, as Chip has improved the PVT details, and it then just needs a CalByte stored.
CalOSC is not so critical on a P2 price point part. It matters a LOT more on a 28c MCU !
P2 will most likely be used with Crystal or CMOS osc or Clipped Sine TCXO & Clipped Sine TCXO are quite cheap, for very good precision (±500ppb)
External Flash is low cost and small and flexible, but more important than where flash is, is keeping the boot times down as much as possible.
It appears P2 can boot from the new OctoFlash parts, as well as QuadSPI parts.
If I had to pick a missing feature on P2 around Clocks, it would be there is no Clock failure fall back. Some software standards require this.
eg after reset, there is no means to check Xtal osc is working, before you flip-over, and No osc watchdog.
An external clocked WDOG can manage the osc-watchdog side, but with no means to check Osc-ok, you simple repeat the WDOG cycles.
How difficult is it to have a smartpin create a square wave and with a couple of components create a boost converter to achieve the 5V. This could be done with a jumper at the time of blowing the fuse.
The smartpins have the following mode
%01010 = PWM switch-mode power supply with voltage and current feedback
Comments
This has the new RC Osc designs, so you can check Temperature and Vcc deviations & confirm fNom ?
Does the PLL include all VCO/FPD/Dividers, so you can check that works ?
We're heading for the realm of statistical distributions I guess. But 4.5 v for ~1ms would be fine I suspect.
The point is that 4.5V DC, will overshoot as the current collapses, just from parasitic supply inductance.
I think each Vio pin has some small number of associated fuses, but it is more complex to ripple each pin separately, than to just raise Vdd.
Fuse are blown one at a time.
Only the particular VIO that contains the four currently-getting-blown fuses needs to be raised, but it would be easier to design a single supply that connects to all of the VIO's.
The I/O pins got some minor resistor-length adjustments.
The clock pad, though, had extensive changes, with its own active power supply to feed the internal RC oscillator and the PLL. Plus, all those divider circuits are in there.
The reset pin had its power-on-reset detector reduced so that it operates more quickly.
I think these are all low-risk changes.
Cool, so you will be able to get MHz/Vcc/Temp plots on oscillators, as well as exercise the PLL with various signal sources, right up to (above) the 180MHz target ?
Either you have a special board with a special expensive socket in it to allow you to program all your P2s fuses before placing them on final boards, or you build the special circuit into every board just for blowing the fuses the first time and then never use it again.
Both options seem like completely awful solutions for anyone doing mass production, they increase the cost or time or both. Seems like you need to find a solution that doesn't require special circuitry external to the chip, or you just scrap fuses (because the people that want the security aren't going to jump through those hoops to get it... it's too much....)
For designs with interconnected ics that must be protected, decoupling/clamps/bank segregation/second reg strategies might apply. But that's not impossible
And wouldn't that require you to always setup the smart pin properly at startup? That's not a workable solution when you have the potential for that pin to never be set right due to software. Could even lead to feeding too much power for extended periods... sizzle.
The right solution is the one that does not require anything special.
Seriously, Chip, this can't be an acceptable thing. You have to either drop the feature entirely or fix it properly. This will be considered a flaw, and it will cost potential sales.
Not impossible but a whole load of extra stuff on the BOM.
For commercial designs, particularly for mass productions, it's what will make many opt out of P2. "Your design has to handle 4.5 VDC spikes on the 3.3 VDC lines in order to set fuses, or you have to make a rig to set fuses on the chips before placing them on the boards." I suspect many potential commercial users that want security will see those requirements and pass on the chip for that reason alone. Those kinds of things can cost a lot of extra money in manufacturing.
Exactly and even that 4.5V has fish-hooks aplenty...
If you target a nominal 4.5V, you need to check tolerances which may mean 5% of headroom, and then you need to check the Dynamic Load performance of your regulator, under fuse-blow conditions. add maybe 100~200mV of additional spike, and you need parts spec'd to 4.875V
Parallax may need to provide a fuse current model, (likely needs tight Cap specs), as the user is not going to want to consume chips for testing...
Maybe with the new shuttle run, some better statistical data can be gleaned on just what Vcc really IS needed to blow fuses, in real cumulative percentage curves,
(and that will need some Capp specs too)
The sample size thus far, seems too small to be useful.
The falling transition is similar. I think this kind of thing is really common and doesn't cause significant failures
The yellow trace is the 3v3 power rail, AC coupled. I am investigating something jmg mentioned earlier that might be used to advantage, maybe
Isn't it worth asking onsemi about shaving these fuses down?
Many vendors do offer factory Programming, and that does solve some issues, but not all.
Moderately paranoid customers are ok with giving a vendor fuse info, highly paranoids ones less so.
It also means part codes and labeling need more resources.
ISTR they already are the min-width ?
An OTP cell is probably the next-easiest step.
Of course, Non-OTP is nicer, but that may have process/area costs ?
Here's the capture of the flip module switcher rail with heavy resistive loads on 6 pins being sharply cut off
-Phil
There are already enough reasons to use another "more standard" chip that the P2. This will give the designes just another reason to bypass the P2.
Add to this, the requirement for an external Flash chip, and maybe an external crystal. It is just not a chip of 2017 !!!
Overshoot is *real*, Phil!. Yes, there are certainly probe artifacts present but my point is things keep running even after being probed, subjected to jumper wires etc. I don't believe for a minute 4.5v peaks are going to cause us trouble.
That I agree less with, as there ARE chips with external Crystals and external flash - the WiFi parts do this.
The P2 may be able to have a Cal OSC, as Chip has improved the PVT details, and it then just needs a CalByte stored.
CalOSC is not so critical on a P2 price point part. It matters a LOT more on a 28c MCU !
P2 will most likely be used with Crystal or CMOS osc or Clipped Sine TCXO & Clipped Sine TCXO are quite cheap, for very good precision (±500ppb)
External Flash is low cost and small and flexible, but more important than where flash is, is keeping the boot times down as much as possible.
It appears P2 can boot from the new OctoFlash parts, as well as QuadSPI parts.
If I had to pick a missing feature on P2 around Clocks, it would be there is no Clock failure fall back. Some software standards require this.
eg after reset, there is no means to check Xtal osc is working, before you flip-over, and No osc watchdog.
An external clocked WDOG can manage the osc-watchdog side, but with no means to check Osc-ok, you simple repeat the WDOG cycles.