On July 6 Chip stated that the new test chip should go into a shuttle run in about 4 weeks.
I suspect this has not happened yet since Chip has been away. However, Chip did know about the China trip when he made this estimate, so maybe he had factored that in.
I read that as the test chip was done, and in the queue. ie it did not need any additional input from Chip, which means it should be 'in the FAB', right now ?
I wonder how much they can test, with this new test chip ?
On July 6 Chip stated that the new test chip should go into a shuttle run in about 4 weeks.
I suspect this has not happened yet since Chip has been away. However, Chip did know about the China trip when he made this estimate, so maybe he had factored that in.
I read that as the test chip was done, and in the queue. ie it did not need any additional input from Chip, which means it should be 'in the FAB', right now ?
I wonder how much they can test, with this new test chip ?
It's just the analog parts again like the last time isn't it? And the fuses.
It's just the analog parts again like the last time isn't it? And the fuses.
Yes, but I think this time is a full-pad-ring, as in the 'final' outer full custom silicon design.
So I'm taking from that they can test all pin's ADCs and DACs and the new RC Oscillators where Chip tuned the PVT side and bumped to 20MHz min from 20MHz typ.
Not sure if the expanded digital dividers for the VCO are in there, if not the issue becomes can the VCO drive external dividers ok ?
Some IccIO numbers should be possible too... and maybe ESD testing.
Yep, same as last time I believe. Chip will have had some tweaking done ... might have been the fuses in fact ...
I recall fuse problems around needing a Vpp, but on every IO pin, which is pretty much the kiss of death for end use.
Not sure of the final outcome, there - maybe they can re-test to confirm Vpp ( > 3.3V) is needed, and then swap to OnSemi OTP cell for fuses, now in the core.
In that case, I'd imagine the PAD ring design is not changed, but the fuse-signals are routed to GND.
And explain to every single company, startup, engineer that there is a completely documented and open source microcontroller called P1v (verilog) that anyone can use in FPGA, or implement in 22nm FD-SOI.
How it comes that since 2014 nobody have made a P8x32 substitute/clone?
(The answer is obvious: this is not a pentium or atmega328 ...)
No one has made a P8x32 clone for the simple reason it's expensive to turn it into silicon when they can buy the real thing, right now from Digikey for $8 a piece.
For a variant to be produced, there would have to be a serious demand for it to just recoup the investment in it.
In addition with the plethora of mcu's in the wild and more entering every month, the Prop doesn't stand out. ARM has a massive industry mind share, so most engineers will stick with what they know and it's generally ARM or something else from Microchip or NXP. Hobby wise the Arduino and it's many variations are the dominant chips. Now a day, Arduino encompasses everything from a Atmel 328 to PIC32's and even Digital Signal controllers.
This isn't the same market that existed when the Prop was first introduced, far from it.
That's the thing. "Arduino" is not a particular MCU or even particular board or even from the Arduino company.
Arduino is an IDE and a language and a bunch of libraries. Which over time have been made to work with many devices.
For example you can use the Arduino IDE to program the ESP32 WIFI devices.
Many vendors when introducing new gadgets have provided Arduino IDE integration in the hopes of attracting all the Arduino users. Quite a smart move, there is nothing more annoying than having to get familiar with a whole new IDE for every damn board one buys.
No one has made a P8x32 clone for the simple reason it's expensive to turn it into silicon when they can buy the real thing, right now from Digikey for $8 a piece.
Quite likely. The Prop market is not big enough to attract cloners.
For a variant to be produced, there would have to be a serious demand for it to just recoup the investment in it.
And why would anyone make a variant? If one is designing a chip and wanted some funky logic/IO or whatever in there one would design it into the hardware. There is no need for a multi-core Propeller in there when you can do that. At which point you may as well go with an ARM core or whatever that has great C compiler support.
In addition with the plethora of mcu's in the wild and more entering every month, the Prop doesn't stand out.
It's true that we are awash with MCU now a days. But still the Prop stands out. It can do things many of those cannot.
Many vendors when introducing new gadgets have provided Arduino IDE integration in the hopes of attracting all the Arduino users. Quite a smart move, there is nothing more annoying than having to get familiar with a whole new IDE for every damn board one buys.
Yes, but "Arduino IDE integration" means only Edit and Download, there is no Simulation or Debug, right ?
Many vendors when introducing new gadgets have provided Arduino IDE integration in the hopes of attracting all the Arduino users. Quite a smart move, there is nothing more annoying than having to get familiar with a whole new IDE for every damn board one buys.
Yes, but "Arduino IDE integration" means only Edit and Download, there is no Simulation or Debug, right ?
Well, really edit, compile, link, download. It integrates the compiler toolchain.
That's the thing. "Arduino" is not a particular MCU or even particular board or even from the Arduino company.
Arduino is an IDE and a language and a bunch of libraries. Which over time have been made to work with many devices.
For example you can use the Arduino IDE to program the ESP32 WIFI devices.
Many vendors when introducing new gadgets have provided Arduino IDE integration in the hopes of attracting all the Arduino users. Quite a smart move, there is nothing more annoying than having to get familiar with a whole new IDE for every damn board one buys.
this might have worked for the Propeller as well,
when done at the right time.
the super Propellerino
I still think it is a lost marketing opportunity that when I search for Arduino on Ebay no Propellers come up ;-)
Heck they do not even show up when I search for Parallax Propeller ...
Seems to me Parallax does not want to sell them :-((
It would be so easy having always at least one Propeller product on Ebay - tagged with Arduino of course ;-) - so people will stumble over it and get interrested.
I my self discovered the Propeller only very accidentally - luckily
There was/is some some of the Arduino standard library supported for it. I'm not sure how far along integration with the Arduino IDE got.
In hind sight perhaps it should have been called the "Produino" with full IDE support available. Still at 50 dollars it has stiff competition from the hundreds of other Arduino like devices are available for peanuts.
... Now a day, Arduino encompasses everything from a Atmel 328 to PIC32's and even Digital Signal controllers.
I didn't know that! Is there integration of all those at the IDE level as well?
There are various forks of the IDE that support chips from TI(energia.nu), Microchip(PIC32 28 pin version) and those $3 ARM boards on Ebay. It's really amazing how it took off. Vendors seem to see it as a way introducing new hardware to people.
The test chip shuttle is scheduled for September 15th. That's still four weeks away. We intended to run our latest test chip on there.
In the interim, we've asked OnSemi to do the synthesis work for us, as soon as they can, since they have everything under one roof (including the RAM/ROM IP) and should be able to do it cheaper than anyone else. I figure the risk of the latest test chip not working is very low, so it is safe to proceed with final synthesis - especially in light of how much time it would take to get a test chip back and then do the synthesis.
As for the fuses, I'm still not sure how to handle this. They have a fuse IP block, but it would require a lot of integration work on our end and, to me, the risk seems much higher than using what we've already got, though our current solution would require every VIO pin to be a temporary 4.5V VPP pin, necessitating a programming fixture for apps that didn't accommodate the VPP requirement, themselves. I know this is a pain, but remember that this whole fuse issue can be ignored, if the customer is not caring about code protection. Even the OnSemi fuse IP would require a 5V pin for programming (aside from the integration complexities). So, code protect should be able to be done reliably, but it may require pre-solder device handling.
The test chip shuttle is scheduled for September 15th. That's still four weeks away. We intended to run our latest test chip on there.
In the interim, we've asked OnSemi to do the synthesis work for us, as soon as they can, since they have everything under one roof (including the RAM/ROM IP) and should be able to do it cheaper than anyone else. I figure the risk of the latest test chip not working is very low, so it is safe to proceed with final synthesis - especially in light of how much time it would take to get a test chip back and then do the synthesis.
As for the fuses, I'm still not sure how to handle this. They have a fuse IP block, but it would require a lot of integration work on our end and, to me, the risk seems much higher than using what we've already got, though our current solution would require every VIO pin to be a temporary 4.5V VPP pin, necessitating a programming fixture for apps that didn't accommodate the VPP requirement, themselves. I know this is a pain, but remember that this whole fuse issue can be ignored, if the customer is not caring about code protection. Even the OnSemi fuse IP would require a 5V pin for programming (aside from the integration complexities). So, code protect should be able to be done reliably, but it may require pre-solder device handling.
Chip,
Have you asked about OnSemi Flash/EEPROM/OTP IP ?
This could solve the fuse issue as well as give a lot of benefits. There are so many micros with huge internal Flash, it will make the P2 look obsolete right from the start. It doesn't even need to be hub memory mapped if that helps, just serial like the ROM.
BTW getting OnSemi to do the synthesis seems like a smart move.
Am I correct in understanding that the chip shuttle will be a full P2, not just the frame???
As for the fuses, I'm still not sure how to handle this. They have a fuse IP block, but it would require a lot of integration work on our end and, to me, the risk seems much higher than using what we've already got, though our current solution would require every VIO pin to be a temporary 4.5V VPP pin, necessitating a programming fixture for apps that didn't accommodate the VPP requirement, themselves. I know this is a pain, but remember that this whole fuse issue can be ignored, if the customer is not caring about code protection. Even the OnSemi fuse IP would require a 5V pin for programming (aside from the integration complexities). So, code protect should be able to be done reliably, but it may require pre-solder device handling.
What about the OnSemi OTP block ? That does not mention needing an external Vpp ?
Even a single Vpp pin is rapidly becoming a thing of the past, so should ideally be avoided on any NEW chip design.
Multiple-pin Vpp is to me a total kiss of death. No one does that now, and it looks like you simply made a mistake. The chip becomes VERY hard to use.
High volumes are NOT going to want to do pre-solder handling, your only hope there is to offer a programming service, and many will not be able to get sign-off on that either.
An OTP block, that does not need Vpp and that does allow Serial Number and Calibrate factory constants, and user OTP is much more sale-able.
Am I correct in understanding that the chip shuttle will be a full P2, not just the frame???
My reading is the test chip shuttle scheduled for September 15th, is the P2 Custom PAD frame, ie excludes final synthesis or core logic, but includes the full custom Analog PAD Ring and all Analog/Fuse/PinIO support, and PLLs and Dividers and PFC and RC Oscs.
Details of how that is bonded for test access, or if this will allow full speed IO testing, are sparse.
Maybe it's a 144 or 176 pin package ?
Whats the effect of this 4.5v Vpp on the abs max rating of the silicon, Chip? Would it mean an abs max of say 5v and therefore some kind of limited 5v compatibility tolerance? Or is it only for some brief time
I'm not too worried about the multiple pins needing a temporary rise, it sounds like FPGAs where many of the Vccio1..8 etc are tied together anyway. If we use an adjustable LDO it may just involve a parallel resistor on the lower leg of the adjustment setpoint, which the prop could control. This isn't a big price to pay for fuses/code protection.
Yes, Lachlan, we'd need to raise the 3.3V supply to 4.5V For 1ms to blow each fuse. It's beyond normal operating spec but wouldn't hurt anything, just scare everyone.
Am I correct in understanding that the chip shuttle will be a full P2, not just the frame???
My reading is the test chip shuttle scheduled for September 15th, is the P2 Custom PAD frame, ie excludes final synthesis or core logic, but includes the full custom Analog PAD Ring and all Analog/Fuse/PinIO support, and PLLs and Dividers and PFC and RC Oscs.
Details of how that is bonded for test access, or if this will allow full speed IO testing, are sparse.
Maybe it's a 144 or 176 pin package ?
Correct. Just the pad frame circuits bonded into a 128-pin package, same as before.
Am I correct in understanding that the chip shuttle will be a full P2, not just the frame???
My reading is the test chip shuttle scheduled for September 15th, is the P2 Custom PAD frame, ie excludes final synthesis or core logic, but includes the full custom Analog PAD Ring and all Analog/Fuse/PinIO support, and PLLs and Dividers and PFC and RC Oscs.
Details of how that is bonded for test access, or if this will allow full speed IO testing, are sparse.
Maybe it's a 144 or 176 pin package ?
Correct just the pad frame circuits bonded into a 128-pin package, same as before.
I don't understand. In a message above you said this:
Yes, it would be the full P2 with 16 cogs, 64 I/O's, and 512KB RAM.
Are there two different shuttles you're talking about?
Am I correct in understanding that the chip shuttle will be a full P2, not just the frame???
My reading is the test chip shuttle scheduled for September 15th, is the P2 Custom PAD frame, ie excludes final synthesis or core logic, but includes the full custom Analog PAD Ring and all Analog/Fuse/PinIO support, and PLLs and Dividers and PFC and RC Oscs.
Details of how that is bonded for test access, or if this will allow full speed IO testing, are sparse.
Maybe it's a 144 or 176 pin package ?
Correct just the pad frame circuits bonded into a 128-pin package, same as before.
I don't understand. In a message above you said this:
Yes, it would be the full P2 with 16 cogs, 64 I/O's, and 512KB RAM.
Are there two different shuttles you're talking about?
Yes. We can run the new test chip right now and then push the complete chip through the next shuttle, if we are done.
Am I correct in understanding that the chip shuttle will be a full P2, not just the frame???
My reading is the test chip shuttle scheduled for September 15th, is the P2 Custom PAD frame, ie excludes final synthesis or core logic, but includes the full custom Analog PAD Ring and all Analog/Fuse/PinIO support, and PLLs and Dividers and PFC and RC Oscs.
Details of how that is bonded for test access, or if this will allow full speed IO testing, are sparse.
Maybe it's a 144 or 176 pin package ?
Correct just the pad frame circuits bonded into a 128-pin package, same as before.
I don't understand. In a message above you said this:
Yes, it would be the full P2 with 16 cogs, 64 I/O's, and 512KB RAM.
Are there two different shuttles you're talking about?
Yes. We can run the new test chip right now and then push the complete chip through the next shuttle, if we are done.
Cool! Sounds great. Does that mean you'd have the results of the second shuttle by the end of the year?
I'm not too worried about the multiple pins needing a temporary rise, it sounds like FPGAs where many of the Vccio1..8 etc are tied together anyway. If we use an adjustable LDO it may just involve a parallel resistor on the lower leg of the adjustment setpoint, which the prop could control. This isn't a big price to pay for fuses/code protection.
The problem is worse when P2 is part of a larger system, along with many 3v3 parts, - many of those will not tolerate 4v5 rails...
More common is a 4.0V Absolute max rating.
Keep in mind any fuse-blow will likely have high dI/dT and cause some Vcc overshoot in a design too.
Comments
I wonder how much they can test, with this new test chip ?
Yes, but I think this time is a full-pad-ring, as in the 'final' outer full custom silicon design.
So I'm taking from that they can test all pin's ADCs and DACs and the new RC Oscillators where Chip tuned the PVT side and bumped to 20MHz min from 20MHz typ.
Not sure if the expanded digital dividers for the VCO are in there, if not the issue becomes can the VCO drive external dividers ok ?
Some IccIO numbers should be possible too... and maybe ESD testing.
I recall fuse problems around needing a Vpp, but on every IO pin, which is pretty much the kiss of death for end use.
Not sure of the final outcome, there - maybe they can re-test to confirm Vpp ( > 3.3V) is needed, and then swap to OnSemi OTP cell for fuses, now in the core.
In that case, I'd imagine the PAD ring design is not changed, but the fuse-signals are routed to GND.
I think he is much better there. How many years he had been without holidays?. I hope he will take a long (and well deserved) rest.
Also, If I were him I would take a month trip to Chengdu:
http://www.eetimes.com/document.asp?doc_id=1331773
https://www.globalfoundries.com/news-events/press-releases/globalfoundries-and-chengdu-partner-expand-fd-soi-ecosystem-china
And explain to every single company, startup, engineer that there is a completely documented and open source microcontroller called P1v (verilog) that anyone can use in FPGA, or implement in 22nm FD-SOI.
How it comes that since 2014 nobody have made a P8x32 substitute/clone?
(The answer is obvious: this is not a pentium or atmega328 ...)
No one has made a P8x32 clone for the simple reason it's expensive to turn it into silicon when they can buy the real thing, right now from Digikey for $8 a piece.
For a variant to be produced, there would have to be a serious demand for it to just recoup the investment in it.
In addition with the plethora of mcu's in the wild and more entering every month, the Prop doesn't stand out. ARM has a massive industry mind share, so most engineers will stick with what they know and it's generally ARM or something else from Microchip or NXP. Hobby wise the Arduino and it's many variations are the dominant chips. Now a day, Arduino encompasses everything from a Atmel 328 to PIC32's and even Digital Signal controllers.
This isn't the same market that existed when the Prop was first introduced, far from it.
I disagree. I am not aware of a single chip that is better suited to motion control.
http://www.marketsandmarkets.com/PressReleases/motion-control.asp
Arduino is an IDE and a language and a bunch of libraries. Which over time have been made to work with many devices.
For example you can use the Arduino IDE to program the ESP32 WIFI devices.
Many vendors when introducing new gadgets have provided Arduino IDE integration in the hopes of attracting all the Arduino users. Quite a smart move, there is nothing more annoying than having to get familiar with a whole new IDE for every damn board one buys.
Yes, but "Arduino IDE integration" means only Edit and Download, there is no Simulation or Debug, right ?
I suspect Arduino users have never heard of "simulation" or "debug".
this might have worked for the Propeller as well,
when done at the right time.
the super Propellerino
I still think it is a lost marketing opportunity that when I search for Arduino on Ebay no Propellers come up ;-)
Heck they do not even show up when I search for Parallax Propeller ...
Seems to me Parallax does not want to sell them :-((
It would be so easy having always at least one Propeller product on Ebay - tagged with Arduino of course ;-) - so people will stumble over it and get interrested.
I my self discovered the Propeller only very accidentally - luckily
http://www.instructables.com/id/Propeller-Power-for-the-Arduino/
Oh it's still available:
http://www.ic0nstrux.com/Propeller-ASC#.WZMBoKxidhE
https://www.parallax.com/product/32214
There was/is some some of the Arduino standard library supported for it. I'm not sure how far along integration with the Arduino IDE got.
In hind sight perhaps it should have been called the "Produino" with full IDE support available. Still at 50 dollars it has stiff competition from the hundreds of other Arduino like devices are available for peanuts.
There are various forks of the IDE that support chips from TI(energia.nu), Microchip(PIC32 28 pin version) and those $3 ARM boards on Ebay. It's really amazing how it took off. Vendors seem to see it as a way introducing new hardware to people.
In the interim, we've asked OnSemi to do the synthesis work for us, as soon as they can, since they have everything under one roof (including the RAM/ROM IP) and should be able to do it cheaper than anyone else. I figure the risk of the latest test chip not working is very low, so it is safe to proceed with final synthesis - especially in light of how much time it would take to get a test chip back and then do the synthesis.
As for the fuses, I'm still not sure how to handle this. They have a fuse IP block, but it would require a lot of integration work on our end and, to me, the risk seems much higher than using what we've already got, though our current solution would require every VIO pin to be a temporary 4.5V VPP pin, necessitating a programming fixture for apps that didn't accommodate the VPP requirement, themselves. I know this is a pain, but remember that this whole fuse issue can be ignored, if the customer is not caring about code protection. Even the OnSemi fuse IP would require a 5V pin for programming (aside from the integration complexities). So, code protect should be able to be done reliably, but it may require pre-solder device handling.
Chip,
Have you asked about OnSemi Flash/EEPROM/OTP IP ?
This could solve the fuse issue as well as give a lot of benefits. There are so many micros with huge internal Flash, it will make the P2 look obsolete right from the start. It doesn't even need to be hub memory mapped if that helps, just serial like the ROM.
BTW getting OnSemi to do the synthesis seems like a smart move.
Am I correct in understanding that the chip shuttle will be a full P2, not just the frame???
I will ask more about other NV options.
What about the OnSemi OTP block ? That does not mention needing an external Vpp ?
Even a single Vpp pin is rapidly becoming a thing of the past, so should ideally be avoided on any NEW chip design.
Multiple-pin Vpp is to me a total kiss of death. No one does that now, and it looks like you simply made a mistake. The chip becomes VERY hard to use.
High volumes are NOT going to want to do pre-solder handling, your only hope there is to offer a programming service, and many will not be able to get sign-off on that either.
An OTP block, that does not need Vpp and that does allow Serial Number and Calibrate factory constants, and user OTP is much more sale-able.
My reading is the test chip shuttle scheduled for September 15th, is the P2 Custom PAD frame, ie excludes final synthesis or core logic, but includes the full custom Analog PAD Ring and all Analog/Fuse/PinIO support, and PLLs and Dividers and PFC and RC Oscs.
Details of how that is bonded for test access, or if this will allow full speed IO testing, are sparse.
Maybe it's a 144 or 176 pin package ?
Whats the effect of this 4.5v Vpp on the abs max rating of the silicon, Chip? Would it mean an abs max of say 5v and therefore some kind of limited 5v compatibility tolerance? Or is it only for some brief time
I'm not too worried about the multiple pins needing a temporary rise, it sounds like FPGAs where many of the Vccio1..8 etc are tied together anyway. If we use an adjustable LDO it may just involve a parallel resistor on the lower leg of the adjustment setpoint, which the prop could control. This isn't a big price to pay for fuses/code protection.
Correct. Just the pad frame circuits bonded into a 128-pin package, same as before.
Yes. We can run the new test chip right now and then push the complete chip through the next shuttle, if we are done.
The problem is worse when P2 is part of a larger system, along with many 3v3 parts, - many of those will not tolerate 4v5 rails...
More common is a 4.0V Absolute max rating.
Keep in mind any fuse-blow will likely have high dI/dT and cause some Vcc overshoot in a design too.