From what JMG put here, and the information I've looked at, and others have talked about, this process has a fairly low static drain. The smaller you get, the bigger that problem becomes. At the size we are, it's not a big deal.
Somebody will correct me on that, if I'm wrong. Hope not. But I really could be.
As for microprocessor development, yes! We are in the past, but that's what it takes to bootstrap new entities into the market. Or it takes a lot of dollars. We can make this happpen incrementally. I think we must.
This entire discussion has yielded NO options that do not cost us a lot of time and money, both of which could be selling this nice design. This discussion has also yielded the information that there are use cases and buyers we can sell to.
We did the work, it was fun, now we have to own it, and fund the future.
If 65nm reduce power consumption and may speed up to ~250MHz or more, compare this price to 8x 250MHz ARM MCU's or one 1-2GHz CPU. An 1GHz Cortex A8 cost ~44$.
A Prop2 built in 65nm would have a raw manufacturing cost of about $2, which is the same cost as a 180nm chip in a low-power package. A 180nm chip in a 5W BGA would probably cost $5 to make.
To build Prop2 in 65nm would cost about $1M. This is more than Parallax can afford, of course.
I asked OnSemi if they'd be interested in partnering in some way, so that they would make this big investment and we would share in the outcome. I don't know if they'd be interested in doing that. With a partner like them, we could really knock out some nice products, not having to worry about so many implementation details, ourselves. They seem pretty smart, to me, about how they go about designs. When I explained that we have special I/O pads that need to be implemented in whatever process we wind up using, they said right away that we'd need their design kit, we'd do a minimum-sized test die in a shuttle run, repeating, if necessary, to prove our I/O's, and once proven, they'd integrate them into their design flow, which has all the checks needed for reliable closure. Cool!
By the way, that "lock them in the room for a week" I put here earlier? Doing that, right now, would very significiantly improve the chance of partnering. They will need to see a risk / reward case, and some known demand.
For them, the investment is multiplied by their internal costs, which makes it less. If we respond with a favorable risk profile, it could be compelling! Just saying.
This is one option that doesn't cost us too much time and money, but it has a pay off in the more near term than slogging through moving enough of the current P2 and process does. It's attractive and very worth doing the work to secure. Serious work.
I'm not sure I get the motivation for this multiple P2 idea.
What you are suggesting is that the chip be cut in half and the clock speed dropped. Then, to get performance/functionality back when we need it lets use more than one chip.
This makes not make sense to me yet because:
a) Building boards for two chips is always going to be bigger and more expensive than one.
b) This does not save you any power. you have just spread it around. OK that's good from a heat concentration point of view.
c) Rearranging code or writing new code for a 2 chip system is never going to be as simple as the single chip solution.
d) You are going to waste a COG in each device just taking care of communications between them.
The possibility of "massively parallel" systems is a myth. Who on earth is going to build a 1024 node Propeller system? The guys who want compute performance have far easier and more economical ways to get it (Did I mention my Parallella board has arrived, 16 floating point units and an ARM all for 100 dollars.) Who is going to want 80,000 odd I/O pins?
I really think you should envision a Kickstarter campaign : "Help us manufacture the most versatile microcontroller!". The people would pledge for a QuickStart 2 board containing a Prop II. I'm sure people would really want to back this project, given the success of the P8X32A and the current advancement status of the Prop II. You said you wanted people to be beta testers, why not having pledge level with DE2 and the adapter board, and further pledge level with your custom FPGA board?
Chip listed cutting the design in half as an option.
I personally would prefer a P2 that has better Cog bandwidth at the expense of fewer Cogs. So I saw the heat issue as
an opportunity and not really a problem at all.
All of my designs use multiple boards that's just the way I like to build things.
True story:
When Libby and I were young we bought an abandoned building. We spent about $100,000 for an architectural design.
By the time the design was done, we didn't have enough money for the build.
So, we scrapped the design, and with a few guys started throwing up walls. When we backed ourselves into
a corner, we tore a few walls down and put up new ones. When we were done, we had exactly what we wanted and
it cost a fraction of the $100,000 we spent on the architect. Of course the people building the walls and then tearing
them down again got a little frustrated.
To me this design process matches what I have found works best in my own experience.
You guys are great and it looks like Chip is close to turning the page on this chapter.
Pebble and Ouya did have very general broad appeal among early adopters who had money to spend.
Is that true for P2? If so who?
Then if you go to https://www.kickstarter.com/discover/categories/technology/most-funded
you will see that some electronics project do quite well : Parallella 0.9M$ UDOO 0.64M$ HackRF 0.6M$ Spark Core 0.57M$ MicroView 0.45M$ and still 13 days to go.
If it can get Parallax the little financial push to grant a 65nm chip...
The Pono Music project got 5.3M$ to date here is what the Founder has to say about his Kickstarter experience:
Here we are at the halfway point. My experience here at Kickstarter has been life changing. After banging my head against the walls of venture capitalism for almost three years, dealing with business experts who didn’t understand what we were trying to accomplish; rescue the art of recorded sound and make great music available into the future, I found you people. You are the ones who understand what this is. You have proven it with your amazing support.
When we blew through our goal and actually doubled it on the first day, you changed my life. I will never forget that. This is just the beginning of a long road towards our goal of rescuing the music, all of it, from Cab Calloway to Sinatra, the Beatles and Rolling Stones, to Nirvana and Patti Smith, to Jay Z and Rihanna, and beyond. All of this music is the world’s history, the cultural creations of artists since the beginning of recorded sound. Now it can be preserved, if we do our job right, for future generations to hear and feel, not just recognize.
We are working now with Rap and R&B music sources as well as Country Music and Classical, in an effort to show you how great all music can and will sound with PONO.
Thanks for your help. We are very grateful for it. Obviously we can’t do this without you.
Neil Young
Pono
Kickstarter is about what people (hobbyist?) want, and in the microcontroller world, I don't know many companies who care about us. They are far more interested in making cash with high volume. The user experience with Parallax is incredible and we have to spread the word about that.
Problem is that now a days people will be comparing to things like STM32 that drink 260uA per mega hertz and run up to 180MHz. That's 0.2 watts !
So we have 8 COGS, that would be only 1.6 watts.
Yeah Heater. That sucks. We don't have the process and resources right now to even come close to that metric. So, we just don't, unless some deal can be struck with OnSemi, or we get some magic crowd source thing, and frankly, I'm nervous about that, because it typically takes us a loooooong time to sort things out. Last thing we want is an angry mob. I would rather have the power disadvantage.
So then, we don't worry about it as I mentioned above. What we do have is a cool design, done in an affordable process for us, and it's got a lot of capabilities! Again, the possible. I'm not wanting to entertain how the magic power fairy didn't touch this P2. It was never, ever going to compete on the metric you just put there. We could have abandoned the design years ago, if that were the hard requirement.
But it wasn't the hard requirement. So now here we are. Time to own up and figure this thing out. If this were my design effort, and the money spent, etc... you can bet your Smile, it would get figured out to fund the future. That is what needs to happen.
Rather than look at the negatives, this discussion gets really simple: Who isn't so worried about power? They are now attractive prospects and we need to get after 'em.
Or, of those who are worried about power, how much of the performance do they need? We get after them too.
If it can get Parallax the little financial push to grant a 65nm chip...
Yeah, if it's enough. I'm totally up for a shrink, and in fact, think the shrink is the necessary thing to continue with volume in hobby land. I don't think it's needed for other opportunities.
With it shrunk, will it be attractive enough?
That discussion is as important as the other ones. And it also means some feature commits and a date too. Things all necessary at this point.
When I wrote the GUI for the original Scribbler, I got quite a way into the programming (thousands of lines) when I realized I had taken the wrong approach. I was faced with either pushing ahead or starting over from scratch. Well, not from scratch, really, because that would have ignored the context of all that I had learned from doing it "wrong." I chose to start over. Had I not had the one false start, I may never have hit upon the technique I ended up using, and the results may not have turned out as well. Moreover, had I started with the technique I ultimately used, it would have taken much longer than it did in the context of my previous attempt.
What I'm getting at is that there is no such thing as "failure" if you learn and derive inspiration from what you've done and apply those lessons going forward. As a consequence, I'm never afraid to start over on a project that has gotten into trouble and will only get into more trouble if I forge ahead instead of regrouping. In the long run the results are better, and the total effort is usually less than if I had continued on the original trajectory.
Parallax may want to consider doing the 180nm P2 first, and then do a 65nm version later on. This way the revenue from the 180nm version will help to fund the 65nm version. There's less risk with the 180nm version, and the lessons learn from it will reduce the risk when developing the 65nm version.
Crowd sourcing: Goal to make up the gap from what Parallax can afford investing in a 180NM fab P2 to what it will cost for 65NM fab
Funding levels and rewards (numbers are estimated):
$5 - Thanks for your support - net to Parallax - $5
$15 - Thanks an P2 T-shirt - net to Parallax $7 (cost $8 for t-shirt and shipping)
$30 - Thanks, T-Shirt and P2 chip from production run - net to Parallax $12 (cost: $8 t-shirt, $10 for chip)
$75 - Thanks, T-Shirt and P2 Dev board - net to Parallax $15 (cost: $8 T-shirt, $52 for dev board)
$130 - Thanks, T-Shirt, DE0 Nano, first run P2 chip - net to Parallax - $12 (cost: $8 shirt, $10 chip, $100 Nano)
$200 - Thanks, Shirt, DE0 Nano, P2 Dev board - net to Parallax - $40 - (Cost: $8 shirt, $100 nano, $52 dev board)
$500 - Thanks, Shirt, Parallax FPGA board, P2 Dev Board - net to Parallax - $90 - (Cost: $8 shirt, $52 dev board, $350 FPGA board)
$1000 - Thanks, Shirt, 2 Parallax FPGA boards, 2 P2 Dev boards - net to Parallax - $ 78 - (Cost: $8 shirt, $104 dev boards, $700 FPGA boards)
$5000 - Thanks, you're a fanatic, you get several dev boards and a trip to the Walnut Farm when it is all done!! - net to Parallax $2500
OK, get the idea?
Now:
- The Nano could be an issue since you can't run 1 full COG on it at the moment - if somebody buys in to play, you need to be able to keep them in the game.
- The cost figures I included are fictional Parallax costs (parts, labor, shipping, NRE, overhead, everything) - there is no profit and hopefully no loss
- Parallax gets to put the "Net" amount toward the P2 project, everything else is spent or put in escrow to cover final rewards.
How many do you need to sell at each level to make $1M less Parallax contribution to funding??
How to you handle your crowd sourcing when it turns into MOB sourcing if there are delays?
How do you handle Angry Mob sourcing if something major happens (bad shuttle run, major bug in silicon (worst case), delays because of problems found in FPGA testing)?
If you need a second shuttle run, how do you fund it? You now have an angry mob, you can't just regroup, refocus and start putting profits from sales toward the next shuttle. You need to pony up hard cash you may not have because you have waiting investors.
I'd like to see if anyone can come up with target investor numbers for the various reward levels - it could be interesting to see how hard it is to raise some % of $1M.
and of course, the big question (back to where we are now) - what do you do if the crowd sourcing experiment doesn't raise the cash? You still need a plan B.
Parallax may want to consider doing the 180nm P2 first, and then do a 65nm version later on. This way the revenue from the 180nm version will help to fund the 65nm version. There's less risk with the 180nm version, and the lessons learn from it will reduce the risk when developing the 65nm version.
Dave, I like the way you think!
From an earlier post of mine:
There's a lot to be tested still, there's a lot to be developed still before it is a viable system to use and sell. Retrenching won't change those facts, If you redesign, there is still the same amount of testing and development to do. You'll have a new design, you'll have added 2 years to the clock and you may have a similar or worse situation and you'll still have a year or more on top of that to get to market....that makes everyone 3 years older, 3 years less enchanted, 3 years distracted with other shiny things that are doing the job for them. 3 years is a LONG time.
Get something in the hands of the people that can use it. Get prototypes out, get dev boards out, get chips out. Ok, so the dev boards run warm, they let people actually get hands-on experience, they let software people actually test and implement their neat ideas. Software dreams can become reality. Hardware designers that understand the power relationships can start designing real hardware that will work with a P2A and will just work better with a P2B.
There's a lot of productive and necessary work to do and a lot that can be done with a warm chip!
What I'm getting at is that there is no such thing as "failure" if you learn and derive inspiration from what you've done and apply those lessons going forward. As a consequence, I'm never afraid to start over on a project that has gotten into trouble and will only get into more trouble if I forge ahead instead of regrouping. In the long run the results are better, and the total effort is usually less than if I had continued on the original trajectory.
And
Parallax may want to consider doing the 180nm P2 first, and then do a 65nm version later on. This way the revenue from the 180nm version will help to fund the 65nm version. There's less risk with the 180nm version, and the lessons learn from it will reduce the risk when developing the 65nm version.
Is right where I'm at on it too.
Of course Phil. However, say a do over takes 4 years? That's a failure mode potential running very high, and that's really what I'm getting at.
A Prop2 built in 65nm would have a raw manufacturing cost of about $2, which is the same cost as a 180nm chip in a low-power package. A 180nm chip in a 5W BGA would probably cost $5 to make.
Are those $2 prices for a thermal PAD TQFP128, as you were planning, or something even lower in price ?
Is that $5 BGA a real price, or an estimate - seems a lot to add for a package ?
Or is it an Alumina substrate to aggressively move the heat ?
The Thermal info I looked at, suggests a BGA does not gain that much, and the main thermal driver is the 'sea of vias' into the inner layers. A large die like the P2 helps a little here.
What does NRE tooling for a special TQFP128 (0.4 or 0.5) or TQFP144 (0.4 or 0.5) cost ?
ie one with the ideal PAD size, to spread heat from the die, before it hits the 'sea of vias'
I've seen packages with exposed pads on the TOP as well. My gut feeling is ~3W is practical, still in TQFP.
I asked OnSemi if they'd be interested in partnering in some way, so that they would make this big investment and we would share in the outcome. I don't know if they'd be interested in doing that. With a partner like them, we could really knock out some nice products, not having to worry about so many implementation details, ourselves. They seem pretty smart, to me, about how they go about designs. When I explained that we have special I/O pads that need to be implemented in whatever process we wind up using, they said right away that we'd need their design kit, we'd do a minimum-sized test die in a shuttle run, repeating, if necessary, to prove our I/O's, and once proven, they'd integrate them into their design flow, which has all the checks needed for reliable closure. Cool!
Problem with 65nm is that $1M is a (rough) per-pass cost, so $1M is not guaranteed to result in release level silicon.
This is one reason I would go with 180nm first, and then do 65nm after problems have been worked out and more is learned about the development process. Ideally, the 180nm and the 65nm version should be functionally equivalent, but it's likely that some new features would be added to the 65nm version. The number of new features should be minimized to reduce the risk.
Potentially misprogramming my P2 collapses my power supply or fries my board !
and merging with my earlier suggestion of Counters faster than the Core (for power saving reasons) .
The P2 has fuses.
this idea of Packaging in more than one way opens.
* Lowest cost package, with lower power and a Ceiling on fMAX and VCore.
Possibly a Fuse could be used to allow high-speed timing precision, while the opcodes run slower.
ie the Fuse presents the highest power combinations of PLL + Core speeds.
OR a PCB with a (eg 100MHZ) Vcc, would further limit any power profiles, but at the cost of some precision.
Personally, I would prefer a 160MHz timing precision and 80MHz core, for example.
* Power focused package, allows Higher fMAX and VCore, no limits, able to be cooled to run everything at full speed.
- and I would look very hard for a package solution that enables both, with modest cost impact.
eg A dual Thermal PAD (top and Bottom) offers a number of cooling choices, at (hopefully) lower cost than a $3 adder Special BGA.
I agree, let's not panic and get this done at 180nm and get rolling.
The 5W estimate is not 'real world'. Make the shuttle run, package as Chip best sees fit, and lets get these things on some boards and do some REAL real world testing. Then Chip and Ken will have good solid data to use for writing up an official 'release' specification that maximizes the marketing potential for this great chip.
If a one chip / three performance range approach does not work then perhaps they can look at three different chip packages.
20MHz - Low Power, 160Mips 8 core mini monster. This is, in effect, pretty much what the original 'improved' P1 concept was.
80MHz - Medium Power, 640Mips 8 core monster. With HUBEXEC, tasks, threading, SERDES, etc, this is a killer chip even at 80MHz.
160MHz - High Power, 1280Mips 8 core GODZILLA! This is an absolute BEAST of a chip and even with the power/heat design constraints will have a lot of application possibilities.
EDIT: All three would be the same 'chip' internally. Only difference would be max selectable clock speed and package type (TQFP128 @ 20/80, BGA @ 160). Yes, a 20MHz version would need 80MHz internal clocking (forgot about that).
A Prop2 built in 65nm would have a raw manufacturing cost of about $2, which is the same cost as a 180nm chip in a low-power package.
That sounds like heaven. How to get there?
@FredBlais,
Kickstarter is about what people (hobbyist?) want,
I find it fascinating. How many hobbyists want a chip with 16 or 64 floating point cores? Or would know what to do with one if they had one? But still Parallella exceeded their expectations. To the tune of 800 thousand dollars or so. Seems Kickstarter is not all about hobbyists in the usual sense.
@potatohead
Last thing we want is an angry mob.
I have not seen any "angry mobs" so far on Kickstarter. The deal is somebody asks for money to do something. You decide if they are trustworthy and competent and lay down your cash. If it does not work out, oh well, that's my silly fault for putting money on the wrong horse.
I put a hundred and something dollars on Parallella. After checking their track record it seemed reasonable bet. After one year of delays I thought it was a bust. But lo Parallella is now shipping what they promised.
There were no "angry mobs" in that long year of waiting.
I'm not saying Kickstarter is the way to go. But it might me of course...
@Phil
What I'm getting at is that there is no such thing as "failure" if you learn...
Whilst I love the "Nike" philosophy actually it is possible to fail. When all the money is blown, all the employees are let go, when you have to sell the farm to survive. Sometimes there is no coming back.
I'm "Heater" give me the chip now. Hot as it might be. I feel sure that Bill has a point. The worst case of 5W is not where we will be.
If a one chip / three performance range approach does not work then perhaps they can look at three different chip packages.
20MHz - Low Power, 160Mips 8 core mini monster. This is, in effect, pretty much what the original 'improved' P1 concept was.
80MHz - Medium Power, 640Mips 8 core monster. With HUBEXEC, tasks, threading, SERDES, etc, this is a killer chip even at 80MHz.
160MHz - High Power, 1280Mips 8 core GODZILLA! This is an absolute BEAST of a chip and even with the power/heat design constraints will have a lot of application possibilities.
Three does not make much sense, as you are either thermally active, or you are not.
You have also mentioned more peripheral choices, which is more silicon variations. Best avoided.
20MHz P2, with matching Vcc, will be quite low power, but needs the caution that the present P1 has 80MHz timing, with a 20 MOP COG
A P2 with less precision, is not viable, but it is relatively easy to have a P2 with Timers at 80MHz and 20 MOP COGs
More marketable is 100MHz timing and 25M MOP COGs, but even that will be well inside any package Power envelope. (Of course, users can lower the Clock/Vcc if they need less )
Quite likely in a std (original) thermal TQFP128 would be something up to at least
100MHz timing and 1 x 100 MOP COG, and 7 x 50 MOP COGs,
and then there is whatever is possible, with serious thermal design. (this does need COG temperature sense )
This problem is like trying to fit a large block V8 in a mini. A lot of you guys are essentially saying things like "lets change the spark plug wires, that'll make it fit" or "if we use a different fuel injection system, it'll work" or "let's paint the block blue instead of red, then it'll surely fit". The real solutions are more dramatic like switch to a 4 banger, reduce the engine to a small block with much smaller bore pistons, or pick a different car to put the large block V8 into.
The problem with stepping back to 4 cogs may be seen the same as going from a V8 to a V4. Most people may not need all that V8 power, but fear that V4 is too little.
My dad has a Lancia Apia with a V4. A great little car, but you just couldn't make it up some hills in San Francisco with 4 people in it.
++++++++++++++++
On the other hand, we have seen a big expansion of power hungry programing features of recent that also demand a lot more explaination to the user. The device might not only be 5 watts, but too challenging for wide spread popularity in the initial launch.
So cutting back some of the complexity, trying to keep all the originally promised features with maybe doubling the RAM (always a desired boost) might be prudent.
Don't be to greedy or ambitious. Don't get too far ahead of what most of your customers can learn.
Just have it compare as significantly better than the ArduinoDUE in terms of resources and you may avoid a lot of silly negatives from that crowd.
I'll take the P2 as it is. BUT I'm a hobbyist and not the market the P2 needs to be successful for Parallax. The $64000 question is how do you market a hot potato of a chip like the P2 in a field dominated by power sipping ARM's especially when they need millions in sales to recoup their investment.
In case you folks have forgotten, they've put in $4,000,000 into it.
That's a lot for a small company.
Do you push forward in a market where this particular flaw will show up like a clown car at a circus or do you hope to find a guardian angel(VC or OnSemi) to bail out your design? These probably have their own risks as well, especially with a VC being involved.
One thing I haven't heard from the crowd here is how to market the P2 given it's issues or when EDN does a review and brings up it being a power pig compared to cheaper alternatives on the market. It's going to take more than slamming a bunch of hobbyists and artist types using Arduino or repeated nostrums of "hard real time", etc. Evaluators will demand proof why the P2 is a better choice than say a STM32 M4 or some of the multicore ARM's from TI.
And Parallela? Sure they did kickstarter but they almost went under and needed a VC and Ericcson to bail them out to the tune of $3.5 million. What happens when Parallax eats through their kickstarter funds and then they realize they need more? There is this possibility and Parallax would be remiss in not factoring it in.
Chip has said the same die can be used for different heat packages - QFP144, BGA256, and maybe others such as QFP144 with thermal pad.
Therefore I suggest Parallax continue and build P2 at 180nm and package in QFP144, but preferably in a larger package ie larger pitch than 0.4mmbecause it should be a little better with heat transfer (is this so?).
If the P2has some temperature sensor on board we can monitor this while trying to profile (and validate) the P2. Parallax canthen market the P2 with whatever clock etc restrictions necessary to maintain the power disipation limit.
Later some die can be packaged in BGA256 for higher performance version.
I think my idea of utilising task(s) as "idle" clocks to reduce speed by 0-15:16 clocks should be implemented as this permits each cog to individually slowed in 1/16 clock increments to lower power.
Meanwhile who knows what OnSemimay come up with.
BTW Chip said the static power (leakage) at 180nm is ~1mA so nothing to worry about here.
A 5W P2 will take years before it makes a profit as sales will not be that high, so to use the profit for a 90nm later would mean in year 2020 and then its should be time for a P3 at what ever reasonable nm fab then.
Kickstarter, good thing is that they are pre-orders and not a share in the IP/Company, but sale prices need to be low as people are expecting a discount for pre-ordering 6 months in advance
Getting OnSemi as partner could be good as long the right deal is struck, like $1 for every P2 sold for the first 1mill units and then drop to 25cents.
Comments
Somebody will correct me on that, if I'm wrong. Hope not. But I really could be.
As for microprocessor development, yes! We are in the past, but that's what it takes to bootstrap new entities into the market. Or it takes a lot of dollars. We can make this happpen incrementally. I think we must.
This entire discussion has yielded NO options that do not cost us a lot of time and money, both of which could be selling this nice design. This discussion has also yielded the information that there are use cases and buyers we can sell to.
We did the work, it was fun, now we have to own it, and fund the future.
A Prop2 built in 65nm would have a raw manufacturing cost of about $2, which is the same cost as a 180nm chip in a low-power package. A 180nm chip in a 5W BGA would probably cost $5 to make.
To build Prop2 in 65nm would cost about $1M. This is more than Parallax can afford, of course.
I asked OnSemi if they'd be interested in partnering in some way, so that they would make this big investment and we would share in the outcome. I don't know if they'd be interested in doing that. With a partner like them, we could really knock out some nice products, not having to worry about so many implementation details, ourselves. They seem pretty smart, to me, about how they go about designs. When I explained that we have special I/O pads that need to be implemented in whatever process we wind up using, they said right away that we'd need their design kit, we'd do a minimum-sized test die in a shuttle run, repeating, if necessary, to prove our I/O's, and once proven, they'd integrate them into their design flow, which has all the checks needed for reliable closure. Cool!
By the way, that "lock them in the room for a week" I put here earlier? Doing that, right now, would very significiantly improve the chance of partnering. They will need to see a risk / reward case, and some known demand.
For them, the investment is multiplied by their internal costs, which makes it less. If we respond with a favorable risk profile, it could be compelling! Just saying.
This is one option that doesn't cost us too much time and money, but it has a pay off in the more near term than slogging through moving enough of the current P2 and process does. It's attractive and very worth doing the work to secure. Serious work.
I'm not sure I get the motivation for this multiple P2 idea.
What you are suggesting is that the chip be cut in half and the clock speed dropped. Then, to get performance/functionality back when we need it lets use more than one chip.
This makes not make sense to me yet because:
a) Building boards for two chips is always going to be bigger and more expensive than one.
b) This does not save you any power. you have just spread it around. OK that's good from a heat concentration point of view.
c) Rearranging code or writing new code for a 2 chip system is never going to be as simple as the single chip solution.
d) You are going to waste a COG in each device just taking care of communications between them.
The possibility of "massively parallel" systems is a myth. Who on earth is going to build a 1024 node Propeller system? The guys who want compute performance have far easier and more economical ways to get it (Did I mention my Parallella board has arrived, 16 floating point units and an ARM all for 100 dollars.) Who is going to want 80,000 odd I/O pins?
It has been seen before that projects on Kickstarter can get a lot of money : Pebble 10M$, Ouya 8.6M$ and the list goes on ( https://www.kickstarter.com/discover/most-funded?ref=most_funded )
Is that true for P2? If so who?
Personally, I'm hoping something is possible with OnSemi.
Or we have to do the work to move this design / process.
Fail can't be an option. It just can't.
Chip listed cutting the design in half as an option.
I personally would prefer a P2 that has better Cog bandwidth at the expense of fewer Cogs. So I saw the heat issue as
an opportunity and not really a problem at all.
All of my designs use multiple boards that's just the way I like to build things.
True story:
When Libby and I were young we bought an abandoned building. We spent about $100,000 for an architectural design.
By the time the design was done, we didn't have enough money for the build.
So, we scrapped the design, and with a few guys started throwing up walls. When we backed ourselves into
a corner, we tore a few walls down and put up new ones. When we were done, we had exactly what we wanted and
it cost a fraction of the $100,000 we spent on the architect. Of course the people building the walls and then tearing
them down again got a little frustrated.
To me this design process matches what I have found works best in my own experience.
You guys are great and it looks like Chip is close to turning the page on this chapter.
Rich
Potatohead has it right… failure is not an option.
Then if you go to https://www.kickstarter.com/discover/categories/technology/most-funded
you will see that some electronics project do quite well : Parallella 0.9M$ UDOO 0.64M$ HackRF 0.6M$ Spark Core 0.57M$ MicroView 0.45M$ and still 13 days to go.
If it can get Parallax the little financial push to grant a 65nm chip...
The Pono Music project got 5.3M$ to date here is what the Founder has to say about his Kickstarter experience:
Kickstarter is about what people (hobbyist?) want, and in the microcontroller world, I don't know many companies who care about us. They are far more interested in making cash with high volume. The user experience with Parallax is incredible and we have to spread the word about that.
Yeah Heater. That sucks. We don't have the process and resources right now to even come close to that metric. So, we just don't, unless some deal can be struck with OnSemi, or we get some magic crowd source thing, and frankly, I'm nervous about that, because it typically takes us a loooooong time to sort things out. Last thing we want is an angry mob. I would rather have the power disadvantage.
So then, we don't worry about it as I mentioned above. What we do have is a cool design, done in an affordable process for us, and it's got a lot of capabilities! Again, the possible. I'm not wanting to entertain how the magic power fairy didn't touch this P2. It was never, ever going to compete on the metric you just put there. We could have abandoned the design years ago, if that were the hard requirement.
But it wasn't the hard requirement. So now here we are. Time to own up and figure this thing out. If this were my design effort, and the money spent, etc... you can bet your Smile, it would get figured out to fund the future. That is what needs to happen.
Rather than look at the negatives, this discussion gets really simple: Who isn't so worried about power? They are now attractive prospects and we need to get after 'em.
Or, of those who are worried about power, how much of the performance do they need? We get after them too.
People need to get their heads around this.
Yeah, if it's enough. I'm totally up for a shrink, and in fact, think the shrink is the necessary thing to continue with volume in hobby land. I don't think it's needed for other opportunities.
With it shrunk, will it be attractive enough?
That discussion is as important as the other ones. And it also means some feature commits and a date too. Things all necessary at this point.
When I wrote the GUI for the original Scribbler, I got quite a way into the programming (thousands of lines) when I realized I had taken the wrong approach. I was faced with either pushing ahead or starting over from scratch. Well, not from scratch, really, because that would have ignored the context of all that I had learned from doing it "wrong." I chose to start over. Had I not had the one false start, I may never have hit upon the technique I ended up using, and the results may not have turned out as well. Moreover, had I started with the technique I ultimately used, it would have taken much longer than it did in the context of my previous attempt.
What I'm getting at is that there is no such thing as "failure" if you learn and derive inspiration from what you've done and apply those lessons going forward. As a consequence, I'm never afraid to start over on a project that has gotten into trouble and will only get into more trouble if I forge ahead instead of regrouping. In the long run the results are better, and the total effort is usually less than if I had continued on the original trajectory.
-Phil
Funding levels and rewards (numbers are estimated):
$5 - Thanks for your support - net to Parallax - $5
$15 - Thanks an P2 T-shirt - net to Parallax $7 (cost $8 for t-shirt and shipping)
$30 - Thanks, T-Shirt and P2 chip from production run - net to Parallax $12 (cost: $8 t-shirt, $10 for chip)
$75 - Thanks, T-Shirt and P2 Dev board - net to Parallax $15 (cost: $8 T-shirt, $52 for dev board)
$130 - Thanks, T-Shirt, DE0 Nano, first run P2 chip - net to Parallax - $12 (cost: $8 shirt, $10 chip, $100 Nano)
$200 - Thanks, Shirt, DE0 Nano, P2 Dev board - net to Parallax - $40 - (Cost: $8 shirt, $100 nano, $52 dev board)
$500 - Thanks, Shirt, Parallax FPGA board, P2 Dev Board - net to Parallax - $90 - (Cost: $8 shirt, $52 dev board, $350 FPGA board)
$1000 - Thanks, Shirt, 2 Parallax FPGA boards, 2 P2 Dev boards - net to Parallax - $ 78 - (Cost: $8 shirt, $104 dev boards, $700 FPGA boards)
$5000 - Thanks, you're a fanatic, you get several dev boards and a trip to the Walnut Farm when it is all done!! - net to Parallax $2500
OK, get the idea?
Now:
- The Nano could be an issue since you can't run 1 full COG on it at the moment - if somebody buys in to play, you need to be able to keep them in the game.
- The cost figures I included are fictional Parallax costs (parts, labor, shipping, NRE, overhead, everything) - there is no profit and hopefully no loss
- Parallax gets to put the "Net" amount toward the P2 project, everything else is spent or put in escrow to cover final rewards.
How many do you need to sell at each level to make $1M less Parallax contribution to funding??
How to you handle your crowd sourcing when it turns into MOB sourcing if there are delays?
How do you handle Angry Mob sourcing if something major happens (bad shuttle run, major bug in silicon (worst case), delays because of problems found in FPGA testing)?
If you need a second shuttle run, how do you fund it? You now have an angry mob, you can't just regroup, refocus and start putting profits from sales toward the next shuttle. You need to pony up hard cash you may not have because you have waiting investors.
I'd like to see if anyone can come up with target investor numbers for the various reward levels - it could be interesting to see how hard it is to raise some % of $1M.
and of course, the big question (back to where we are now) - what do you do if the crowd sourcing experiment doesn't raise the cash? You still need a plan B.
Dave, I like the way you think!
From an earlier post of mine:
There's a lot of productive and necessary work to do and a lot that can be done with a warm chip!
And
Is right where I'm at on it too.
Of course Phil. However, say a do over takes 4 years? That's a failure mode potential running very high, and that's really what I'm getting at.
Problem with 65nm is that $1M is a (rough) per-pass cost, so $1M is not guaranteed to result in release level silicon.
Good point.
Now that the idea of partnering the product has surfaced, there may be other interesting partnership opportunities that will surface.
Rich
Are those $2 prices for a thermal PAD TQFP128, as you were planning, or something even lower in price ?
Is that $5 BGA a real price, or an estimate - seems a lot to add for a package ?
Or is it an Alumina substrate to aggressively move the heat ?
The Thermal info I looked at, suggests a BGA does not gain that much, and the main thermal driver is the 'sea of vias' into the inner layers. A large die like the P2 helps a little here.
What does NRE tooling for a special TQFP128 (0.4 or 0.5) or TQFP144 (0.4 or 0.5) cost ?
ie one with the ideal PAD size, to spread heat from the die, before it hits the 'sea of vias'
I've seen packages with exposed pads on the TOP as well. My gut feeling is ~3W is practical, still in TQFP.
That is per-pass ? - what is the mask+prep cost per pass ?
All sounds sensible.
and, a little over stated, but valid...
and merging with my earlier suggestion of Counters faster than the Core (for power saving reasons) .
The P2 has fuses.
this idea of Packaging in more than one way opens.
* Lowest cost package, with lower power and a Ceiling on fMAX and VCore.
Possibly a Fuse could be used to allow high-speed timing precision, while the opcodes run slower.
ie the Fuse presents the highest power combinations of PLL + Core speeds.
OR a PCB with a (eg 100MHZ) Vcc, would further limit any power profiles, but at the cost of some precision.
Personally, I would prefer a 160MHz timing precision and 80MHz core, for example.
* Power focused package, allows Higher fMAX and VCore, no limits, able to be cooled to run everything at full speed.
- and I would look very hard for a package solution that enables both, with modest cost impact.
eg A dual Thermal PAD (top and Bottom) offers a number of cooling choices, at (hopefully) lower cost than a $3 adder Special BGA.
The 5W estimate is not 'real world'. Make the shuttle run, package as Chip best sees fit, and lets get these things on some boards and do some REAL real world testing. Then Chip and Ken will have good solid data to use for writing up an official 'release' specification that maximizes the marketing potential for this great chip.
If a one chip / three performance range approach does not work then perhaps they can look at three different chip packages.
20MHz - Low Power, 160Mips 8 core mini monster. This is, in effect, pretty much what the original 'improved' P1 concept was.
80MHz - Medium Power, 640Mips 8 core monster. With HUBEXEC, tasks, threading, SERDES, etc, this is a killer chip even at 80MHz.
160MHz - High Power, 1280Mips 8 core GODZILLA! This is an absolute BEAST of a chip and even with the power/heat design constraints will have a lot of application possibilities.
EDIT: All three would be the same 'chip' internally. Only difference would be max selectable clock speed and package type (TQFP128 @ 20/80, BGA @ 160). Yes, a 20MHz version would need 80MHz internal clocking (forgot about that).
@FredBlais, I find it fascinating. How many hobbyists want a chip with 16 or 64 floating point cores? Or would know what to do with one if they had one? But still Parallella exceeded their expectations. To the tune of 800 thousand dollars or so. Seems Kickstarter is not all about hobbyists in the usual sense.
@potatohead I have not seen any "angry mobs" so far on Kickstarter. The deal is somebody asks for money to do something. You decide if they are trustworthy and competent and lay down your cash. If it does not work out, oh well, that's my silly fault for putting money on the wrong horse.
I put a hundred and something dollars on Parallella. After checking their track record it seemed reasonable bet. After one year of delays I thought it was a bust. But lo Parallella is now shipping what they promised.
There were no "angry mobs" in that long year of waiting.
I'm not saying Kickstarter is the way to go. But it might me of course...
@Phil Whilst I love the "Nike" philosophy actually it is possible to fail. When all the money is blown, all the employees are let go, when you have to sell the farm to survive. Sometimes there is no coming back.
I'm "Heater" give me the chip now. Hot as it might be. I feel sure that Bill has a point. The worst case of 5W is not where we will be.
Three does not make much sense, as you are either thermally active, or you are not.
You have also mentioned more peripheral choices, which is more silicon variations. Best avoided.
20MHz P2, with matching Vcc, will be quite low power, but needs the caution that the present P1 has 80MHz timing, with a 20 MOP COG
A P2 with less precision, is not viable, but it is relatively easy to have a P2 with Timers at 80MHz and 20 MOP COGs
More marketable is 100MHz timing and 25M MOP COGs, but even that will be well inside any package Power envelope. (Of course, users can lower the Clock/Vcc if they need less )
Quite likely in a std (original) thermal TQFP128 would be something up to at least
100MHz timing and 1 x 100 MOP COG, and 7 x 50 MOP COGs,
and then there is whatever is possible, with serious thermal design. (this does need COG temperature sense )
The problem with stepping back to 4 cogs may be seen the same as going from a V8 to a V4. Most people may not need all that V8 power, but fear that V4 is too little.
My dad has a Lancia Apia with a V4. A great little car, but you just couldn't make it up some hills in San Francisco with 4 people in it.
++++++++++++++++
On the other hand, we have seen a big expansion of power hungry programing features of recent that also demand a lot more explaination to the user. The device might not only be 5 watts, but too challenging for wide spread popularity in the initial launch.
So cutting back some of the complexity, trying to keep all the originally promised features with maybe doubling the RAM (always a desired boost) might be prudent.
Don't be to greedy or ambitious. Don't get too far ahead of what most of your customers can learn.
Just have it compare as significantly better than the ArduinoDUE in terms of resources and you may avoid a lot of silly negatives from that crowd.
You have a failed OnSemi 180nm die. Can't that be used to validate the I/O ?
In case you folks have forgotten, they've put in $4,000,000 into it.
That's a lot for a small company.
Do you push forward in a market where this particular flaw will show up like a clown car at a circus or do you hope to find a guardian angel(VC or OnSemi) to bail out your design? These probably have their own risks as well, especially with a VC being involved.
One thing I haven't heard from the crowd here is how to market the P2 given it's issues or when EDN does a review and brings up it being a power pig compared to cheaper alternatives on the market. It's going to take more than slamming a bunch of hobbyists and artist types using Arduino or repeated nostrums of "hard real time", etc. Evaluators will demand proof why the P2 is a better choice than say a STM32 M4 or some of the multicore ARM's from TI.
And Parallela? Sure they did kickstarter but they almost went under and needed a VC and Ericcson to bail them out to the tune of $3.5 million. What happens when Parallax eats through their kickstarter funds and then they realize they need more? There is this possibility and Parallax would be remiss in not factoring it in.
Therefore I suggest Parallax continue and build P2 at 180nm and package in QFP144, but preferably in a larger package ie larger pitch than 0.4mmbecause it should be a little better with heat transfer (is this so?).
If the P2has some temperature sensor on board we can monitor this while trying to profile (and validate) the P2. Parallax canthen market the P2 with whatever clock etc restrictions necessary to maintain the power disipation limit.
Later some die can be packaged in BGA256 for higher performance version.
I think my idea of utilising task(s) as "idle" clocks to reduce speed by 0-15:16 clocks should be implemented as this permits each cog to individually slowed in 1/16 clock increments to lower power.
Meanwhile who knows what OnSemimay come up with.
BTW Chip said the static power (leakage) at 180nm is ~1mA so nothing to worry about here.
Kickstarter, good thing is that they are pre-orders and not a share in the IP/Company, but sale prices need to be low as people are expecting a discount for pre-ordering 6 months in advance
Getting OnSemi as partner could be good as long the right deal is struck, like $1 for every P2 sold for the first 1mill units and then drop to 25cents.