We're looking at 5 Watts in a BGA!
cgracey
Posts: 14,208
OnSemi has been doing some prep work and their initial power estimation for the core came back at 4-6W. This is without clock-gating, so when they get their synthesis tools to properly infer clock-gating, power will drop by probably 1/3. This is still huge, and doesn't account for memory and I/O power, which could be significant. My gut feeling is that we can get the power down to 5W and not need cooling by using a 17x17mm BGA package.
This all seems, outrageous, I know. I think we are being very ambitious for a 180nm process. This level of design complexity really needs 90nm, or less, to be practical. 40nm would be great - low power and GHz+ speed, but we don't have the budget for that.
I don't know what level of enthusiasm there might be for a 5W BGA Prop2 that costs $12. I think the 5W is worse than $12.
What we can do at this point:
A) Continue on the current trajectory.
Pare down the design, jettisoning all kids of features, like hub exec, and get back to something much smaller and maybe faster. The current FPGA implementation could be further honed and later, hopefully, made into a chip using a smaller technology.
C) Drop the current design to four cogs, which would also reduce cache sizes and hub memory down to 128KB. This would also allow us to shrink the die considerably, as we could change the I/O pin aspect ratio to allow them to fit together more densely, occupying more of what was needed for the core. This would also mean the whole chip would fit on an FPGA.
D) Retire to an opium den.
E) Other ideas?
This all seems, outrageous, I know. I think we are being very ambitious for a 180nm process. This level of design complexity really needs 90nm, or less, to be practical. 40nm would be great - low power and GHz+ speed, but we don't have the budget for that.
I don't know what level of enthusiasm there might be for a 5W BGA Prop2 that costs $12. I think the 5W is worse than $12.
What we can do at this point:
A) Continue on the current trajectory.
Pare down the design, jettisoning all kids of features, like hub exec, and get back to something much smaller and maybe faster. The current FPGA implementation could be further honed and later, hopefully, made into a chip using a smaller technology.C) Drop the current design to four cogs, which would also reduce cache sizes and hub memory down to 128KB. This would also allow us to shrink the die considerably, as we could change the I/O pin aspect ratio to allow them to fit together more densely, occupying more of what was needed for the core. This would also mean the whole chip would fit on an FPGA.
D) Retire to an opium den.
E) Other ideas?
This discussion has been closed.
Comments
5W bad
BGA? Probably really bad for anybody fabricating.
D -
Very unsettling. How about:
E) P8x32b with 64KB HUB RAM while we wait.
Agreed, we would need to show some nice applications to aid the process though ;-)
Chip, have you ever considered this route? I best most on here would support it.
I think the current situation is an inevitable consequence of the open design process. So I'll go with ...
E) Take a month off -- two months off. Go to Mexico, sit on the beach, body surf, and put the P2 out of your mind completely. When you return, you'll have a whole new vision and perspective. Start afresh, and maintain that vision. Stay away from Rocklin. Stay off the forum and the suggestions found here that distract you from your vision. We've done our part, and you really don't need us anymore. A year -- two years -- down the road, convene a presentation in Rocklin, and amaze us with a finished chip, like you did with the P1.
-Phil
But I just bought a BIG, honkin' FPGA!! :frown:
...and as for the Kickstarter??
But I just bought a BIG, honkin' FPGA!! :frown:
I don't understand the implications of the 5W level. So until someone explains why 5W is such a problem, I like A. I assume that there are some very compelling arguments against 5W, but you have a really nice design, and I would hate to see you scrap it all. If 5W is an absolute "no" and you can keep the current design and go to 4 cogs…I think 128K is more than enough… then my next favorite is D.
At this point I think my absolute favorite is F.
F:
The time has come to take Parallax public. Figure out how much money you would need to do 40nm in house. Figure out how much money your grandchildren will need. Multiply that number by a factor of two. Hire a consultant to write a white paper. You will be rich by next December… and we will have more cogs, more ram, and more features than we could have dreamed. If you don't want to be rich, then
G:
Go to crowd funding and get to 40nm on the cheap. For crowd funding, timing is critical. So, you will need to thoroughly test the design before entering the mash pit.
Rich
5W? Doesn't phase me as much as it seems to phase others. I never envisioned a battery-powered P2. Still, the crowd-source idea is appealing...even intriguing!
Ditch HubEx? Do it today!
Four cogs? Amazing how useful a single P2 cog is! Four P2 cogs would handle a BUNCH.
Talk about rocks and hard places.
Phil probably has a very good idea.
Options A) and D) look like the roads to hell. As attractive as D) seems sometimes.
C) Given that we have threads now perhaps 4 cogs is OK. A hard way to go though. Cutting back on RAM would be horrible. Those C guys need it.
E) Ah..got me there.
Yep, I'd go for the therapeutic break. It's amazing what ones brain can come up with whilst you are busy thinking about something totally different.
Dave is also right, measure the problem, where are the high power low use value areas.
@rjo,
Well, my soldering iron is 15 watts and it melts solder. 5 watts generated in a much smaller area is going to melt something.
Look at refactoring the design of features to reduce power consumption if possible, then put features on the chopping block if the power consumption is still excessive.
C.W.
nice day-te today
You mean Chip could be the Orson Wells of the semi-conductor world??
One would hope you are correct...
C.W.
You rock!
-Phil
Ditto with mine!
Then, after getting an email from OnSemi, I forgot all about it being April 1st, and thought I'd better start figuring out what we are going to do about this power problem.
I'm going to be talking to them in a few minutes...
Serious? No.
Then assuming it goes well, we can then add all the functions back in for P3.
e) Make a list, go sit under a walnut tree (by yourself) and whack away features until it fits the power profile you want. Then come back and tell us what we get in a P2 and we are all happy. (We are ALL HAPPY, right guys????)
(We're all really chomping at the bit to start workign on teh P2 anyway!!)
John Abshier
Re sitting under walnut trees or on the beach. The P1 just seemed "right" I think that is because you had a vision and designed to that vision. The forum threads of the last several months, which I only often skim and not read for detail, make me think of a camel, a horse designed by a committee. I don't know what your vision for the PII is. It is probably not my vision. But I am not experienced enough and willing to put in the required effort to design a chip. You are. I think you should step away from all of us on the forum, decide what you want the PII chip to be, probably also look at what Parallax the company needs, and make a PII that hopefully will seem "right" when you are done.
John Abshier