There is no question that something needs to be done - the P2 is unsaleable at these power levels. The question is what.
Ross.
I'd buy it!
As previously mentioned it will save at least 2 watts from other parts in my application. So if P2 has a typical use figure of 1~2 watts, which looks likely, addition of the P2 could even be carbon neutral.
As previously mentioned it will save at least 2 watts from other parts in my application. So if P2 has a typical use figure of 1~2 watts, which looks likely, addition of the P2 could even be carbon neutral.
Yeah, but you lunatics would buy it at 5W, 10W or even 50W!
Ross.
10w, yes, still. Perhaps I should lobby Chip to squeeze a few more features (or cogs) in
50W, now you're just being silly. Though when looking back through some work during the past 20 months I did realise that yes, we'd do pretty much whatever it takes to integrate a P2.
10w, yes, still. Perhaps I should lobby Chip to squeeze a few more features (or cogs) in
50W, now you're just being silly. Though when looking back through some work during the past 20 months I did realise that yes, we'd do pretty much whatever it takes to integrate a P2.
If you're looking for something to bump up the wattage maybe Chip would consider my TLB idea. :-)
At a given clock frequency, is there a difference between running 8 cogs and running 8 cogs "full bore"?
Personally, I don't think I'd buy a Propeller 2 for anything more than hobby use if it takes more than 0.5W. And comparing it to a Pi or other ARM isn't fair: I'd much rather use Linux with all of it's existing tools and wide support, even if the Propeller 2 is just as powerful (both in MIPS and W).
If a cog is spending 90% of its time waiting for something it will only take roughly 10% of the power of running full bore.
So I'd say it is quite likely that for most uses the P2 power envelope will meet your 0.5W criteria. Just don't use more cogs than you have to, and only run at the clock speed you need.
As far as using Linux and Pi's... I *LOVE* my Raspberry Pi's, but they are not hard real time microcontrollers. Which is my I made RoboPi - to add hard real time.
Regarding using P2 if it takes more than .5W ... that will depend on the application.
If I don't need the extra features or speed, I am likely to use the P1 if it has enough "ooph". Plenty of life left in the P1, and far lower leakage current.
If I need the P2 features to accomplish my (or my clients) task, and the P2 is the best fit, even if it takes 10W, I'll use the P2.
If Cortex M4 with FPU is a better choice than the P2 (not likely for most of my work) I'll use the M4. I've got ARM etc boards coming out the ying yang in my lab.
If XMOS is the best fit, I'll use XMOS.
My strong preference is P1 / P2 due to shorter development time and elegance, but I will use whatever chip is appropriate to the project at hand.
At a given clock frequency, is there a difference between running 8 cogs and running 8 cogs "full bore"?
Personally, I don't think I'd buy a Propeller 2 for anything more than hobby use if it takes more than 0.5W. And comparing it to a Pi or other ARM isn't fair: I'd much rather use Linux with all of it's existing tools and wide support, even if the Propeller 2 is just as powerful (both in MIPS and W).
[" SureCore’s 28nm silicon tests confirm world leading power efficiency
SureCore Ltd has today announced that early testing of its innovative low power SRAM design confirms its simulations that deliver in excess of 50 percent power savings over other SRAM technologies.
The tests prove that the patented circuit architecture developed by SureCore delivers greater than 50% power savings versus industry standard SRAMs."]
Isn't the P2 designed in a similar process to the P1? How many P1's would you say a P2 can perform the work of? I think it's a few, which puts us at 1-2 watts.
This is reasonable.
Did anyone actually expect a power profile similar to the P1? I know I never did, and I know that after I processed Chip talking 1-2Watts for the early design we had unsuccessfully fabbed.
If we were to add the timing capabilities JMG has suggested, we've got a LOT of very reasonable options.
And again, the chip running at 80Mhz rocks hard. So many things are improved, and at the 80Mhz, one could expect to treat it a lot like a super P1, and do so at a modest power budget. Coupla watts.
One thing galls me. And this isn't aimed at anybody, it's just something that galls me overall, just having been a part of this. If we had hardline requirements, why the heck didn't we at least keep those somewhat relevant?
Several times, I often wondered, "What is a P2 supposed to be?" and we didn't have the answers, other than to maximize the design potential. So that's what we did, and that comes at a power cost, one that JMG also highlighted a whole lot of times now.
To me, we made the choice, and again, we are at a very basic decision point:
1. Punt and go make a spiffy P1B. I'm really not inclined toward that direction. I love the P1, but when that's done, it's going to appeal to people who are into the P1 now, but I see that as way behind where we need to be. I'm very curious to hear more from people about that. In particular, would there be serious volume sales possible? The kind of volume that gets us a P2 in a process that is better for everybody in terms of power?
2. Finish this CPU. It's a pretty great CPU, and I find Bill's comparisons to other CPUs particularly lucid. This reminds me a whole lot of how MIPS was compared to Intel devices. I used to run MIPS at a few hundred Mhz, sometimes just 200Mhz, and it would often sing compared to 800Mhz plus, pick your Pentium. Kind of funny how that worked out.
The P2 is like this, and even at a modest clock, is capable of a lot. If we got the full 8 COGS, the FPGA shows us the thing can do a ton right now. And I think it would be hard to really max it out for a lot of use cases, particularly with the clock variation per COG being discussed. That's smart. Add some basic temp control, and we can really make use of the chip well under the ugly wattage people are feeling bad about.
Subtract an OS, GPU BLOB, fat tool chain, etc... and you can do things on the P2 that would take a lot of resources on other devices and do them in parallel in a lean software environment. Lots of dependencies go away. This is worth something. Could be worth a whole lot.
Given how much we've got invested in this design, and how excellent it is, I'm really on the fence about bagging on it. Here's a thought:
Will it do the work people need it to do? And more importantly, can it be sold to do that work? This really needs discussion and I know sales, marketing and other kinds of non-engineering related topics are not popular here, and for good reason! We are geeks. But some of us are business minded geeks, and I'm one of those, and before I went off and either diluted down this investment or abandoned it, I would make damn sure I had a business case for doing so.
We have quite simply not done that work. Honestly, let's say this thing worked it's magic, 200Mhz, full performance at 1-2 watts. How is that different? What use cases fall on the map that aren't on the map now at the higher power profile? More importantly, what use cases are common, and where are the extremes that need full bore performance and what do they really look like at 5 watts as opposed to a coupla maybe three watts? Or one?
If we are wanting to make tablets, 5 watts kind of sucks. But if we are wanting to make computers, automate industrial machines, build instruments, power robotics --real things, not toys and fun stuff, that kind of power budget isn't a big deal.
So where are the edges? And where are the dollars relative to those edges?
Frankly, I feel sometimes like this is just people thinking P1 and how it can almost run off the power we get from a potato battery, or imagining it won't run off a USB nice and easy, getting cranky and projecting that onto what can happen otherwise. Is this true? I really think it might be.
Maybe it is for education. I really want to hear about that, and how education needs the full throttle. Does it? Run this at 20Mhz, and it runs off a battery and will still do great video, make cool sounds and drive all sorts of things. Seriously.
3. Rip into it, gutting the thing, complicating it, or hobbling it for no reason.
Before we do that, we really need to have the use case discussion. Just what is a P2 supposed to be, and WHY is it supposed to be that way?
The what should be driven by some idea of the kinds of thing we know buyers will adopt it for. We won't know all of those, and we won't know of the buyers who adopt it because of things we didn't see, etc... but we can make some boundaries from the things we do know, and if we do that, this discussion becomes a lot easier and more rational.
Right now, we are trying to optimize everything at once, and it's taking years. I like where we are now, but I don't like the idea of taking off for another few years to end up somewhere else, and I really don't like it if we've done that for no apparent basis.
So we really need to have that discussion, or if we can't have it, and not having it for that reason is fine. We might just not have the skills or the time or the data needed to have it proper, then we need to pay somebody to help us have it so that we know something about how we fund P3 with whatever we do now, right along with how we fund our futures together.
Some of us here are doing it for fun. Some of us want to make and sell stuff. Others want to put the chip to work solving problems for people. Still others want to make products of some kind or other.
Those futures need to be funded, and for that to happen, we need to answer a couple of basic questions I've put here, not just grumble over the power requirements when we knew darn well what they were going to look like the whole time.
This chip was never, ever going to be less than a watt. Ever. We knew that years ago, and we knew it because of the process, etc... Now we let 5+ watts creep up on us. Fair. But we also did so much awesome work that we don't need to run the chip full blast to get a whole lot done either. Think about that. It's worth thinking about.
So then, it was going to take some juice to run. It was always going to take some juice to run.
4. Shrink the thing. Frankly, I would produce this one, and use it to fund the shrink, or a P1 variant, or just to recover some costs and get some things done.
Maybe a shrink is a great transition to a much more powerful third gen design. This is worth thinking about on a few year timeline, but only if we are selling something and getting things done and made now; otherwise, people are going to drop off the wagon. Seriously. They just will, and they will because P1 continues to age.
Re: Linux, etc...
At 100Mhz, this chip can present a GUI, run a lot of controls and sensors, generate sounds, process a lot of data, deliver fine grained control over so many GPIO pins it's nuts, and it can do so without an OS, and in ways that are not difficult.
I still think that is an extremely valuable proposition at our current power consumption. Sure, smaller processes, optimized through zillions in volume production get down to very modest power levels, but they come with a lot of entanglements. This chip does not. I think that's worth a considerable amount, but that's me.
When I read this discussion, I want to see the business side thought about more, because we are at a crossroads because we didn't think about the business side of things very much in the design phase. Again, that's fine. Many of us feel it's worth it to have done it that way, so here we are. Before we jump off cliffs or doom a great design out of hand, let's have a rational talk about what is possible. And based on that possible, figure out what, if anything should be done to maximize our futures.
What can be done, not what can't. It was a lot of fun getting here wasn't it? Damn right it was. Now let's own our work and talk about the possible. And more importantly, if we have failed and we have to punt, let's own that too and define what will succeed. I'm sick of chasing a tail around wondering what makes sense, and I know I am not the only one. It was fun stuffing features in, now we gotta do the work to figure out what that all means.
I'm for getting the design packaged and tuned up in this process and out the door so it can do some good. Anything else puts years in front of us and I'm so not up for that. Not without something in the can we can be working with, on, and for to fund the activity over the long haul.
Cool !! That means the ~170mW a P2 can reach, when emulating a P1, (20MHz), should deliver you 100,000,000 ?
What order number should Parallax use, when sending you the invoice ?
[Where I live, price sensitive means people worry about, well, price, not that 'W' thing]
You have a much better grasp of power utilization and ASIC's than I do.
1) What do you think a realistic max wattage is for the P2?
2) Based on Chip's initial post, and clock gating, I feel that 3.5W is a far more likely maximum, with eight cogs going full blast @ 160Mhz. Do you think that is more likely than 5W?
3) Personally, I suspect than in most applications, P2 will not be going anywhere near full blast with all eight cogs. I think "typical" power usage will be well below 1W, more like 0.5W. What do you think?
4) I think 170mW @ 20Mhz would be a killer chip for many uses!
Cool !! That means the ~170mW a P2 can reach, when emulating a P1, (20MHz), should deliver you 100,000,000 ?
What order number should Parallax use, when sending you the invoice ?
[Where I live, price sensitive means people worry about, well, price, not that 'W' thing]
This chip was never, ever going to be less than a watt. Ever[/B]. We knew that years ago, and we knew it because of the process, etc...
Not at Full throttle, but I calculate it can emulate a P1 (same opcode speed - ignoring smarter opcode gains for now) at ~170mW, so it can do useful work, at well under 1W.
I think 170mW @ 20Mhz would be a killer chip for many uses!
So do I, and the funny thing is we still get spiffy video at 20Mhz. Will dance circles around P1. Just saying as a point of reference.
@JMG, totally with you on that. I think we have a case of unrealistic expectations in play here, not something that is a failure. We need to reset, reframe and figure out what makes sense given this design, and once we understand that better, maximize it. We've got a good design, capable of a lot over what now appears to be a very wide range of power / performance ranges. Sweet!
An incredible 288 posts in less than 36 hours, and all based on very little factual information. The general direction of this thread brings to mind two cliche's. Yes, they're cliche's, but they're clich
You have a much better grasp of power utilization and ASIC's than I do.
1) What do you think a realistic max wattage is for the P2?
The "realistic max wattage" for P2, is ultimately what the package and thermal management can handle
This has morphed a little from a Electronic optimise problem, to a Thermal one.
( ie it looks like the core can run ahead of the package/cooling.)
Of course, that's also how intel has designed CPUs for quite a while now - start with power, and work backwards.
I would start looking for the worlds thermally best TQFP128 (0.4 or 0.5mm) or TQFP144 & try to avoid BGA, if at all possible.
One with exposed metal on top and bottom would be interesting....
2) Based on Chip's initial post, and clock gating, I feel that 3.5W is a far more likely maximum, with eight cogs going full blast @ 160MHz. Do you think that is more likely than 5W?
That sim run excluded RAM, but also did not properly simulate Clock Gating. So there are many variables in play.
Hopefully Clock Gating gains dominate, but the package-limit area is looking like 3W Tops.
3) Personally, I suspect than in most applications, P2 will not be going anywhere near full blast with all eight cogs. I think "typical" power usage will be well below 1W, more like 0.5W. What do you think?
4) I think 170mW @ 20Mhz would be a killer chip for many uses!
That's why good clock control looks like it matters more now.
Chip has indicated this is not hard, given he already gates clocks to COGs.
VCore control does not need any chip changes, and COG Temperature sense, is very small.
One COG at full speed will be 625mW, but very few systems will need Timers AND CPU at 160MHz
All other COGS (at the higher VCore) can give P1 performance, for another 625mW
potatohead:
Well said, a little long but well said!!!
Currently we don't have all the facts, that's for sure. Until we do we cannot (well Chip & Ken) cannot make any hard decisions. So we can just discuss options.
Most don't like 5W and that is a problem. However some will use it at anyway.
While I understand how this power crept up on us, I am not sure if any of my designs I have in mind would use 2W, and likely much less. Using the SETASK and making some tasks idle allows us to easily slow each cog individually down in 1:16 clock increments.
I have advocated a number of possibilities including the P1B & P1C. I have attempted to explain where I see the extra power usage crept in (not all wish to agree). My overall preference is hopefully still with the P2. I just want to be sure we can offer a suggested alternative to Chip if the P2 is going to be delayed for a while due to reconfig or costs.
But this thread should examine some real possibilities (I know without a lot of hard data) of how we could save some things on P2. Each may only save a little, but each has a *8 multipier, and a number of little savings add up to reasonable savings. That's precisely what happened the other way over time. I don't think it is going to magically fix itself.
BTW: I have access to KILLER Electronic Systems Cooling software. If that comes up...
@Cluso, yeah I do long. Sorry. But we all know that by now.
And I must emphasize, for each of those little cuts, we must ask whether or not the scope of capability isn't equally well addressed by an appropriate power and clock.
I've been thinking through scenarios myself, and just treating it like a P1 with extras, with a 1W budget, gets people a ton of capability. We really need to think about that.
So, what is a plausible use case that seriously flexes the chip we've got done?
There is using a P1, and there is multiple P1 chips, and there is a P2, and various power ranges * clock = heat trade-offs, and then there is something else... We are quite used to running P1 chips near max clock. I'm not so sure we max them out in terms of compute, etc...
With this one, running at max isn't necessarily a given, so what uses cases take what? That's what I'm after. Expectations ran high, and they did so for a long time. Time to reset them realistically.
@Cluso, he's factoring in various voltage scenarios in addition to the raw clock / power ratio.
As usual I am just lurking here. But I think that @potatohead is summing up things quite well. summing up is a relative thing with his posts.
I will be more short.
This is about sustainability. It is a quit big hit for Parallax. Going public is out of question. We are talking about selling the (walnut) farm.
Parallax is privately owned an that is one of the reasons they are able to archive what they are doing. I just was once down there in Rocklin. This company rocks.
Its not just the customer service they do excellent. It is also the workplace for 60+(?) people they provide. Chip and Ken (and all those other guys and gals working there) are:
-dedicated
-smart
-willing to work hard
-fun to be with
But there are just 60+ people and just one Ken, one Chip and one Beau. Them try but they can't walk on water and do wonders.
But P2 is overdue. It took now 6+ years to get where we are.
All those discussions about a prop 1.5 with limited features are hopeless. I may be hard here, but this may end up as a big joke in the industry. This should not happen.
There is no time anymore to develop another year or two. This thing needs to get out.
Do not slash ANY function. Add serdes and usb support as planned. Add different clock speeds for cogs if that helps.
And live with it. Yes 5 watts. horrible for mobile devices. But of NO concern in any industrial application.
Sure. If Parallax can pull out $1m somewhere out of some pocket it would be great to go to a smaller process and more speed/less power.
Maybe all of us should spend some money on lottery tickets dedicated to Parallax. You never know.
Enjoy!
Mike
[edit]
Below you see one of the shortest @potatohead posts ever...
[/edit]
By following Atmel's Power scaling, I took 4.5V and 2.7v to be conservative, and that gives
4.5*2.2/2.7*1 = 3.66666 power ratio 625mW/ans = 170.454 mW
( Suggests 1.1-1.2V core voltage.)
This also is clear from the Pt = SumOf(Cpd * Ft * Vc^2) - high Vcc is only mandated if you want High MHz, at low MHz you can drop both Ft and Vc
When Chip paired down the task LIFOs from 32 bits wide to 18 bits wide, IIRC he said that saved 240 flops. There were 4 x LIFOs x 4 deep = 16*14bits saved = 224 so we are about right here. Scale this from 14 saved to 18 used and we get 308 flops, so say 300. Of course we have 8 sets for 8 cogs.
Now, each time there is a push/pop/call/ret, all of these flops toggle. If the LIFO used a SRAM and a pointer, no doubt a lot less registered bits toggle. Could this result in a reasonable power saving ???
Below you see one of the shortest @potatohead posts ever...
I think sometimes slowly, but long form. That's an artifact of the kind of work I've done for way too many years. It involves picking through a lot of requirements, multi-departments, MAKING BUSINESS CASES (which often suck huge, mind you, but I can do them), and then presenting what is possible.
If it were me on this?
I would full stop, other than Chip continuing to optimize what we've got with OnSemi, and before doing another thing, drop some $$ on getting the right people, some outsiders to this whole thing who have experience in markets we think likely, lock 'em up, feed them as necessary, and don't let 'em out, until some of the possible is known to the point where we know we can fund a future or not. Might take a week. I'm serious. Nobody will want to be in that room after the second day. That is what gets it done.
Do not have Chip in that room. I mean that too.
Then move on that info. Finish it.
And I've done something similar to that in the past to get past stuff like this. It works, and it sucks for everybody, and people hate you, until they love you when it's working nicely afterword.
I cannot overemphasize how important it is right now to understand what is possible with the product of our work. It's a lot of work! It needs to pay off, and I believe it can.
By following Atmel's Power scaling, I took 4.5V and 2.7v to be conservative, and that gives
4.5*2.2/2.7*1 = 3.66666 power ratio 625mW/ans = 170.454 mW
( Suggests 1.1-1.2V core voltage.)
This also is clear from the Pt = SumOf(Cpd * Ft * Vc^2) - high Vcc is only mandated if you want High MHz, at low MHz you can drop both Ft and Vc
Yesterday you told us it scales linearly uW/MHz.
Now you are using a factor of 3.7.
Something is not right here.
Comments
I'd buy it!
As previously mentioned it will save at least 2 watts from other parts in my application. So if P2 has a typical use figure of 1~2 watts, which looks likely, addition of the P2 could even be carbon neutral.
brucee not sure you've seen the (relatively recent) Hub execute feature, which allows the program code to fill available hub ram (256kB at last count)
That 5W worst case will likely be more like 3.5W once the clock gating is taken into account.
And that is full blast, all cores, non-stop. Not likely to happen.
Not to mention if we don't need the speed, we can drop multipliers, and unused or mostly waiting draw little to nothing.
Yeah, but you lunatics would buy it at 5W, 10W or even 50W!
Ross.
10w, yes, still. Perhaps I should lobby Chip to squeeze a few more features (or cogs) in
50W, now you're just being silly. Though when looking back through some work during the past 20 months I did realise that yes, we'd do pretty much whatever it takes to integrate a P2.
Sorry David you're going to have to help me out on that one. I've probably read about it somewhere already, but got a link?
Personally, I don't think I'd buy a Propeller 2 for anything more than hobby use if it takes more than 0.5W. And comparing it to a Pi or other ARM isn't fair: I'd much rather use Linux with all of it's existing tools and wide support, even if the Propeller 2 is just as powerful (both in MIPS and W).
If a cog is spending 90% of its time waiting for something it will only take roughly 10% of the power of running full bore.
So I'd say it is quite likely that for most uses the P2 power envelope will meet your 0.5W criteria. Just don't use more cogs than you have to, and only run at the clock speed you need.
As far as using Linux and Pi's... I *LOVE* my Raspberry Pi's, but they are not hard real time microcontrollers. Which is my I made RoboPi - to add hard real time.
Regarding using P2 if it takes more than .5W ... that will depend on the application.
If I don't need the extra features or speed, I am likely to use the P1 if it has enough "ooph". Plenty of life left in the P1, and far lower leakage current.
If I need the P2 features to accomplish my (or my clients) task, and the P2 is the best fit, even if it takes 10W, I'll use the P2.
If Cortex M4 with FPU is a better choice than the P2 (not likely for most of my work) I'll use the M4. I've got ARM etc boards coming out the ying yang in my lab.
If XMOS is the best fit, I'll use XMOS.
My strong preference is P1 / P2 due to shorter development time and elegance, but I will use whatever chip is appropriate to the project at hand.
http://electroiq.com/blog/2014/04/surecores-28nm-silicon-tests-confirm-world-leading-power-efficiency/
[" SureCore’s 28nm silicon tests confirm world leading power efficiency
SureCore Ltd has today announced that early testing of its innovative low power SRAM design confirms its simulations that deliver in excess of 50 percent power savings over other SRAM technologies.
The tests prove that the patented circuit architecture developed by SureCore delivers greater than 50% power savings versus industry standard SRAMs."]
Whereas I think 5W is silly. It should be easy to quantify this. A simple table:
Ross.
This is reasonable.
Did anyone actually expect a power profile similar to the P1? I know I never did, and I know that after I processed Chip talking 1-2Watts for the early design we had unsuccessfully fabbed.
If we were to add the timing capabilities JMG has suggested, we've got a LOT of very reasonable options.
And again, the chip running at 80Mhz rocks hard. So many things are improved, and at the 80Mhz, one could expect to treat it a lot like a super P1, and do so at a modest power budget. Coupla watts.
One thing galls me. And this isn't aimed at anybody, it's just something that galls me overall, just having been a part of this. If we had hardline requirements, why the heck didn't we at least keep those somewhat relevant?
Several times, I often wondered, "What is a P2 supposed to be?" and we didn't have the answers, other than to maximize the design potential. So that's what we did, and that comes at a power cost, one that JMG also highlighted a whole lot of times now.
To me, we made the choice, and again, we are at a very basic decision point:
1. Punt and go make a spiffy P1B. I'm really not inclined toward that direction. I love the P1, but when that's done, it's going to appeal to people who are into the P1 now, but I see that as way behind where we need to be. I'm very curious to hear more from people about that. In particular, would there be serious volume sales possible? The kind of volume that gets us a P2 in a process that is better for everybody in terms of power?
2. Finish this CPU. It's a pretty great CPU, and I find Bill's comparisons to other CPUs particularly lucid. This reminds me a whole lot of how MIPS was compared to Intel devices. I used to run MIPS at a few hundred Mhz, sometimes just 200Mhz, and it would often sing compared to 800Mhz plus, pick your Pentium. Kind of funny how that worked out.
The P2 is like this, and even at a modest clock, is capable of a lot. If we got the full 8 COGS, the FPGA shows us the thing can do a ton right now. And I think it would be hard to really max it out for a lot of use cases, particularly with the clock variation per COG being discussed. That's smart. Add some basic temp control, and we can really make use of the chip well under the ugly wattage people are feeling bad about.
Subtract an OS, GPU BLOB, fat tool chain, etc... and you can do things on the P2 that would take a lot of resources on other devices and do them in parallel in a lean software environment. Lots of dependencies go away. This is worth something. Could be worth a whole lot.
Given how much we've got invested in this design, and how excellent it is, I'm really on the fence about bagging on it. Here's a thought:
Will it do the work people need it to do? And more importantly, can it be sold to do that work? This really needs discussion and I know sales, marketing and other kinds of non-engineering related topics are not popular here, and for good reason! We are geeks. But some of us are business minded geeks, and I'm one of those, and before I went off and either diluted down this investment or abandoned it, I would make damn sure I had a business case for doing so.
We have quite simply not done that work. Honestly, let's say this thing worked it's magic, 200Mhz, full performance at 1-2 watts. How is that different? What use cases fall on the map that aren't on the map now at the higher power profile? More importantly, what use cases are common, and where are the extremes that need full bore performance and what do they really look like at 5 watts as opposed to a coupla maybe three watts? Or one?
If we are wanting to make tablets, 5 watts kind of sucks. But if we are wanting to make computers, automate industrial machines, build instruments, power robotics --real things, not toys and fun stuff, that kind of power budget isn't a big deal.
So where are the edges? And where are the dollars relative to those edges?
Frankly, I feel sometimes like this is just people thinking P1 and how it can almost run off the power we get from a potato battery, or imagining it won't run off a USB nice and easy, getting cranky and projecting that onto what can happen otherwise. Is this true? I really think it might be.
Maybe it is for education. I really want to hear about that, and how education needs the full throttle. Does it? Run this at 20Mhz, and it runs off a battery and will still do great video, make cool sounds and drive all sorts of things. Seriously.
3. Rip into it, gutting the thing, complicating it, or hobbling it for no reason.
Before we do that, we really need to have the use case discussion. Just what is a P2 supposed to be, and WHY is it supposed to be that way?
The what should be driven by some idea of the kinds of thing we know buyers will adopt it for. We won't know all of those, and we won't know of the buyers who adopt it because of things we didn't see, etc... but we can make some boundaries from the things we do know, and if we do that, this discussion becomes a lot easier and more rational.
Right now, we are trying to optimize everything at once, and it's taking years. I like where we are now, but I don't like the idea of taking off for another few years to end up somewhere else, and I really don't like it if we've done that for no apparent basis.
So we really need to have that discussion, or if we can't have it, and not having it for that reason is fine. We might just not have the skills or the time or the data needed to have it proper, then we need to pay somebody to help us have it so that we know something about how we fund P3 with whatever we do now, right along with how we fund our futures together.
Some of us here are doing it for fun. Some of us want to make and sell stuff. Others want to put the chip to work solving problems for people. Still others want to make products of some kind or other.
Those futures need to be funded, and for that to happen, we need to answer a couple of basic questions I've put here, not just grumble over the power requirements when we knew darn well what they were going to look like the whole time.
This chip was never, ever going to be less than a watt. Ever. We knew that years ago, and we knew it because of the process, etc... Now we let 5+ watts creep up on us. Fair. But we also did so much awesome work that we don't need to run the chip full blast to get a whole lot done either. Think about that. It's worth thinking about.
So then, it was going to take some juice to run. It was always going to take some juice to run.
4. Shrink the thing. Frankly, I would produce this one, and use it to fund the shrink, or a P1 variant, or just to recover some costs and get some things done.
Maybe a shrink is a great transition to a much more powerful third gen design. This is worth thinking about on a few year timeline, but only if we are selling something and getting things done and made now; otherwise, people are going to drop off the wagon. Seriously. They just will, and they will because P1 continues to age.
Re: Linux, etc...
At 100Mhz, this chip can present a GUI, run a lot of controls and sensors, generate sounds, process a lot of data, deliver fine grained control over so many GPIO pins it's nuts, and it can do so without an OS, and in ways that are not difficult.
I still think that is an extremely valuable proposition at our current power consumption. Sure, smaller processes, optimized through zillions in volume production get down to very modest power levels, but they come with a lot of entanglements. This chip does not. I think that's worth a considerable amount, but that's me.
When I read this discussion, I want to see the business side thought about more, because we are at a crossroads because we didn't think about the business side of things very much in the design phase. Again, that's fine. Many of us feel it's worth it to have done it that way, so here we are. Before we jump off cliffs or doom a great design out of hand, let's have a rational talk about what is possible. And based on that possible, figure out what, if anything should be done to maximize our futures.
What can be done, not what can't. It was a lot of fun getting here wasn't it? Damn right it was. Now let's own our work and talk about the possible. And more importantly, if we have failed and we have to punt, let's own that too and define what will succeed. I'm sick of chasing a tail around wondering what makes sense, and I know I am not the only one. It was fun stuffing features in, now we gotta do the work to figure out what that all means.
I'm for getting the design packaged and tuned up in this process and out the door so it can do some good. Anything else puts years in front of us and I'm so not up for that. Not without something in the can we can be working with, on, and for to fund the activity over the long haul.
Cool !! That means the ~170mW a P2 can reach, when emulating a P1, (20MHz), should deliver you 100,000,000 ?
What order number should Parallax use, when sending you the invoice ?
[Where I live, price sensitive means people worry about, well, price, not that 'W' thing]
jmg,
You have a much better grasp of power utilization and ASIC's than I do.
1) What do you think a realistic max wattage is for the P2?
2) Based on Chip's initial post, and clock gating, I feel that 3.5W is a far more likely maximum, with eight cogs going full blast @ 160Mhz. Do you think that is more likely than 5W?
3) Personally, I suspect than in most applications, P2 will not be going anywhere near full blast with all eight cogs. I think "typical" power usage will be well below 1W, more like 0.5W. What do you think?
4) I think 170mW @ 20Mhz would be a killer chip for many uses!
Not at Full throttle, but I calculate it can emulate a P1 (same opcode speed - ignoring smarter opcode gains for now) at ~170mW, so it can do useful work, at well under 1W.
So do I, and the funny thing is we still get spiffy video at 20Mhz. Will dance circles around P1. Just saying as a point of reference.
@JMG, totally with you on that. I think we have a case of unrealistic expectations in play here, not something that is a failure. We need to reset, reframe and figure out what makes sense given this design, and once we understand that better, maximize it. We've got a good design, capable of a lot over what now appears to be a very wide range of power / performance ranges. Sweet!
The "realistic max wattage" for P2, is ultimately what the package and thermal management can handle
This has morphed a little from a Electronic optimise problem, to a Thermal one.
( ie it looks like the core can run ahead of the package/cooling.)
Of course, that's also how intel has designed CPUs for quite a while now - start with power, and work backwards.
I would start looking for the worlds thermally best TQFP128 (0.4 or 0.5mm) or TQFP144 & try to avoid BGA, if at all possible.
One with exposed metal on top and bottom would be interesting....
That sim run excluded RAM, but also did not properly simulate Clock Gating. So there are many variables in play.
Hopefully Clock Gating gains dominate, but the package-limit area is looking like 3W Tops.
That's why good clock control looks like it matters more now.
Chip has indicated this is not hard, given he already gates clocks to COGs.
VCore control does not need any chip changes, and COG Temperature sense, is very small.
One COG at full speed will be 625mW, but very few systems will need Timers AND CPU at 160MHz
All other COGS (at the higher VCore) can give P1 performance, for another 625mW
Well said, a little long but well said!!!
Currently we don't have all the facts, that's for sure. Until we do we cannot (well Chip & Ken) cannot make any hard decisions. So we can just discuss options.
Most don't like 5W and that is a problem. However some will use it at anyway.
While I understand how this power crept up on us, I am not sure if any of my designs I have in mind would use 2W, and likely much less. Using the SETASK and making some tasks idle allows us to easily slow each cog individually down in 1:16 clock increments.
I have advocated a number of possibilities including the P1B & P1C. I have attempted to explain where I see the extra power usage crept in (not all wish to agree). My overall preference is hopefully still with the P2. I just want to be sure we can offer a suggested alternative to Chip if the P2 is going to be delayed for a while due to reconfig or costs.
But this thread should examine some real possibilities (I know without a lot of hard data) of how we could save some things on P2. Each may only save a little, but each has a *8 multipier, and a number of little savings add up to reasonable savings. That's precisely what happened the other way over time. I don't think it is going to magically fix itself.
@Cluso, yeah I do long. Sorry. But we all know that by now.
And I must emphasize, for each of those little cuts, we must ask whether or not the scope of capability isn't equally well addressed by an appropriate power and clock.
I've been thinking through scenarios myself, and just treating it like a P1 with extras, with a 1W budget, gets people a ton of capability. We really need to think about that.
Not if the power consumption of the MCU you choose increases the price of the whole design.
Ross.
How do you get 170mW @ 20MHz ?
(170mW @ 20MHz) *8 = 1.36W @ 160MHz
(5W @ 160MHz) / 8 = 625mW @ 20MHz
There is using a P1, and there is multiple P1 chips, and there is a P2, and various power ranges * clock = heat trade-offs, and then there is something else... We are quite used to running P1 chips near max clock. I'm not so sure we max them out in terms of compute, etc...
With this one, running at max isn't necessarily a given, so what uses cases take what? That's what I'm after. Expectations ran high, and they did so for a long time. Time to reset them realistically.
@Cluso, he's factoring in various voltage scenarios in addition to the raw clock / power ratio.
I will be more short.
This is about sustainability. It is a quit big hit for Parallax. Going public is out of question. We are talking about selling the (walnut) farm.
Parallax is privately owned an that is one of the reasons they are able to archive what they are doing. I just was once down there in Rocklin. This company rocks.
Its not just the customer service they do excellent. It is also the workplace for 60+(?) people they provide. Chip and Ken (and all those other guys and gals working there) are:
-dedicated
-smart
-willing to work hard
-fun to be with
But there are just 60+ people and just one Ken, one Chip and one Beau. Them try but they can't walk on water and do wonders.
But P2 is overdue. It took now 6+ years to get where we are.
All those discussions about a prop 1.5 with limited features are hopeless. I may be hard here, but this may end up as a big joke in the industry. This should not happen.
There is no time anymore to develop another year or two. This thing needs to get out.
Do not slash ANY function. Add serdes and usb support as planned. Add different clock speeds for cogs if that helps.
And live with it. Yes 5 watts. horrible for mobile devices. But of NO concern in any industrial application.
Sure. If Parallax can pull out $1m somewhere out of some pocket it would be great to go to a smaller process and more speed/less power.
Maybe all of us should spend some money on lottery tickets dedicated to Parallax. You never know.
Enjoy!
Mike
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Below you see one of the shortest @potatohead posts ever...
[/edit]
Sell them, make the money, do the shrink, continue on. Precisely. A lot is possible. We need to focus on that.
By following Atmel's Power scaling, I took 4.5V and 2.7v to be conservative, and that gives
4.5*2.2/2.7*1 = 3.66666 power ratio 625mW/ans = 170.454 mW
( Suggests 1.1-1.2V core voltage.)
This also is clear from the Pt = SumOf(Cpd * Ft * Vc^2) - high Vcc is only mandated if you want High MHz, at low MHz you can drop both Ft and Vc
Now, each time there is a push/pop/call/ret, all of these flops toggle. If the LIFO used a SRAM and a pointer, no doubt a lot less registered bits toggle. Could this result in a reasonable power saving ???
I think sometimes slowly, but long form. That's an artifact of the kind of work I've done for way too many years. It involves picking through a lot of requirements, multi-departments, MAKING BUSINESS CASES (which often suck huge, mind you, but I can do them), and then presenting what is possible.
If it were me on this?
I would full stop, other than Chip continuing to optimize what we've got with OnSemi, and before doing another thing, drop some $$ on getting the right people, some outsiders to this whole thing who have experience in markets we think likely, lock 'em up, feed them as necessary, and don't let 'em out, until some of the possible is known to the point where we know we can fund a future or not. Might take a week. I'm serious. Nobody will want to be in that room after the second day. That is what gets it done.
Do not have Chip in that room. I mean that too.
Then move on that info. Finish it.
And I've done something similar to that in the past to get past stuff like this. It works, and it sucks for everybody, and people hate you, until they love you when it's working nicely afterword.
I cannot overemphasize how important it is right now to understand what is possible with the product of our work. It's a lot of work! It needs to pay off, and I believe it can.
Now you are using a factor of 3.7.
Something is not right here.