Lament
John Abshier
Posts: 1,116
My grandmother lived until 99. My dad is 92 and still bales hay. I am 67. But I think I will not live to see a Prop 2. I took part in the original forum discussion on the Prop 2--More cogs versus more memory. At numerous Prop Expos I saw someone say "Wouldn't it be nice..." Chip's eyes would light up and I would add another quarter to the Prop 2 ship date. A common theme from the beginning has been "we need it for high quality graphics." I don't understand this, but it is what it is. Chip is one of the smartest people I have met. Up there with Buckminster Fuller. But he doesn't have the discipline to get the Prop 2 out the door. Six months ago at the UPEW, Beau found the fatal error. Now instead of talking about "Describe your project to get an early Prop 2 board from a shuttle run" we are still talking architecture. Today the Prop 2 has less capability than an Atmel ATtiny 85. I can buy an ATtiny 85, The Prop 2 is a mirage.
John Abshier
PS. Hard to believe that I have been watching Prop 2 development for over 10% of my life.
Edit: I am now 69. Latest time sink de jour is LUT sharing. I am bothered that I see nothing about development of HLLs. I would prefer Spin, but would settle for FORTRAN, C, LUA, Python, or others.
John Abshier
PS. Hard to believe that I have been watching Prop 2 development for over 10% of my life.
Edit: I am now 69. Latest time sink de jour is LUT sharing. I am bothered that I see nothing about development of HLLs. I would prefer Spin, but would settle for FORTRAN, C, LUA, Python, or others.
Comments
Here's the crux of the issue, Chip was working on the Verilog right up until lock-in for the fab. In that time he found some problems and non-optimal issues that he said "if we have another fab run" he would fix. Well, the fab run failed because the process was too different than the process the chip was designed for.
The new fab run costs half what a TSMC run costs, so he's taking the opportunity to a) fix the non-optimal things b) refine the Verilog c) make significant changes to improve the likelihood of success d) adding some features people cried for after the last fab when gold.
For some of us, the sorely needed new features are necessary, for other features they come as essentially "free" to Chip in the process of accomplishing his other goals.
Chip isn't going to invest his own hard earned money in something that isn't right, simply for the ease of "getting it out the door". Chip is no dummy and he has someone who can exercise plenty of business perspective (his brother), so far Ken has only made a couple of light remarks.
Just have patience.
So Chip is adding extra features to pass the time until the next fabrication window opens up, and at the time the design will be submitted
While I'm sad about the first batch of ICs not working. In a way, the doubling of HUBRAM makes it worth the wait for me.
I know all the smoke and clamor in the kitchen have some on the verge of dialing 911, but we are on track for a much better Prop2 than we were last April. These last several months, with all the input from the forum members, have been as productive as the prior two years were, working on my own. This is the way to get a project done well.
Please stick around.
Chip
I think you have confused capability with availability.
You can run P2 code, right now, on your bench, so it is not a mirage.
There are plenty of chips announced, but still not in full production release. This is not a rare event
Chip
This is a natural consequence of information exchange. Everyone learns something, from every other's work.
It's like watching a chess game, you almost ever comes with a best move, because you're not emotionally involved in the game.
To you, the worst part of it, is not being emotionally involved, because it's one more of your "sons", just there, at the computer screen, being raised, nurtured and challenged.
Many of us did feel the same before, many not. This can be all the difference in each and everyone's else point of view.
Yanomani
This model is known as the benevolent dictatorship, but unlike Linux, there is a real tangible physical chip being created.
The future of this development model has me excited and afraid at the same time. I welcome the openness of the development process, but I also worry about unscrupulous people using the hard work of Chip and company in ways that would not benefit Parallax.
Chip has the view that silicon design is so expensive that it would be improbable to "copy" the P2 or P3 chip, but I also know there are plenty of jerks that got their money in unscrupulous ways and will spend that money unscrupulously to gain even more money.
I personally think there needs to be some control over this. In my day job I see this exact thing happening and it has been happening for years. The only way they can stay ahead of the copycats is by having a dual license and by being innovative.
The MIT license is an expression of ultimate freedom for all, whereas the GPLv3 gives the original copyright holder the upper hand. For companies that want to extend the Parallax IP and integrate it into their own product without having to subject their own product to the GPL, Parallax could grant a private license that generates income for them. For projects that are truly Open Source, the GPLv3 would not be a hindrance and any changes would they contribute would be the "toll" for using Parallax's code and hard work.
For a "free" project to be successful, you must have a revenue program behind it, you can't just give it away and hope for the best. RedHat is a good example, there are 2 projects which have leveraged their work, which RedHat doesn't generate income from. The difference is that RedHat makes a lot of money off of supporting their product and all of the community users are a ready base of potential customers.
If you can somehow convert Open Source users into paying customers down the road, you can afford to give away your IP.
Parallax is in a different boat, they have a tangible product which you can hold in your hand. The downside is that the silicon can only change very seldomly. With an FPGA product to work along side, full-custom can be a reality that generates additional income.
I think that if Parallax does move towards an open development model, where the "customer" has access to the real IP, they also need to have support and FPGA products on the shelf to fill the pipeline, otherwise customers will go somewhere else for those products.
I also think a premium paid support could go a long way if Parallax has a "soft" product. There is a lot people can get from forums, but at some point they will require expert level support, especially if they base a business or product on it. If it's IP Parallax is providing, they need to get paid in support premiums. Right now Parallax makes the money on the chips and gives away the support; give away the "chip" and they need to pay for "premium" support.
Assuming P2 becomes real, someone wanting a P2 system will be better off buying a P2, simply because the FPGA that can run even ONE COG, is much more expensive, and slower. ( That may change slowly over time. )
P2 is also large - a NIOS core, can fit in a smaller cheaper FPGA, so someone has to really want what P2 has, but in FPGA form.
I can see some hybrid ground, where P2 is sold with a FPGA/CPLD alongside.
a) P2 and smaller FPGA/CPLD, using SERDES / QuadSPI or similar, the CPLD can augment what the P2 does.
b) P2 and a 1 COG FPGA. This is a bump up from P2, but users can get to the register and opcode level.
They effectively buy a 9th custom COG, (right now likely at a lower speed than the P2) alongside the 8 P2 COGs.
Path b) has a place in education and research, but I'm less sure of the industrial commercial viability.
To me, path a) makes more sense commercially, and Parallax has a lot of the support frameworks in place for this already.
Even with a) the footprint is not large, as the P2 can displace many of the smaller FPGA's itself, so it need an application where P2 is not quite enough on its own.
To make money, Parallax can move to a app store model, where proven IP is there to buy, as users need it.
The P2 we almost had was excellent. This one blows that one out of the water, assuming the better half of all the great ideas put here make the cut. I really was disconcerted at the set of increasingly bold changes beginning when I felt it all "so close", and an exchange between me and JMG got me to really thinking about it.
Really, the safe thing to do would have been to touch as little of it as possible, clean up the design, vet it and run it through fab. The bold thing to do is pretend that one would have been fine had it not been for the trouble. If it's gonna get done this way, then it's gonna get done, and that means a whole pile of the rules we know well are all under reconsideration.
They have to be. There is no baseline to compare to.
A whole bunch of things change when this process is validated. I'm as excited about that as I am silicon, because it is potentially disruptive and most of us here know what that means.
Truth is, we are all older and this has taken a long time. That is hard. I don't like it either. But, I loved what I saw on my FPGA. And that's old news now.
Very soon, Beau will have completed the manual layout stuff needed to drop this design in. Synth can begin, and we know now that synthesis can be tweaked a little on the way through, though it's not cheap. When Beau gets it wrapped up and Chip is once again on the critical path, we will see a freeze and commit, like we should.
Then the images go out, we start coding and we find out if there is trouble. At the same time, drivers are getting done, documents, sample programs, GCC can get sorted, maybe we will see Ross jump in once he knows it's a go, etc...
I'm going to be lazy and not go search out the forum member I exchanged words with a few days ago, but they were along the lines of:
We will be able to do real time, process control, sensors, feedback, etc... and do so with a nice display and user input all on a chip with NO OPERATING SYSTEM.
Guys, that is where the magic is. We've all run lots of stuff. Some of us have been out of the game for a while, others are pros, etc... and even the little P1 can do some amazing things and do so easily. It's just not quite enough, though it packs a punch well above it's weight class anyway. And that is why we all came here.
What happens when you get a Pi, or some other small system? There is an OS, drivers, kernels, user land, and on it goes. A whole lot ends up between you and the control task at hand. On the P2, in SPIN which will run about as fast as PASM will on P1, you will be able to put a little bit of PASM right there where it's needed, and it's going to work like the P1 does. Easy. And that, by the way, is an excellent and very lean way to learn assembly language too. I can't wait.
PropGCC is going to work, and with these changes, be faster. Once the core libraries are sorted out, drivers done, people are going to be able to build and run fairly big programs. Game changes once that is possible, and everybody knows it based on just how much we made P1 do.
Some of these features are to maximize the chip. Many people won't need 'em, but they will need the bits of code to come together like they do on the P1, and for the most part, that is intact and so long as it is, the secret sauce is there.
Some of these things won't make it, or they will get pushed to P3, who knows? Trust Chip on it. He likes it lean, simple, and that isn't going to change at all, because doing that gets away from why he's doing this in the first place. I believe that.
Because of that delay Chip and Ken ended up talking very openly with the Propeller community here about things. That created an amazing synergy with the community, which has a LOT of experts in it, stepping up and instead of complaining about the failure they actually started offering their knowledge to help solve problems. As a result development progress went through the roof and we now have a much more amazing chip in the works that will get done very soon.
While this has been great for the P2, I don't see is stopping there. The P3 will have a VERY short dev cycle and will be a revolutionary leap forward in how systems design is done. Systems designed from the ground up Without An Operating System. NO ONE can do that today at the level that the P2/P3 will do.
We just need to buy enough P2 chips to get the funding to Parallax to make the first P3 chip run.
We are not getting a P2. We are getting P2.9.
My dream for the P3?
Drop from 180 to 90 process, double cores to 16, use the extra die space to pack in a ton of Cog ram for amazing RT control or huge local fast data / cached program calls, eliminate the dedicated Hub chip ram (moved to the cogs) with a big DDR memory module stacked on top of the chip taking place of the Hub ram. Other than extending the cog memory pointer all of that has already been worked out in the P2 discussion!
I don't have the resources to do this, so I will toss it out as one example of a "think about this", but can you imagine a 1GHz 16 core Prop3 as a rack mount server appliance? How much performance could be gained JUST from eliminating the OS overhead? Security? LOL no OS to exploit!
You're not alone and I know that Chip understands the implications of such a delayed release. He already realizes that he's taken a pure R&D-driven route on this project without consideration to a more productive business model with smaller design revisions. My job is to support him and provide the environment to achieve this goal, at any cost. The more we have into this project, the more we need to complete it. Chip wants this finished more than anybody.
Forum users include many engineers, and although they appreciate the business side, most of us won't understand what all of these feature requests mean to the company in the short-term unless you sat through our meetings and participated in our financial planning. We shouldn't be entertaining any more feature requests now. Two hours, 30 days - whatever - these time estimates are never accurate and shouldn't even be discussed. They have serialized dependencies with layout and synthesis and may take months to get the design right. Every design component gets complex before it's made simple. All of us should discourage more features for this reason, and for the complexity of trying to document them and explain them.
Yet there's a very important component to this kind of crowd-sourcing. There's a ground swell of support around P2, and if Parallax and the community manage it correctly we could be releasing the most open core in the world. I'm reading all of these posts, especially the ones pertaining to open cores and licensing.
We're over $4M into P2 development, maybe more. I can add up all the numbers and then it's not a surprise anymore.
I share your frustration, but this is where we are. I'll turn that frustration into appreciation for the Parallax team. - without their ongoing efforts in education, support, new products and marketing the P2 design wouldn't be possible. This cycle feeds itself since all of their efforts tend to evolve around BASIC Stamps and Propellers.
It's not a normal business by any means. Truly frustrating at times but highly rewarding at other times. If we were purely financially-driven it wouldn't be nearly as exciting for Parallax and the customers.
I promise I'll FedEx the first P2 samples to Leavenworth, Kansas no matter how many Atmels or ARMs you are using.
Ken Gracey
I'm not trying to issue a gag order on anybody. This is a free place and we can discuss any features we want, but I encourage the contributors to understand that all of these requests have implications and a financial/opportunity cost. Chip has to make these decisions and do it very effectively, favoring completion.
Like you, I also see the need to take advantage of any improvements that produce a high-performance C compiler. But because I don't understand the real design issues and really want this project finished I'm quiet on this point.
Once we have a chip in hand we still have programming tools, hardware, testing, data sheets, documentation and marketing ahead of us.
Thanks Ken!
Atta boy. Me too. It almost feels like the technology available to us (DDR RAM, SRAM, manufacturing processes) continues to change and that if we try to keep up with it we will never finish. However, just like buying a computer it saves a bunch to be a half-generation or more behind the latest available process. The idea about crowd funding $2M through Kickstarter for a faster process was an interesting one, however.
Ken
Take twenty times five on it!
At least I'll have an opportunity to destinate my PP account for a better purpose, other than reloading my Skype account credit basket!
Yanomani
-Phil
-Phil
Phil
Part of this can be someway alleviated by two fundamentals of education, a field where Parallax soars:
-Example and coaching.
The worst part of all, for a newcomer, will be understanding as fast and clear as possible, how exactly the Propeller line can help soving its problems, at all.
The Parallax hosted Learn, Obex and forum initiatives are a must in this process.
The more everyone can add or help them achieving their goals, the more it'll spread the overall good-feeling, even in cases where the Propeller would not be the best fitting option, but sure, it always will be a desired to learn one.
Only my two cents.
Yanomani
The problem is that people who need to be designing product with P2 chips (big sales wins for Parallax to make a reasonable ROI) won't even think about it if it doesn't have enough capability. The extra HUB RAM is a huge win in that respect. Built-in SERDES will be critical for design wins especially if P2 would be considered as a SPI slave peripheral to another chip. Having the HUB execution instructions should at least be entertained long enough to decide if they are practical.
DDR2 is simply too big a change risk to consider at this point - period, no ifs, ands, or buts. It should seriously be considered for a quick update within a year or two of P2 release though.
I always thought that HUB execute capability should be "a next device" feature, but I'm beginning to wonder now if the risk is not too big. HUB execute should bring much more larger applications power to the table for the people who need it. It would be very useful for 200MHz processor to run a large-scale application at 200MIPs per core. Having fractional performance caused by needing an LMM interpreter will put off customers who are not forumists, educators, or scribblers.
Without good performance (and practical development tools), ARM will beat you every time where it really counts regardless of how much extra circuitry people will need (it's pretty funny to have seen the number of I2C muxes in some high end high volume products that use ARM).
Chip has had an opportunity to make improvements because of some kind of an induced delay (I have a good idea what it is, but won't say here). The design needs to be frozen very soon though. If the chip gets frozen after the next big FPGA update, I'll be happy enough. Getting it out is important. Getting it out right (and all the meanings of it) is more important.
Considering the design cycle time to date, missing a big feature will be devastating. I hope Parallax has done enough research to understand what are the right features. I love the idea of Chip fulfilling his dream, and hopefully enough customers share his dream to make a positive ROI for Parallax.
I use to be a big supporter of freezing the design and getting it out in the wild....however, these last design changes, increasing HUB memory and executing directly from HUB with little performance lost, are two awesome features and game changers. Unbound by COG memory limits puts the P2 in a new league. Great feature! 200MIPS per COG, 256K HUB, eight multiprocessors (not limited to 2K), video capabilities that don't require a PHD in signal processing...and...and no interrupts. I am happy with the design...and the wait is going to be worth it
Coupla basic things got traded for it; namely, any COG any PIN for the high speed DACS, which means we will have to start COGS in order once in a while.
But, doing that compared to all the sweat each of us contributed to understanding and making LMM practical?
No brainer.
I'm very pleased we are going to do it. It shocked me at first, and I ranted over it, and I deleted that rant after the implications sunk in.
Me too.
-Phil