Wish it was SERDES. I begged, and begged, and begged.
I know you did. I just didn't have time to venture into what it would take to make a universal serializer/deserializer with all kinds of modulation schemes, bit-stuffing, and so on. Attacking that problem is as hard as video, it seems. Next time, we will incorporate a SERDES, though.
I know you did. I just didn't have time to venture into what it would take to make a universal serializer/deserializer with all kinds of modulation schemes, bit-stuffing, and so on. Attacking that problem is as hard as video, it seems. Next time, we will incorporate a SERDES, though.
Ah, the power of HDLs... You can retain all the IP you've already generated and just add new stuff when your brain's not so fried and you're not so under-the-gun. So glad to hear there will be a next time!
I don't know if it helps to point out that SER is still an order of magnitude faster than the fastest Transputer link. It's fabulous to have a machine-supported interprop channel.
I'm still not seeing it. How is TASKSW skipped over the first time?
It's not skipped over. Sorry about that.
What happens, though is that TASKSW (1st time) saves the PC into pc+0, then loads the PC from pc+1, which points to thread, which would have been the next instruction, anyway. Then, the loop keeps executing for each task in a round-robin fashion.
What happens, though is that TASKSW (1st time) saves the PC into pc+0, then loads the PC from pc+1, which points to thread, which would have been the next instruction, anyway. Then, the loop keeps executing for each task in a round-robin fashion.
OK! That's what I thought would happen. Now, in the original example, would that mean that there would have been five TASKSW calls before the first iteration through the loop, the first four being a jump back to loop (the TASKSW statement itself) with a PC+1 adjustment to each of the pc[] entries?
OK! That's what I thought would happen. Now, in the original example, would that mean that there would have been five TASKSW calls before the first iteration through the loop, the first four being a jump back to loop (the TASKSW statement itself) with a PC+1 adjustment to each of the pc[] entries?
A question came up at the conference yesterday regarding how Prop I assembler code will be portable to the Prop II.
Seems for most Prop I PASM only a few small changes will be required to get it running. Before, that is one starts looking at optimizing using new Prop II features.
Is there a porting guide anywhere that points out the changes to look for?
Most of the P1 stuff we do today works just fine. The workhorse instructions are pretty much unchanged. You do have to think about the pipe line more because it has more stages and sometimes things need to be done at a particular stage, or you need to use a delay effect instruction to avoid nop instructions.
Getting at pins is more complicated, and the pins are smart now and not anywhere close to emulated now either. Gotta have the real chip to really grok the pins. I'm waiting on that personally, not connecting much to the FPGA at the moment.
Video works much differently, though I think it's generally better, faster, easier, etc...
IMHO, a P1 port might go fairly easy if it's not touching too much, but then again, most things in PASM are touching the hardware to get speed, enable capability.
The new instructions change things. We can use REP on lots of loops where before we would invoke a register and DNJZ or CMP.
Most things need a rewrite, and they will be smaller when done, more capable.
Anything with math is going to be huge! P2 has most things people need in hardware so whole routines go away replaced by a few instructions.
Thing is I've got this Z80 emulator which has been patiently waiting for Prop II because it will no longer need the complexity of external RAM there. Then there is PullMoll's emulator. They are going to want moving to the Prop II.
In my case the emulator engine does nothing with hardware and will probably port easily. No doubt it can be optimized with P2 instructions once it is up and running.
Actually I'm planning on migrating all the Spin parts to C where I guess the equivalent of FSRW and such already exit.
Then there is the FFT. Again no hardware involvement but certainly the complex multiplications can be turbo charged somewhat. Some pointers there would be helpful.
Just hope I can find the time to get into all of this.
Doug touched on the various points well. Based on what I've seen, a direct port will usually be possible because most of the instructions from the Prop 1 function identically in the Prop2.
Off the top of my head, here are some of the details:
* Pins are not addressed as INA and OUTA anymore, the register is now called PINx where x is ABCD
* Pins are configured to do different things (smart pins as Doug alluded to) and must be setup prior
* Self modifying code must account for the change being effective on the 3rd clock after the instruction (see line 958 in doc TXT)
* Memory read instructions take 3..10 clock cycles instead of 8..23
More semantic changes are abound, such as the counters support many more modes.
If you are actually reimplementing code from the Prop 1 to the Prop 2, there are many changes that you will implement such as:
* REPS for simple immediate loops
* REPD for variable iteration loops
* PTRx for HUB memory transfer
* INDx for COG memory transfer
* Using the CLUT for lookup, stack, buffer, cache, or CLUT
* Rewriting of code to take advantage of P2 specific instructions like the math instructions, bit manipulation, and data manipulation.
* Cooperative multi-tasking with TASKSW or temporal multi-threading via SETTASK/JMPTASK
An important item to note is looping. On the P1 looping is typically done with DJNZ, the P2 has this same construct and actually requires that you use this if you plan to perform any branch instructions within a loop. The REPx instructions will not work if you have a branch occur within the loop, they are only intended for compact local code loops.
Those are some of the specific differences, but by no means is it a complete list.
Thanks Pedward. That is certainly enough to inspire me to get started. Looks like there is a lot of new instructions that will speed up the emulation beyond a simple port as well.
Now that the emulator has the chance to run CP/M without external RAM it seems the first available Prop II boards will come with stonking great SDRAMS attached:)
Thanks Pedward. That is certainly enough to inspire me to get started. Looks like there is a lot of new instructions that will speed up the emulation beyond a simple port as well.
Now that the emulator has the chance to run CP/M without external RAM it seems the first available Prop II boards will come with stonking great SDRAMS attached:)
heater: It will be much simpler that you think to convert ZiCog. Only a few places where any changes are necessary.
I just tried porting my P2 debugger back to P1 and it is quite simple.
getcnt, setp, etc instructions are the main issues. But you will have to be careful of self-modifying code due to the pipeline delays.
Of course, these simple changes will not use the new features of P2. But who cares because it will run at least 8 times faster without this.
Documentation has slowed down quite a bit lately. As discussed earlier, a big factor is the performance issues we've been encountering with Google Docs. I have been discussing the idea of "moving" the documentation to wikispaces, where I believe it can be more flexibly implemented (among other things). However, the Propeller conference has be second-guessing this approach. There is clearly new, official documentation (web-based) that will be forthcoming. At the same time, there was mention of working with the community documentation efforts, but not much in the way of details.
So where does that leave us? Continue updating GDocs for the moment? Go ahead with migrating the documentation to wikispaces? Rework the community documentation to complement the official documentation? Something else entirely?
Here is an updated visual decoded instruction set for the P2. The spinfile also contains the conditional assembly parameters too.
Added are the PTRA/PTRB for rd/wr-byte/word/long/quad-c instructions and INDA/INDB for cog addresses (as shown below).
My info shows the second one is a spare opcode. I checked the latest pdf too.
Are you looking at the latest info or where are you seeing the second coginit?
My info shows the second one is a spare opcode. I checked the latest pdf too.
Are you looking at the latest info or where are you seeing the second coginit?
It is in the list at the end of the GDoc version. This looks like it was a verbatim copy from an earlier post by Chip in this thread. But it's not mentioned in any of the details sections.
I believe I read somewhere that the bus between the hub and the cogs was 128 bits wide, which would make sense for the xxQUAD operations to be able to atomically latch the data. However, why does the RDQUAD require the additional (two?) clock cycles before they can be read? Is this only when the quads are mapped to registers? I'm guessing not, as the RDxxxxC operations will also block for those same two clock cycles (when the cache is dirty).
(note: This is only partially a clarification question. I'm also just curious about the internal workings of that mechanism.)
I believe I read somewhere that the bus between the hub and the cogs was 128 bits wide, which would make sense for the xxQUAD operations to be able to atomically latch the data. However, why does the RDQUAD require the additional (two?) clock cycles before they can be read? Is this only when the quads are mapped to registers? I'm guessing not, as the RDxxxxC operations will also block for those same two clock cycles (when the cache is dirty).
(note: This is only partially a clarification question. I'm also just curious about the internal workings of that mechanism.)
Yes, the hub to cog bus is 128 bits wide.
From the info I summarised into an Excel Spreadsheet, all Reads (Byte/Word/Long) take an extra 2 clocks (ie 3..10 clocks). The cached versions vary depending upon whether they are in the cache or not. If they are in cache then it is a single cycle, otherwise there appears to be 3..10 clocks. Therefore, I presume there is some setup (2 clocks) required when interfacing the reads to the hub.
Comments
I know you did. I just didn't have time to venture into what it would take to make a universal serializer/deserializer with all kinds of modulation schemes, bit-stuffing, and so on. Attacking that problem is as hard as video, it seems. Next time, we will incorporate a SERDES, though.
Thanks Chip.
Ah, the power of HDLs... You can retain all the IP you've already generated and just add new stuff when your brain's not so fried and you're not so under-the-gun. So glad to hear there will be a next time!
I don't know if it helps to point out that SER is still an order of magnitude faster than the fastest Transputer link. It's fabulous to have a machine-supported interprop channel.
I'm still not seeing it. How is TASKSW skipped over the first time?
It's not skipped over. Sorry about that.
What happens, though is that TASKSW (1st time) saves the PC into pc+0, then loads the PC from pc+1, which points to thread, which would have been the next instruction, anyway. Then, the loop keeps executing for each task in a round-robin fashion.
OK! That's what I thought would happen. Now, in the original example, would that mean that there would have been five TASKSW calls before the first iteration through the loop, the first four being a jump back to loop (the TASKSW statement itself) with a PC+1 adjustment to each of the pc[] entries?
That's right.
Seems for most Prop I PASM only a few small changes will be required to get it running. Before, that is one starts looking at optimizing using new Prop II features.
Is there a porting guide anywhere that points out the changes to look for?
Most of the P1 stuff we do today works just fine. The workhorse instructions are pretty much unchanged. You do have to think about the pipe line more because it has more stages and sometimes things need to be done at a particular stage, or you need to use a delay effect instruction to avoid nop instructions.
Getting at pins is more complicated, and the pins are smart now and not anywhere close to emulated now either. Gotta have the real chip to really grok the pins. I'm waiting on that personally, not connecting much to the FPGA at the moment.
Video works much differently, though I think it's generally better, faster, easier, etc...
IMHO, a P1 port might go fairly easy if it's not touching too much, but then again, most things in PASM are touching the hardware to get speed, enable capability.
The new instructions change things. We can use REP on lots of loops where before we would invoke a register and DNJZ or CMP.
Most things need a rewrite, and they will be smaller when done, more capable.
Anything with math is going to be huge! P2 has most things people need in hardware so whole routines go away replaced by a few instructions.
In my case the emulator engine does nothing with hardware and will probably port easily. No doubt it can be optimized with P2 instructions once it is up and running.
Actually I'm planning on migrating all the Spin parts to C where I guess the equivalent of FSRW and such already exit.
Then there is the FFT. Again no hardware involvement but certainly the complex multiplications can be turbo charged somewhat. Some pointers there would be helpful.
Just hope I can find the time to get into all of this.
Off the top of my head, here are some of the details:
* Pins are not addressed as INA and OUTA anymore, the register is now called PINx where x is ABCD
* Pins are configured to do different things (smart pins as Doug alluded to) and must be setup prior
* Self modifying code must account for the change being effective on the 3rd clock after the instruction (see line 958 in doc TXT)
* Memory read instructions take 3..10 clock cycles instead of 8..23
More semantic changes are abound, such as the counters support many more modes.
If you are actually reimplementing code from the Prop 1 to the Prop 2, there are many changes that you will implement such as:
* REPS for simple immediate loops
* REPD for variable iteration loops
* PTRx for HUB memory transfer
* INDx for COG memory transfer
* Using the CLUT for lookup, stack, buffer, cache, or CLUT
* Rewriting of code to take advantage of P2 specific instructions like the math instructions, bit manipulation, and data manipulation.
* Cooperative multi-tasking with TASKSW or temporal multi-threading via SETTASK/JMPTASK
An important item to note is looping. On the P1 looping is typically done with DJNZ, the P2 has this same construct and actually requires that you use this if you plan to perform any branch instructions within a loop. The REPx instructions will not work if you have a branch occur within the loop, they are only intended for compact local code loops.
Those are some of the specific differences, but by no means is it a complete list.
Now that the emulator has the chance to run CP/M without external RAM it seems the first available Prop II boards will come with stonking great SDRAMS attached:)
I just tried porting my P2 debugger back to P1 and it is quite simple.
getcnt, setp, etc instructions are the main issues. But you will have to be careful of self-modifying code due to the pipeline delays.
Of course, these simple changes will not use the new features of P2. But who cares because it will run at least 8 times faster without this.
So where does that leave us? Continue updating GDocs for the moment? Go ahead with migrating the documentation to wikispaces? Rework the community documentation to complement the official documentation? Something else entirely?
---------------------------------------------------------------------------------------------- Instuction set for Propeller II ..... -opc-- opcode- operand zcri cccc opcode- operand zcri cccc opcode- operand zcri cccc ---------------------------------------------------------------------------------------------- 000000 wrbyte D,S/PTR 000p ---- rdbyte D,S/PTR -01p ---- rdbytec D,S/PTR -11p ---- 000001 wrword D,S/PTR 000p ---- rdword D,S/PTR -01p ---- rdwordc D,S/PTR -11p ---- 000010 wrlong D,S/PTR 000p ---- rdlong D,S/PTR -01p ---- rdlongc D,S/PTR -11p ---- 000011 coginit D,S ---0 ---- ───── *** see table for opcode 000011 r=1 below *** 000100 mul D,[#]S ---1 ---- ───────────────────────────┐ 000101 scl D,[#]S ---1 ---- ─────────────────────────┐ │ ┌ setacca D,[#]S 000- ---- 000110 enc D,[#]S ---- ---- │ └──┤ setaccb D,[#]S 010- ---- 000111 jmpret D,[#]S ---- ---- call/ret │ │ maca D,[#]S 100- ---- 001000 ror D,[#]S ---- ---- │ └ macb D,[#]S 110- ---- 001001 rol D,[#]S ---- ---- │ 001010 shr D,[#]S ---- ---- │ ┌ movf D,[#]S 000- ---- 001011 shl D,[#]S ---- ---- └────┤ qsincos D,[#]S 010- ---- 001100 rcr D,[#]S ---- ---- │ qarctan D,[#]S 100- ---- 001101 rcl D,[#]S ---- ---- └ qrotate D,[#]S 110- ---- 001110 sar D,[#]S ---- ---- 001111 rev D,[#]S ---- ---- 010000 mins D,[#]S ---- ---- 010001 maxs D,[#]S ---- ---- 010010 min D,[#]S ---- ---- 010011 max D,[#]S ---- ---- 010100 movs D,[#]S ---- ---- 010101 movd D,[#]S ---- ---- 010110 movi D,[#]S ---- ---- 010111 jmpretd D,[#]S ---- ---- calld/retd 011000 and D,[#]S ---- ---- test 011001 andn D,[#]S ---- ---- testn 011010 or D,[#]S ---- ---- ┌ setinda #S 0000 0001 011011 xor D,[#]S ---- ---- │ setinda S 0000 0011 011100 muxc D,[#]S ---- ---- │ setindb #D 0000 0100 011101 muxnc D,[#]S ---- ---- │ setindb D 0000 1100 011110 muxz D,[#]S ---- ---- │ setinds #D,#S 0000 0101 011111 muxnz D,[#]S ---- ---- │ setinds #D,S 0000 0111 100000 add D,[#]S ---- ---- ┌──────────────┤ setinds D,#S 0000 1101 100001 sub D,[#]S ---- ---- cmp │ └ setinds D,S 0000 1111 100010 addabs D,[#]S ---- ---- │ 100011 subabs D,[#]S ---- ---- │ ┌ fixinda #D,#S 0000 0001 100100 sumc D,[#]S ---- ---- │ ┌────────────┤ fixindb #D,#S 0000 0100 100101 sumnc D,[#]S ---- ---- │ │ └ fixinds #D,#S 0000 0101 100110 sumz D,[#]S ---- ---- │ │ 100111 sumnz D,[#]S ---- ---- │ │ ┌────────── cfgpins D,[#]S 000- ---- 101000 mov D,[#]S ---- ---- │ │ │ 101001 neg D,[#]S ---- ---- │ │ │ ┌──────── waitvid D,[#]S 000- ---- 101010 abs D,[#]S ---- ---- │ │ │ │ 101011 absneg D,[#]S ---- ---- │ │ │ │ ┌ ijz D,[#]S 00-- --- 101100 negc D,[#]S ---- ---- │ │ │ │ │ ijzd D,[#]S 01-- --- 101101 negnc D,[#]S ---- ---- │ │ │ │ ┌──────┤ ijnz D,[#]S 10-- --- 101110 negz D,[#]S ---- ---- │ │ │ │ │ └ ijnzd D,[#]S 11-- --- 101111 negnz D,[#]S ---- ---- │ │ │ │ │ 110000 cmps D,[#]S ---- ---- │ │ │ │ │ ┌ djz D,[#]S 00-- --- 110001 cmpsx D,[#]S ---- ---- │ │ │ │ │ │ djzd D,[#]S 01-- --- 110010 addx D,[#]S ---- ---- │ │ │ │ │ ┌────┤ djnz D,[#]S 10-- --- 110011 subx D,[#]S ---- ---- │ │ │ │ │ │ └ djnzd D,[#]S 11-- --- 110100 adds D,[#]S ---- ---- │ │ │ │ │ │ 110101 subs D,[#]S ---- ---- │ │ │ │ │ │ ┌ tjz D,[#]S 000- --- 110110 addsx D,[#]S ---- ---- │ │ │ │ │ │ │ tjzd D,[#]S 010- --- 110111 subsx D,[#]S ---- ---- │ │ │ │ │ │ │ tjnz D,[#]S 100- --- 111000 subr D,[#]S --1- ---- ─ cmpr ────────┘ │ │ │ │ │ │ tjnzd D,[#]S 110- --- 111001 cmpsub D,[#]S --1- ---- ─────────────────┘ │ │ │ │ │ jp D,[#]S 001- --- 111010 incmod D,[#]S --1- ---- ───────────────────┘ │ │ │ │ jpd D,[#]S 011- --- 111011 decmod D,[#]S --1- ---- ─────────────────────┘ │ │ ┌──┤ jnp D,[#]S 101- --- 111100 ij*** D,[#]S **-- ---- ───────────────────────┘ │ │ └ jnpd D,[#]S 111- --- 111101 dj*** D,[#]S **-- ---- ─────────────────────────┘ │ 111110 tj*** D,[#]S ***- ---- ───────────────────────────┘ 111111 waitcnt D,[#]S 0--- ---- waitpeq D,[#]S 1-0- ---- waitpne D,[#]S 1-1- ---- ---------------------------------------------------------------------------------------------- -opc-- opcode- operand zcri cccc opcode- operand zcri cccc opcode- operand zcri cccc ---------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------- Additional instructions for opcode=000011 with r=1 (coginit has r=0) ..... -source-- opcode- operand --dest--- zcri cccc opcode- operand --dest--- zcri cccc opcode- operand --dest--- zcri cccc ------------------------------------------------------------------------------------------------------------------------------- 000000000 clkset D --------- 0001 ---- ┌ cachex 000000000 0001 ---- 000000001 cogid D --------- 0011 ---- │ clracca 000000001 --01 ---- 000000010 -spare- D --------- --11 ---- │ clraccb 000000010 --01 ---- 000000011 cogstop D --------- 0001 ---- │ clraccs 000000011 --01 ---- 000000100 locknew D --------- --11 ---- │ -spare- 000000100 --01 ---- 000000101 lockret D --------- 0001 ---- │ fitacca 000000101 --01 ---- 000000110 lockset D --------- 0-01 ---- ┌──┤ fitaccb 000000110 --01 ---- 000000111 lockclr D --------- 0-01 ---- │ └ fitaccs 000000111 --01 ---- 000001000 ******* 000000--- --01 ---- ─────────────────────────────────────┘ 000001001 rcvser D --------- --11 ---- sndser D --------- --01 ---- 000001010 pushzc D --------- ---1 ---- 000001011 popzc D --------- ---1 ---- 000001100 subcnt D --------- --11 ---- cmpcnt D --------- --01 ---- 000001101 getcnt D --------- 0011 ---- passcnt D --------- 0001 ---- 000001110 getacca D --------- ---1 ---- 000001111 getaccb D --------- ---1 ---- 000010000 getlfsr D --------- ---1 ---- 000010001 gettops D --------- -011 ---- polvid --------- -101 ---- 000010010 getptra D --------- ---1 ---- 000010011 getptrb D --------- ---1 ---- 000010100 getpix D --------- ---1 ---- 000010101 getspd D --------- --11 ---- chkspd 000000000 --01 ---- 000010110 getspa D --------- --11 ---- chkspa 000000000 --01 ---- 000010111 getspb D --------- --11 ---- chkspb 000000000 --01 ---- 000011000 popar D --------- --11 ---- 000011001 popbr D --------- --11 ---- 000011010 popa D --------- --11 ---- 000011011 popb D --------- --11 ---- 000011100 reta 000000000 --01 ---- 000011101 retb 000000000 --01 ---- 000011110 retad 000000000 --01 ---- 000011111 retbd 000000000 --01 ---- 000100000 decod2 D --------- ---1 ---- 000100001 decod3 D --------- ---1 ---- 000100010 decod4 D --------- ---1 ---- 000100011 decod5 D --------- ---1 ---- 000100100 blmask D --------- ---1 ---- 000100101 not D --------- ---1 ---- 000100110 onecnt D --------- ---1 ---- 000100111 zercnt D --------- ---1 ---- 000101000 incpat D --------- ---1 ---- 000101001 decpat D --------- ---1 ---- 000101010 bingry D --------- ---1 ---- 000101011 grybin D --------- ---1 ---- 000101100 mergew D --------- ---1 ---- 000101101 splitw D --------- ---1 ---- 000101110 seussf D --------- ---1 ---- 000101111 seussr D --------- ---1 ---- 000110000 getmull D --------- ---1 ---- 000110001 getmulh D --------- ---1 ---- 000110010 getdivq D --------- ---1 ---- 000110011 getdivr D --------- ---1 ---- 000110100 getsqrt D --------- ---1 ---- 000110101 getqx D --------- ---1 ---- 000110110 getqy D --------- ---1 ---- 000110111 getqz D --------- ---1 ---- 000111000 getphsa D --------- ---1 ---- polctra --------- -101 ---- 000111001 getphza D --------- ---1 ---- 000111010 getcosa D --------- ---1 ---- 000111011 getsina D --------- ---1 ---- 000111100 getphsb D --------- ---1 ---- polctrb --------- -101 ---- 000111101 getphzb D --------- ---1 ---- 000111110 getcosb D --------- ---1 ---- 000111111 getsinb D --------- ---1 ---- ------------------------------------------------------------------------------------------------------------------------------- 001iiiiii repd #i 111111111 0001 ---- repd D/#n,#i nnnnnnnnn 00#1 ---- reps #n,#i nnnnnnnnn n111 nnnn ------------------------------------------------------------------------------------------------------------------------------- 01000---- -spare- nnnnnnnnn --#1 ---- 01001mmmm jmptask D/#n,#m --------- 00#1 ---- ------------------------------------------------------------------------------------------------------------------------------- 010100000 nopx D/#n nnnnnnnnn --#1 ---- 010100001 setzc D/#n nnnnnnnnn --#1 ---- 010100010 setspa D/#n --------- 00#1 ---- 010100011 setspb D/#n --------- 00#1 ---- 010100100 addspa D/#n --------- 00#1 ---- 010100101 addspb D/#n --------- 00#1 ---- 010100110 subspa D/#n --------- 00#1 ---- 010100111 subspb D/#n --------- 00#1 ---- 010101000 pushar D/#n nnnnnnnnn 00#1 ---- 010101001 pushbr D/#n nnnnnnnnn 00#1 ---- 010101010 pusha D/#n nnnnnnnnn 00#1 ---- 010101011 pushb D/#n nnnnnnnnn 00#1 ---- 010101100 calla D/#n nnnnnnnnn 00#1 ---- 010101101 callb D/#n nnnnnnnnn 00#1 ---- 010101110 callad D/#n nnnnnnnnn 00#1 ---- 010101111 callbd D/#n nnnnnnnnn 00#1 ---- 010110000 wrquad D/PTR supnnnnnn 00p1 ---- 010110001 rdquad D/PTR supnnnnnn 0*p1 ---- rdquadc D/PTR supnnnnnn 01p1 ---- 010110010 setptra D/#n --------- 00#1 ---- 010110011 setptrb D/#n --------- 00#1 ---- 010110100 addptra D/#n --------- 00#1 ---- 010110101 addptrb D/#n --------- 00#1 ---- 010110110 subptra D/#n --------- 00#1 ---- 010110111 subptrb D/#n --------- 00#1 ---- 010111000 setpix D/#n nnnnnnnnn --#1 ---- 010111001 setpixu D/#n nnnnnnnnn --#1 ---- 010111010 setpixv D/#n nnnnnnnnn --#1 ---- 010111011 setpixz D/#n nnnnnnnnn --#1 ---- 010111100 setpixa D/#n nnnnnnnnn --#1 ---- 010111101 setpixr D/#n nnnnnnnnn --#1 ---- 010111110 setpixg D/#n nnnnnnnnn --#1 ---- 010111111 setpixb D/#n nnnnnnnnn --#1 ---- 011000000 setmula D/#n nnnnnnnnn -1#1 ---- setmulu D/#n nnnnnnnnn -0#1 ---- 011000001 setmulb D/#n nnnnnnnnn --#1 ---- 011000010 setdiva D/#n nnnnnnnnn -1#1 ---- setdivu D/#n nnnnnnnnn -0#1 ---- 011000011 setdivb D/#n nnnnnnnnn --#1 ---- 011000100 setsqrh D/#n nnnnnnnnn --#1 ---- 011000101 setsqrl D/#n nnnnnnnnn --#1 ---- 011000110 setqi D/#n nnnnnnnnn --#1 ---- 011000111 setqz D/#n nnnnnnnnn --#1 ---- 011001000 qlog D/#n nnnnnnnnn --#1 ---- 011001001 qexp D/#n nnnnnnnnn --#1 ---- 011001010 setf D/#n --------- 00#1 ---- 011001011 settask D/#n --------- 00#1 ---- 011001100 cfgdac0 D/#n -------nn --#1 ---- 011001101 cfgdac1 D/#n -------nn --#1 ---- 011001110 cfgdac2 D/#n -------nn --#1 ---- 011001111 cfgdac3 D/#n -------nn --#1 ---- 011010000 setdac0 D/#n nnnnnnnnn --#1 ---- 011010001 setdac1 D/#n nnnnnnnnn --#1 ---- 011010010 setdac2 D/#n nnnnnnnnn --#1 ---- 011010011 setdac3 D/#n nnnnnnnnn --#1 ---- 011010100 cfgdacs D/#n -nnnnnnnn --#1 ---- 011010101 setdacs D/#n nnnnnnnnn --#1 ---- 011010110 getp D/#n --nnnnnnn --#1 ---- 011010111 getnp D/#n --nnnnnnn --#1 ---- 011011000 offp D/#n --nnnnnnn --#1 ---- 011011001 notp D/#n --nnnnnnn --#1 ---- 011011010 clrp D/#n --nnnnnnn --#1 ---- 011011011 setp D/#n --nnnnnnn --#1 ---- 011011100 setpc D/#n --nnnnnnn --#1 ---- 011011101 setpnc D/#n --nnnnnnn --#1 ---- 011011110 setpz D/#n --nnnnnnn --#1 ---- 011011111 setpnz D/#n --nnnnnnn --#1 ---- 011100000 setcog D/#n -----nnnn --#1 ---- 011100001 setmap D/#n ---nnnnnn --#1 ---- 011100010 setquad D/#n nnnnnnnnn 00#1 ---- setquaz D/#n nnnnnnnnn 01#1 ---- 011100011 setport D/#n --nn----- --#1 ---- 011100100 setpora D/#n --nn----- --#1 ---- 011100101 setporb D/#n --nn----- --#1 ---- 011100110 setporc D/#n --nn----- --#1 ---- 011100111 setpord D/#n --nn----- --#1 ---- 011101000 setxch D/#n nnnnnnnnn --#1 ---- 011101001 setxfr D/#n ---nnnnnn --#1 ---- 011101010 setser D/#n --------- --#1 ---- 011101011 setskip D/#n ---nnnnnn --#1 ---- 011101100 setvid D/#n nnnnnnnnn --#1 ---- 011101101 setvidy D/#n nnnnnnnnn --#1 ---- 011101110 setvidi D/#n nnnnnnnnn --#1 ---- 011101111 setvidq D/#n nnnnnnnnn --#1 ---- 011110000 setctra D/#n nnnnnnnnn --#1 ---- 011110001 setwava D/#n nnnnnnnnn --#1 ---- 011110010 setfrqa D/#n nnnnnnnnn --#1 ---- 011110011 setphsa D/#n nnnnnnnnn --#1 ---- 011110100 addphsa D/#n nnnnnnnnn --#1 ---- 011110101 subphsa D/#n nnnnnnnnn --#1 ---- 011110110 synctra nnnnnnnnn --01 ---- 011110111 capctra nnnnnnnnn --01 ---- 011111000 setctrb D/#n nnnnnnnnn --#1 ---- 011111001 setwavb D/#n nnnnnnnnn --#1 ---- 011111010 setfrqb D/#n nnnnnnnnn --#1 ---- 011111011 setphsb D/#n nnnnnnnnn --#1 ---- 011111100 addphsb D/#n nnnnnnnnn --#1 ---- 011111101 subphsb D/#n nnnnnnnnn --#1 ---- 011111110 synctrb nnnnnnnnn --01 ---- 011111111 capctrb nnnnnnnnn --01 ---- ------------------------------------------------------------------------------------------------------------------------------- 1000bbbbb isob D.b --------- ---1 ---- 1001bbbbb notb D.b --------- ---1 ---- 1010bbbbb clrb D.b --------- ---1 ---- 1011bbbbb setb D.b --------- ---1 ---- 1100bbbbb setbc D.b --------- ---1 ---- 1101bbbbb setbnc D.b --------- ---1 ---- 1110bbbbb setbz D.b --------- ---1 ---- 1111bbbbb setbnz D.b --------- ---1 ---- ------------------------------------------------------------------------------------------------------------------------------- -source-- opcode- operand --dest--- zcri cccc opcode- operand --dest--- zcri cccc opcode- operand --dest--- zcri cccc -------------------------------------------------------------------------------------------------------------------------------
P2_Instructions.spin
Added are the PTRA/PTRB for rd/wr-byte/word/long/quad-c instructions and INDA/INDB for cog addresses (as shown below).
------------------------------------------------------------------------------------------------------------------------------- INDA & INDB (Cog addresses $1F6 & $1F7)... ..... (Note: Instructions using indirection ALWAYS execute ) opcode zcri cccc --dest--- -source-- ( Therefore, cccc specify none/postinc/postdec/preinc) ------------------------------------------------------------------------------------------------------------------------------- ------ ---- 00xx 111110110 --------- Dest = INDA ------ ---- 01xx 111110110 --------- Dest = INDA++ ------ ---- 10xx 111110110 --------- Dest = INDA-- ------ ---- 11xx 111110110 --------- Dest = ++INDA ------ ---- 00xx 111110111 --------- Dest = INDB ------ ---- 01xx 111110111 --------- Dest = INDB++ ------ ---- 10xx 111110111 --------- Dest = INDB-- ------ ---- 11xx 111110111 --------- Dest = ++INDB ------ ---0 xx00 --------- 111110110 Srce = INDA ------ ---0 xx01 --------- 111110110 Srce = INDA++ ------ ---0 xx10 --------- 111110110 Srce = INDA-- ------ ---0 xx11 --------- 111110110 Srce = ++INDA ------ ---0 xx00 --------- 111110111 Srce = INDB ------ ---0 xx01 --------- 111110111 Srce = INDB++ ------ ---0 xx10 --------- 111110111 Srce = INDB-- ------ ---0 xx11 --------- 111110111 Srce = ++INDB ------------------------------------------------------------------------------------------------------------------------------- opcode zcri cccc --dest--- -source-- ------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------- PTR (hub address) & RD/WR-QUAD/LONG/WORD/BYTE-C Instructions (i=1 uses PTRx) ..... ------------------------------------------------------------------------------------------------------------------------------- ┌─────────── 0 = PTRA 1 = PTRB │┌────────── 0 = PTRx no update 1 = PTRx updated ││┌───────── 0 = PTRx+Index*Scale 1 = PTRx (post modify) │││ ┌───── Index -32..+31 (nnnnnn = -Index, NNNNNN = +Index) │││ │ Scale is 1=Byte, 2=Word, 4=Long, 16=Quad │││┌──┴─┐ supnnnnnn opcode zcri cccc --dest--- -source-- Expression Uses Initial value Final value ------------------------------------------------------------------------------------------------------------------------------- ------ ---1 ---- --------- 000000000 PTRA PTRA ------ ---1 ---- --------- 011000000 PTRA++ PTRA PTRA += Scale ------ ---1 ---- --------- 011111111 PTRA-- PTRA PTRA -= Scale ------ ---1 ---- --------- 010000001 ++PTRA PTRA + Scale PTRA += Scale (ie Index = +1) ------ ---1 ---- --------- 010111111 --PTRA PTRA - Scale PTRA -= Scale (ie Index = -1) ------ ---1 ---- --------- 000NNNNNN PTRA[Index] PTRA + Index*Scale (ie Index = +NNNNNN) ------ ---1 ---- --------- 011NNNNNN PTRA++[Index] PTRA PTRA += Index*Scale (ie Index = +NNNNNN) ------ ---1 ---- --------- 011nnnnnn PTRA--[Index] PTRA PTRA -= Index*Scale (ie Index = -nnnnnn) ------ ---1 ---- --------- 010NNNNNN ++PTRA[Index] PTRA + Index*Scale PTRA += Index*Scale (ie Index = +NNNNNN) ------ ---1 ---- --------- 010nnnnnn --PTRA[Index] PTRA - Index*Scale PTRA -= Index*Scale (ie Index = -nnnnnn) ------ ---1 ---- --------- 100000000 PTRB PTRB ------ ---1 ---- --------- 111000000 PTRB++ PTRB PTRB += Scale ------ ---1 ---- --------- 111111111 PTRB-- PTRB PTRB -= Scale ------ ---1 ---- --------- 110000001 ++PTRB PTRB + Scale PTRB += Scale (ie Index = +1) ------ ---1 ---- --------- 110111111 --PTRB PTRB - Scale PTRB -= Scale (ie Index = -1) ------ ---1 ---- --------- 100NNNNNN PTRB[Index] PTRB + Index*Scale (ie Index = +NNNNNN) ------ ---1 ---- --------- 111NNNNNN PTRB++[Index] PTRB PTRB += Index*Scale (ie Index = +NNNNNN) ------ ---1 ---- --------- 111nnnnnn PTRB--[Index] PTRB PTRB -= Index*Scale (ie Index = -nnnnnn) ------ ---1 ---- --------- 110NNNNNN ++PTRB[Index] PTRB + Index*Scale PTRB += Index*Scale (ie Index = +NNNNNN) ------ ---1 ---- --------- 110nnnnnn --PTRB[Index] PTRB - Index*Scale PTRB -= Index*Scale (ie Index = -nnnnnn) -------------------------------------------------------------------------------------------------------------------------------
P2_Instructions.spinEdit: err. That would obviously be a question for the source field only.
000011 ZCR 0 CCCC DDDDDDDDD SSSSSSSSS COGINIT D,S 000011 ZCR 1 CCCC DDDDDDDDD 000000010 COGINIT D
What is the second version for?
Are you looking at the latest info or where are you seeing the second coginit?
It is in the list at the end of the GDoc version. This looks like it was a verbatim copy from an earlier post by Chip in this thread. But it's not mentioned in any of the details sections.
(note: This is only partially a clarification question. I'm also just curious about the internal workings of that mechanism.)
Where is that list (the original post)?
From the info I summarised into an Excel Spreadsheet, all Reads (Byte/Word/Long) take an extra 2 clocks (ie 3..10 clocks). The cached versions vary depending upon whether they are in the cache or not. If they are in cache then it is a single cycle, otherwise there appears to be 3..10 clocks. Therefore, I presume there is some setup (2 clocks) required when interfacing the reads to the hub.
It was the preliminary features PDF that was posted, I don't have a link, just the PDF.