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Propeller II Experimenters PCB requirement's - Page 2 — Parallax Forums

Propeller II Experimenters PCB requirement's

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Comments

  • HShankoHShanko Posts: 402
    edited 2011-06-28 11:28
    Re: Prop2_Pins.bmp image, is there a reason to have a blue background with white features?

    Wastes a lot of ink just to get what 'should be' a Black ink on white paper image. And that would be more legible, imho.
  • LeonLeon Posts: 7,620
    edited 2011-06-28 12:55
    I worked off the screen when I updated my spreadsheet. It was difficult to read, though, and the text orientation didn't help.
  • Roy ElthamRoy Eltham Posts: 3,000
    edited 2011-06-28 13:21
    I brought the image into Paint.NET and did a little processing on it to create a black on white image and a while on black image. Here you go:
    Prop2_Pins.jpg

    Prop2_Pins_b.jpg
    750 x 734 - 92K
    750 x 734 - 92K
  • LeonLeon Posts: 7,620
    edited 2011-06-28 13:32
    I've just finished allocating the pins to my PCB part:

    http://www.leonheller.com/Propeller/Propeller%20II.pdf

    I did it on the spreadsheet and pasted the data into the Part Editor. It was much easier than entering them individually, I always end up with duplicates and it can take a long time to sort them out, although the software tells me where the errors are.
  • HShankoHShanko Posts: 402
    edited 2011-06-28 13:43
    @ Roy,

    Now that is beautiful. Thank you. White on almost any other color isn't as useful to me.

    Printed beautifully. I've tried to print white on color, but the ink seems to 'run' and narrow the white text making them nearly unreadable. Looks OK on screen, s***ty when printed.
  • jeff-ojeff-o Posts: 181
    edited 2011-06-28 21:10
    Tubular wrote: »
    Given the great analog capabilities we're going to be getting - ground planes and power circuitry will need very special attention.

    Very much agreed. Read everything you can about proper ground plane and power plane design. Not only for the analog stuff, but for high frequency digital as well.
  • LeonLeon Posts: 7,620
    edited 2011-06-29 02:55
    I'd just use a four-layer board. It costs more, but makes things much simpler.
  • SapiehaSapieha Posts: 2,964
    edited 2011-06-29 03:44
    Hi Leon.

    My goal on Experimenters Board are 2-layers.
    I know it will not be simple to squeeze all traces needed - BUT at last I will try.

    BUT it is still to much info that needs (And that we not have) for that Board to be made!

    Leon wrote: »
    I'd just use a four-layer board. It costs more, but makes things much simpler.
  • LeonLeon Posts: 7,620
    edited 2011-06-29 05:24
    I was thinking of the board operating properly at the increased clock speed, and ensuring good grounding, supply decoupling, and power distribution.
  • jeff-ojeff-o Posts: 181
    edited 2011-06-29 06:41
    Leon wrote: »
    I was thinking of the board operating properly at the increased clock speed, and ensuring good grounding, supply decoupling, and power distribution.

    Exactly. An internal ground and power layer will actually work together as a big, flat capacitor; further enhancing the decoupling capability of the PCB. A two layer board would certainly be cheaper, and perhaps you're looking forward to the challenge of squeezing everything onto those two layers. But it's poor design practice. Performance may suffer. People will be banging their heads on their workbenches trying to chase bugs from their creations. The Propeller 2 will be one beast of a microcontroller; don't hobble it by stuffing it onto a second-rate PCB.
  • prof_brainoprof_braino Posts: 4,313
    edited 2011-06-29 07:16
    $0.02 Input from a non-hardware guy:

    I like posts 4, 5, 21.

    I would hesitate on post 9, as this states components on the BACK of the board is unusual, and the fewest new variables are least likelt to cause new problems.... BUT SMT on the back is an excellent idea once the hardware requirements are fully developed. What about daughter board/expansion connectors on the back?

    To me it is important to have connectors for all the lines brought to headers so I can connect to breadboard and daughter board. I would advise against a hardware soldering prototype area on the board itself, in favor of easy connections to breadboard as this could also connect directly to daughterboard.

    I like the single line headers on schartboard and Gadget gangster USB. Except I would want male headers, as old disk drive cables can be used to run signals to the breadboard. Would there be a simple configuration where we could re-use an old IDE Hard disk cable (etc) to connect to the breadboard? I would think a single line 40 pin male header would be easy to connect to a breadboard with 'half' an old IDE cable. I have lots of surplus cables. I could easily live with (maximum) 4 IDE cables (half the lines used on each), plus additional lines as needed. I also like male header, as these can also be wire wrapped.

    Leon's configuration from post 35, looks handy to have many groups of several pins. But I would ask for a single line of pins for ease of bringing singals to a breadboard, as applicable.

    Also, I would not mind the extra cost of a multi-layer board, if easy to reconfigure for experiments. I would only need one, and use other solutions as required by specific configurations.
  • LeonLeon Posts: 7,620
    edited 2011-06-29 07:23
    I created the part like that to make schematics easy to read and design, that technique is often used for complex devices. How the I/Os are organised in a physical sense depends on the application.

    I can't see anyone wanting all the I/Os brought out on this type of board, and I never use solderless breadboards, so I'd just provide a prototyping area.
  • HShankoHShanko Posts: 402
    edited 2011-06-29 13:37
    @ anyone, Ar one time I think I had this detail correct, but cannot find it today. On the recent Prop 2 pinouts (above) is the Vdd - 3.3v and the VPn - 1.8v?

    For layout purposes, should the GND and GPn be connected together? Could this 'together' be connected under/below the chip and inside the i/o pads? Or some other scheme?

    And, it appears the crystal should be close to the pin 1, 128 corner of the Prop.
  • LeonLeon Posts: 7,620
    edited 2011-06-29 13:48
    Vdd is the core supply, 1.8V. VPn is the I/O supply voltage, and can be 1.8V - 3.3V. I've forgotten what GPn is for.

    The crystal should be quite close to the pin 1 corner. It's connected to pins 126 and 127.
  • DaveJensonDaveJenson Posts: 375
    edited 2011-06-29 15:56
    GPn is Ground for the I/O pins.
  • HShankoHShanko Posts: 402
    edited 2011-06-29 17:49
    Thanks all. OK, makes sense now. Each 8 I/Os has a GPn and VPn. I printed out the drawing, marked off each 8 I/Os with a pen to visually observe it and find a GPn/VPn around the middle of each 'byte'.

    Don't have a feeling for whether the core or I/Os draw more power. Seems there is a lot of logic and Resistors for the analog stuff in the I/Os, from previous discussions. Lot more to learn about for the Prop 2.
  • BigFootBigFoot Posts: 259
    edited 2011-06-29 17:55
    I think the Pins are on a .400 mm spacing, better find a good stereo microscope :)........
  • AleAle Posts: 2,363
    edited 2011-06-29 23:41
    Leon: Please bring all IOs to the headers, don't cripple it :), you never know if a board will be a platform :). Two rows on each side, 25 pins each should work well :). I hope they would release some info in how the SDRAM has to be connected :).
  • LeonLeon Posts: 7,620
    edited 2011-06-30 00:02
    I was thinking of something simple, initially, to try the chip out. I think I'll include an SDRAM, as that is an important new feature. It'll mop up a lot of those I/O pins. I'll add the ISSI IS42S16100E to my schematic, to see what it looks like. It's a 3.3V 16Mb device in TSOP-50, and is quite cheap at under $3. The updated schematic is here:

    http://www.leonheller.com/Propeller/Propeller%20II.pdf

    A more complex board with all the I/Os brought out could come later.
  • SapiehaSapieha Posts: 2,964
    edited 2011-07-01 03:43
    Hi Leon.

    I don't think that is good idea Before we know all info that needs for connecting SDRAM to Propeller II.

    In first stage needs PCB with all I/O pins out to connectors for all possible experiments.

    That is my opinion - I know others maybe have others ideas - BUT as Bill said --- We need learn go before we RUN it fully out.



    Leon wrote: »
    I was thinking of something simple, initially, to try the chip out. I think I'll include an SDRAM, as that is an important new feature. It'll mop up a lot of those I/O pins. I'll add the ISSI IS42S16100E to my schematic, to see what it looks like. It's a 3.3V 16Mb device in TSOP-50, and is quite cheap at under $3. The updated schematic is here:

    http://www.leonheller.com/Propeller/Propeller%20II.pdf

    A more complex board with all the I/Os brought out could come later.
  • LeonLeon Posts: 7,620
    edited 2011-07-01 04:22
    I haven't connected the SDRAM to anything. Anyway, if the Propeller 2 has a properly designed SDRAM interface it should just involve connecting the pins.

    I don't see why my board needs to have all the pins brought out. I just want something I can design quickly that I can use for initial testing and to get familiar with the device.
  • SapiehaSapieha Posts: 2,964
    edited 2011-07-01 05:00
    Hi Leon.

    My one have all pins out to header PIN's -- BUT as I said --- I build experimenters PCB -- to have all possible configurations

    Leon wrote: »
    I haven't connected the SDRAM to anything. Anyway, if the Propeller 2 has a properly designed SDRAM interface it should just involve connecting the pins.

    I don't see why my board needs to have all the pins brought out. I just want something I can design quickly that I can use for initial testing and to get familiar with the device.


    Ps. And I already can say --- 2 sided
  • LeonLeon Posts: 7,620
    edited 2011-07-01 05:03
    Mine will be four-layer. :) It's essential for SDRAM to work properly.
  • Martin HodgeMartin Hodge Posts: 1,246
    edited 2011-07-01 08:32
    Leon wrote: »
    It's essential for SDRAM to work properly.

    Interesting. Please explain why. I'm currently teaching myself to layout 4 layer boards.
  • LeonLeon Posts: 7,620
    edited 2011-07-01 08:43
    Large fast transients are developed with DRAM, look at a typical data sheet. Good ground and power planes, and decoupling, are essential, Micron actually recommends six layers:

    http://download.micron.com/pdf/technotes/DDR/tn4614.pdf
  • jazzedjazzed Posts: 11,803
    edited 2011-07-01 09:19
    Effective SDR SDRAM power and ground can be made with a 2 layer board. A 4 layer board would be better though.
  • LeonLeon Posts: 7,620
    edited 2011-07-01 09:21
    It isn't recommended by the SDRAM makers, though, and I doubt if any professional systems use two layers. I was one of the first users of the (then) new 1 Mbit DRAMs over 30 years ago with the Inmos transputer, and I didn't even consider using a two-layer board for those.
  • SapiehaSapieha Posts: 2,964
    edited 2011-07-01 10:37
    Hi Leon.

    Good document BUT it is to DDR's - Little different ones as SDRAM's on Propeller II

    It is one of my reason to not to build first Experimenter's PCB with SDRAM.
    As we dont know how them need be connected to Propeller II (Chip still not give any document to That) what signals are already on Propeller to support them and what signals we need generate in software. It is not possible to route reliable Propeller II PCB with SDRAM.



    Leon wrote: »
    Large fast transients are developed with DRAM, look at a typical data sheet. Good ground and power planes, and decoupling, are essential, Micron actually recommends six layers:

    http://download.micron.com/pdf/technotes/DDR/tn4614.pdf
  • LeonLeon Posts: 7,620
    edited 2011-07-01 10:40
    That document covers SDRAMs. All SDRAMs have basically the same technology and layout requirements.

    As I said previously, I just added the SDRAM to my schematic; it isn't connected to anything. I haven't even entered the pin numbers yet. People can see what signals are involved, though.
  • Martin HodgeMartin Hodge Posts: 1,246
    edited 2011-07-01 10:44
    Great link, Leon. Thanks!
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