You guys might have noticed how adding all these new instructions was introducing many caveats into the op-code mapping. It had become a big Swiss cheese. A lot of waste was occurring, too because of WR bits (R) that never practically changed, effectively cutting the number of possible instructions in half. There needs to be individual control of Z and C writing, but only a few cases of controlling D writing offered any value, like SUB versus CMP.
I'm combing through the op-codes now, grouping them by D-writing and flag-affecting. It's freed up tons of instruction space we can now have D,S instructions wherever they're beneficial. I'll post the list a little later today when it's more final.
Ah ok, so the structure is a 128:1 mux and then a local edge detector ?
This would have a leading edge blanking scheme, to avoid false-triggering when activated on a pin already hi ?
That's right.
By the way, I added the timeout via WC, just like WAITPEQ/WAITPNE.
How about if the first time you execute one of these edge detection instructions it always fails to detect an edge no matter what the state of the pin but it remembers what pin is being monitored so it can constantly sample it until the instruction comes around again at which time you return the real result. So, if the pin in the instruction matches the one that is being remembered then you return a real value. If not, you change the pin being remembered and start monitoring that new pin until encountering another instruction checking the same pin. I guess that's a bit convoluted though.
Interesting idea :
Then the edge detector becomes a mini cell (one per COG) that always operates, but discards any history if Index changes.
That would allow a sticky/not-sticky option however starting it could get tricky ?
One pin value would need to be illegal/reset value, and to set the pin index, you would need to execute the opcode.
[ with 3 choices already, Rise, Fall, Change, is there a free 4th value, that can be used to set the pin index, but not wait ? ]
That would allow SW to prime the detector, then do other stuff then check /wait when it was ready.
A loop tail case that took longer, would still proceed with some jitter, (but no missing edges) and as long as the next loop was shorter, re-sync would resume.
If someone used in this in 2 threads, I think it proceeds on an interleave-stall basis ?
I'm doing a lot of work in P1 using the global clock, and keeping track of individual threads' timings relative to that. Very frequently I need to know whether or not the global counter is ahead or behind a target value, and I do that with a subtract. Trouble always is what to do about roll-overs. So the answer is to do a subtract, and examine the most significant bit (31) of the result, because just looking at the subtract's borrow will not work when rollovers are present. A left shift puts bit31 into the carry, and this works great, but takes more instructions than is desired for fast operations.
For the P2, could you invent a single cycle instruction that does a subtract, and copies bit31 into the carry ? It will reduce 3 instructions down to 1 for many locations in my code.
For the P2, could you invent a single cycle instruction that does a subtract, and copies bit31 into the carry ? It will reduce 3 instructions down to 1 for many locations in my code.[\QUOTE]
'Already did that, as it turns out. I saw the same need. It's called CMPCNT. I think it copies !bit31 to C, so that C is set if you are past the goal.
I'd posted this question on another thread, but since it's important to me to know, I'll repeat it here:
On the subject of QUAD-related instructions operation, despite the last documents doesn't describe it that way, could you confirm or deny, if a SETQUAD or SETQUAZ instruction execution, inherently implies a CACHEX-like operation too?
Yanomani
P.S. Answered by Chip, at the original thread.
"No, only CACHEX causes the cache to be invalidated."
Event-driven is certainly the ideal. I suppose its zenith might be an automated system which can launch a cog to process an event.
"Even driven" seems to be quite a woolly term. So what I meant by it is a bit different. What you have described there sounds like traditional interrupt handling except instead of jumping to an interrupt routine a whole new COG is started to handle it.
What I had in mind my "event driven" is a bit more fine grained. A single program might have many things it needs to wait for at different stages of it's processing. A UART for example needs to wait on:
a) Arrival of a character from the user program to be transmitted.
b) A timer so that it can bit-bang the TX at the right time.
c) An input pin so it can respond to incoming start bits.
d) Another timer so it can clock in the Rx bits on time.
e) Perhaps other signals for flow control.
Here we have code halting exection and waiting for the next event, when the event arrives it ressumes execution immediately. No context saving and jumping to an interrupt routine, no loading of a COG, it's just ready to run.
This kind of event driven processing can be done by having many processors each of which can wait on anything when ever it likes without blocking others. Or it can be be done with hardware scheduled threads.
"Even driven" seems to be quite a woolly term. So what I meant by it is a bit different. What you have described there sounds like traditional interrupt handling except instead of jumping to an interrupt routine a whole new COG is started to handle it.
What I had in mind my "event driven" is a bit more fine grained. A single program might have many things it needs to wait for at different stages of it's processing. A UART for example needs to wait on:
a) Arrival of a character from the user program to be transmitted.
b) A timer so that it can bit-bang the TX at the right time.
c) An input pin so it can respond to incoming start bits.
d) Another timer so it can clock in the Rx bits on time.
e) Perhaps other signals for flow control.
Here we have code halting exection and waiting for the next event, when the event arrives it ressumes execution immediately. No context saving and jumping to an interrupt routine, no loading of a COG, it's just ready to run.
This kind of event driven processing can be done by having many processors each of which can wait on anything when ever it likes without blocking others. Or it can be be done with hardware scheduled threads.
When you think about it, though, these are merely different ways to get at the same thing. What I describe is not an "interrupt" in the traditional sense, since nothing in truth is being interrupted/blocked. It too uses multiple processors to handle events but has the potential advantage of not burning a processor (power) until the event actually occurs; ie, no software churning doing essentially nothing in the meantime. As for your UART example, bits would best be handled at the hardware level - though I would argue for a generalized SerDes implementation. Characters, or multiple characters, if there is hardware buffering, would be processed in software as "events." Hardware scheduled threads or hardware managed cogs to process events - different ways to get the same end result, each with its own advantages and disadvantages.
The UART is better done in hardware, it was only an example of what I mean by "event driven programming". The same style can be used for many other things. The idea is a code goes around it can have many points where it has to wait for some condition to become true, an event.
Now interrupts are a way to respond to events but they do have the problem that whatever is running is stopped whilst the interrupt handler run. They can also suffer form latency issues as you have to save processor context prior to executing the handler.
On a single processor machine an RTOS is what is used to get processes to wait on events, and interrupts are used to kick the RTOS around. Here we have all the problems of interrupts plus the latency and overheads of an OS and it thread switching etc.
You solution, starting a COG to handle an even, can no doubt work but how do we get around the huge latency of loading a COG and starting it?
...the potential advantage of not burning a processor (power) until the event actually occurs; ie, no software churning doing essentially nothing in the meantime.
Good point. An ideal implementation of events would have the instruction waiting for an event halt until the event occurs. Thus consuming a lot less power. Isn't this what happens with WAITPxx, WAITVID etc. Not sure how it works with multi-threading on the Prop II.
You solution, starting a COG to handle an even, can no doubt work but how do we get around the huge latency of loading a COG and starting it?
What is it now for COGINIT, 7-22 clocks? Perhaps something can be done, in hardware, to speed this up. Now is that really huge? I guess it depends on what you're doing.
Good point. An ideal implementation of events would have the instruction waiting for an event halt until the event occurs. Thus consuming a lot less power. Isn't this what happens with WAITPxx, WAITVID etc. Not sure how it works with multi-threading on the Prop II.
Are those instructions the eq. to a dormant cog, in terms of power consumption? As for P2 and threads, I'm not sure either. I suspect, though, that power will be squandered to some degree.
It should take something like 500*8/4 = 1000 cycles, shouldn't it?
I'm guessing this is about the correct number, most of it chewed up by getting code in the cog, right? So, what I propose would have to be done some way outside the current, normal method for launching cogs. I had assumed this is doable somehow with hardware mods. Perhaps not, though.
For instance, by launching the cog with a pointer to PASM code (located in a memory dedicated to this) rather than the usual copying etc. Then, launch time should in the dozens of cycles max - ie, apprx. what COGINIT is now. That was the idea anyway.
I've been busy for the last few days reorganizing the op-code mapping and I think I've got it about done. In the new scheme, instructions' result-writing is fixed. For the cases where it was useful to not write the result (SUB NR = CMP), there are now dedicated non-result-writing instructions. Z and C writing is still controllable, of course, since that is mission critical.
By getting rid of the R bit, the instruction set was able to expand, so that things like unary operations can have separate source and destination registers. This new instruction coding is much simpler and more regular than before. It will make assemblers and compilers easier to write. Also, a lot of configuration operations take fewer instructions now, since both D and S can convey immediate or register data. For example: SETSERA D,S (config,baud). It now takes 4 instructions to configure the texture mapper, where it used to take 8.
Roy Eltham and I have been talking about what can be done to improve the texture mapper and he suggested quite a few byte/pixel transforms and new blending methods, such as additive and multiplicative (both 1x and 2x). All these pixel blends will now be able to be done directly, without engaging the texture mapper, through simple instructions.
Propeller II Revised Op-Codes (16 October 2013)
ZCDS (for D column: W=write, M=modify, R=read, L=read/immediate)
---------------------------------------------------------------------------------------------------------------------------------------------------------------
ZCWS 0000000 ZC I CCCC DDDDDDDDD SSSSSSSSS RDBYTE D,S/PTRx (waits for hub)
ZCWS 0000001 ZC I CCCC DDDDDDDDD SSSSSSSSS RDBYTEC D,S/PTRx (waits for hub if cache miss)
ZCWS 0000010 ZC I CCCC DDDDDDDDD SSSSSSSSS RDWORD D,S/PTRx (waits for hub)
ZCWS 0000011 ZC I CCCC DDDDDDDDD SSSSSSSSS RDWORDC D,S/PTRx (waits for hub if cache miss)
ZCWS 0000100 ZC I CCCC DDDDDDDDD SSSSSSSSS RDLONG D,S/PTRx (waits for hub)
ZCWS 0000101 ZC I CCCC DDDDDDDDD SSSSSSSSS RDLONGC D,S/PTRx (waits for hub if cache miss)
ZCWS 0000110 ZC I CCCC DDDDDDDDD SSSSSSSSS RDAUX D,S/#/SPx
ZCWS 0000111 ZC I CCCC DDDDDDDDD SSSSSSSSS RDAUXR D,S/#/SPx
ZCMS 0001000 ZC I CCCC DDDDDDDDD SSSSSSSSS ISOB D,S
ZCMS 0001001 ZC I CCCC DDDDDDDDD SSSSSSSSS NOTB D,S
ZCMS 0001010 ZC I CCCC DDDDDDDDD SSSSSSSSS CLRB D,S
ZCMS 0001011 ZC I CCCC DDDDDDDDD SSSSSSSSS SETB D,S
ZCMS 0001100 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBC D,S
ZCMS 0001101 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBNC D,S
ZCMS 0001110 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBZ D,S
ZCMS 0001111 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBNZ D,S
ZCMS 0010000 ZC I CCCC DDDDDDDDD SSSSSSSSS ANDN D,S
ZCMS 0010001 ZC I CCCC DDDDDDDDD SSSSSSSSS AND D,S
ZCMS 0010010 ZC I CCCC DDDDDDDDD SSSSSSSSS OR D,S
ZCMS 0010011 ZC I CCCC DDDDDDDDD SSSSSSSSS XOR D,S
ZCMS 0010100 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXC D,S
ZCMS 0010101 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXNC D,S
ZCMS 0010110 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXZ D,S
ZCMS 0010111 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXNZ D,S
ZCMS 0011000 ZC I CCCC DDDDDDDDD SSSSSSSSS ROR D,S
ZCMS 0011001 ZC I CCCC DDDDDDDDD SSSSSSSSS ROL D,S
ZCMS 0011010 ZC I CCCC DDDDDDDDD SSSSSSSSS SHR D,S
ZCMS 0011011 ZC I CCCC DDDDDDDDD SSSSSSSSS SHL D,S
ZCMS 0011100 ZC I CCCC DDDDDDDDD SSSSSSSSS RCR D,S
ZCMS 0011101 ZC I CCCC DDDDDDDDD SSSSSSSSS RCL D,S
ZCMS 0011110 ZC I CCCC DDDDDDDDD SSSSSSSSS SAR D,S
ZCMS 0011111 ZC I CCCC DDDDDDDDD SSSSSSSSS REV D,S
ZCWS 0100000 ZC I CCCC DDDDDDDDD SSSSSSSSS MOV D,S
ZCWS 0100001 ZC I CCCC DDDDDDDDD SSSSSSSSS NOT D,S
ZCWS 0100010 ZC I CCCC DDDDDDDDD SSSSSSSSS ABS D,S
ZCWS 0100011 ZC I CCCC DDDDDDDDD SSSSSSSSS NEG D,S
ZCWS 0100100 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGC D,S
ZCWS 0100101 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGNC D,S
ZCWS 0100110 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGZ D,S
ZCWS 0100111 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGNZ D,S
ZCMS 0101000 ZC I CCCC DDDDDDDDD SSSSSSSSS ADD D,S
ZCMS 0101001 ZC I CCCC DDDDDDDDD SSSSSSSSS SUB D,S
ZCMS 0101010 ZC I CCCC DDDDDDDDD SSSSSSSSS ADDX D,S
ZCMS 0101011 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBX D,S
ZCMS 0101100 ZC I CCCC DDDDDDDDD SSSSSSSSS ADDS D,S
ZCMS 0101101 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBS D,S
ZCMS 0101110 ZC I CCCC DDDDDDDDD SSSSSSSSS ADDSX D,S
ZCMS 0101111 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBSX D,S
ZCMS 0110000 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMC D,S
ZCMS 0110001 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMNC D,S
ZCMS 0110010 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMZ D,S
ZCMS 0110011 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMNZ D,S
ZCMS 0110100 ZC I CCCC DDDDDDDDD SSSSSSSSS MINS D,S
ZCMS 0110101 ZC I CCCC DDDDDDDDD SSSSSSSSS MAXS D,S
ZCMS 0110110 ZC I CCCC DDDDDDDDD SSSSSSSSS MIN D,S
ZCMS 0110111 ZC I CCCC DDDDDDDDD SSSSSSSSS MAX D,S
ZCMS 0111000 ZC I CCCC DDDDDDDDD SSSSSSSSS ADDABS D,S
ZCMS 0111001 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBABS D,S
ZCMS 0111010 ZC I CCCC DDDDDDDDD SSSSSSSSS INCMOD D,S
ZCMS 0111011 ZC I CCCC DDDDDDDDD SSSSSSSSS DECMOD D,S
ZCMS 0111100 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPSUB D,S
ZCMS 0111101 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBR D,S
ZCMS 0111110 ZC I CCCC DDDDDDDDD SSSSSSSSS MUL D,S (waits one clock)
ZCMS 0111111 ZC I CCCC DDDDDDDDD SSSSSSSSS SCL D,S (waits one clock)
ZCWS 1000000 ZC I CCCC DDDDDDDDD SSSSSSSSS DECOD3 D,S
ZCWS 1000001 ZC I CCCC DDDDDDDDD SSSSSSSSS DECOD4 D,S
ZCWS 1000010 ZC I CCCC DDDDDDDDD SSSSSSSSS DECOD5 D,S
Z-WS 1000011 Z0 I CCCC DDDDDDDDD SSSSSSSSS ENCOD D,S
Z-WS 1000011 Z1 I CCCC DDDDDDDDD SSSSSSSSS BLMASK D,S
Z-WS 1000100 Z0 I CCCC DDDDDDDDD SSSSSSSSS ONECNT D,S (waits one clock)
Z-WS 1000100 Z1 I CCCC DDDDDDDDD SSSSSSSSS ZERCNT D,S (waits one clock)
-CWS 1000101 0C I CCCC DDDDDDDDD SSSSSSSSS INCPAT D,S (waits three clocks)
-CWS 1000101 1C I CCCC DDDDDDDDD SSSSSSSSS DECPAT D,S (waits three clocks)
--WS 1000110 00 I CCCC DDDDDDDDD SSSSSSSSS SPLITW D,S
--WS 1000110 01 I CCCC DDDDDDDDD SSSSSSSSS MERGEW D,S
--WS 1000110 10 I CCCC DDDDDDDDD SSSSSSSSS ESWAP4 D,S
--WS 1000110 11 I CCCC DDDDDDDDD SSSSSSSSS ESWAP8 D,S
--WS 1000111 00 I CCCC DDDDDDDDD SSSSSSSSS SEUSSF D,S
--WS 1000111 01 I CCCC DDDDDDDDD SSSSSSSSS SEUSSR D,S
--WS 1000111 10 I CCCC DDDDDDDDD SSSSSSSSS BINGRY D,S
--WS 1000111 11 I CCCC DDDDDDDDD SSSSSSSSS GRYBIN D,S (waits one clock)
--MS 10010nn n0 I CCCC DDDDDDDDD SSSSSSSSS GETNIB D,S,#n
--MS 10010nn n1 I CCCC DDDDDDDDD SSSSSSSSS SETNIB D,S,#n
--MS 1001100 n0 I CCCC DDDDDDDDD SSSSSSSSS GETWORD D,S,#n
--MS 1001100 n1 I CCCC DDDDDDDDD SSSSSSSSS SETWORD D,S,#n
--MS 1001110 00 I CCCC DDDDDDDDD SSSSSSSSS ROLNIB D,S
--MS 1001110 01 I CCCC DDDDDDDDD SSSSSSSSS ROLBYTE D,S
--MS 1001110 10 I CCCC DDDDDDDDD SSSSSSSSS ROLWORD D,S
--MS 1001110 11 I CCCC DDDDDDDDD SSSSSSSSS SWBYTES D,S (switch/copy bytes in D, S = %11_10_01_00 = D same)
--MS 1001111 00 I CCCC DDDDDDDDD SSSSSSSSS PACKRGB D,S (8:8:8 -> 5:5:5 << 16 | D >> 16)
--MS 1001111 01 I CCCC DDDDDDDDD SSSSSSSSS SETS D,S
--MS 1001111 10 I CCCC DDDDDDDDD SSSSSSSSS SETD D,S
--MS 1001111 11 I CCCC DDDDDDDDD SSSSSSSSS SETI D,S
--MS 101000n n0 I CCCC DDDDDDDDD SSSSSSSSS GETBYTE D,S,#n
--MS 101000n n1 I CCCC DDDDDDDDD SSSSSSSSS SETBYTE D,S,#n
-CMS 1010010 0C I CCCC DDDDDDDDD SSSSSSSSS COGNEW D,S (waits for hub)
-CMS 1010010 1C I CCCC DDDDDDDDD SSSSSSSSS WAITCNT D,S (waits for cnt)
--MS 1010011 00 I CCCC DDDDDDDDD SSSSSSSSS MIXPIX D,S (waits two clocks)
--MS 1010011 01 I CCCC DDDDDDDDD SSSSSSSSS MULPIX D,S (waits two clocks)
--MS 1010011 10 I CCCC DDDDDDDDD SSSSSSSSS MULPIX2 D,S (waits two clocks)
--MS 1010011 11 I CCCC DDDDDDDDD SSSSSSSSS ADDPIX D,S
ZCWS 1010100 ZC I CCCC DDDDDDDDD SSSSSSSSS JMPRET D,S (set D to INA for JMP/RET)
ZCWS 1010101 ZC I CCCC DDDDDDDDD SSSSSSSSS JMPRETD D,S (set D to INA for JMP/RET)
--MS 1010110 00 I CCCC DDDDDDDDD SSSSSSSSS IJZ D,S
--MS 1010110 01 I CCCC DDDDDDDDD SSSSSSSSS IJZD D,S
--MS 1010110 10 I CCCC DDDDDDDDD SSSSSSSSS IJNZ D,S
--MS 1010110 11 I CCCC DDDDDDDDD SSSSSSSSS IJNZD D,S
--MS 1010111 00 I CCCC DDDDDDDDD SSSSSSSSS DJZ D,S
--MS 1010111 01 I CCCC DDDDDDDDD SSSSSSSSS DJZD D,S
--MS 1010111 10 I CCCC DDDDDDDDD SSSSSSSSS DJNZ D,S
--MS 1010111 11 I CCCC DDDDDDDDD SSSSSSSSS DJNZD D,S
ZCRS 1011000 ZC I CCCC DDDDDDDDD SSSSSSSSS TESTB D,S
ZCRS 1011001 ZC I CCCC DDDDDDDDD SSSSSSSSS TESTN D,S
ZCRS 1011010 ZC I CCCC DDDDDDDDD SSSSSSSSS TEST D,S
ZCRS 1011011 ZC I CCCC DDDDDDDDD SSSSSSSSS CMP D,S
ZCRS 1011100 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPX D,S
ZCRS 1011101 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPS D,S
ZCRS 1011110 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPSX D,S
ZCRS 1011111 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPR D,S
--RS 11000nn n0 I CCCC DDDDDDDDD SSSSSSSSS COGINIT D,S,#0..7 (waits for hub) (SETNIB :coginit,cog,#6)
---S 11000nn n1 I CCCC nnnnnnnnn SSSSSSSSS WAITVID #n,S (waits for vid if single-task, loops if multi-task)
--RS 1100011 11 I CCCC DDDDDDDDD SSSSSSSSS WAITVID D,S (waits for vid if single-task, loops if multi-task)
-CRS 110010n nC I CCCC DDDDDDDDD SSSSSSSSS WAITPEQ D,S,#port (waits for pins, +cnt32 if wc) (4)
-CRS 110011n nC I CCCC DDDDDDDDD SSSSSSSSS WAITPNE D,S,#port (waits for pins, +cnt32 if wc) (4)
--LS 1101000 0L I CCCC DDDDDDDDD SSSSSSSSS WRBYTE D,S/PTR (waits for hub)
--LS 1101000 1L I CCCC DDDDDDDDD SSSSSSSSS WRWORD D,S/PTR (waits for hub)
--LS 1101001 0L I CCCC DDDDDDDDD SSSSSSSSS WRLONG D,S/PTR (waits for hub)
--LS 1101001 1L I CCCC DDDDDDDDD SSSSSSSSS FRAC32 D,S
--LS 1101010 0L I CCCC DDDDDDDDD SSSSSSSSS WRAUX D,S/#0..FF/SPx
--LS 1101010 1L I CCCC DDDDDDDDD SSSSSSSSS WRAUXR D,S/#0..FF/SPx
--LS 1101011 0L I CCCC DDDDDDDDD SSSSSSSSS SETACA D,S
--LS 1101011 1L I CCCC DDDDDDDDD SSSSSSSSS SETACB D,S
--LS 1101100 0L I CCCC DDDDDDDDD SSSSSSSSS MACA D,S
--LS 1101100 1L I CCCC DDDDDDDDD SSSSSSSSS MACB D,S
--LS 1101101 0L I CCCC DDDDDDDDD SSSSSSSSS DIV32 D,S
--LS 1101101 1L I CCCC DDDDDDDDD SSSSSSSSS DIV32U D,S
--LS 1101110 0L I CCCC DDDDDDDDD SSSSSSSSS DIV64 D,S
--LS 1101110 1L I CCCC DDDDDDDDD SSSSSSSSS DIV64U D,S
--LS 1101111 0L I CCCC DDDDDDDDD SSSSSSSSS MUL32 D,S
--LS 1101111 1L I CCCC DDDDDDDDD SSSSSSSSS MUL32U D,S
--LS 1110000 0L I CCCC DDDDDDDDD SSSSSSSSS SQRT64 D,S
--LS 1110000 1L I CCCC DDDDDDDDD SSSSSSSSS QSINCOS D,S
--LS 1110001 0L I CCCC DDDDDDDDD SSSSSSSSS QARCTAN D,S
--LS 1110001 1L I CCCC DDDDDDDDD SSSSSSSSS QROTATE D,S
--LS 1110010 0L I CCCC DDDDDDDDD SSSSSSSSS SETSERA D,S (config,baud)
--LS 1110010 1L I CCCC DDDDDDDDD SSSSSSSSS SETSERB D,S (config,baud)
--LS 1110011 0L I CCCC DDDDDDDDD SSSSSSSSS SETCTRS D,S
--LS 1110011 1L I CCCC DDDDDDDDD SSSSSSSSS SETWAVS D,S
--LS 1110100 0L I CCCC DDDDDDDDD SSSSSSSSS SETFRQS D,S
--LS 1110100 1L I CCCC DDDDDDDDD SSSSSSSSS SETPHSS D,S
--LS 1110101 0L I CCCC DDDDDDDDD SSSSSSSSS ADDPHSS D,S
--LS 1110101 1L I CCCC DDDDDDDDD SSSSSSSSS SUBPHSS D,S
--LS 1110110 0L I CCCC DDDDDDDDD SSSSSSSSS SETPIX0 D,S (config,Z)
--LS 1110110 1L I CCCC DDDDDDDDD SSSSSSSSS SETPIX1 D,S (U, V)
--LS 1110111 0L I CCCC DDDDDDDDD SSSSSSSSS SETPIX2 D,S (A, R)
--LS 1110111 1L I CCCC DDDDDDDDD SSSSSSSSS SETPIX3 D,S (G, B)
--LS 1111000 0L I CCCC DDDDDDDDD SSSSSSSSS CFGPINS D,S,#0 (waits for alt)
--LS 1111000 1L I CCCC DDDDDDDDD SSSSSSSSS CFGPINS D,S,#1 (waits for alt)
--LS 1111001 0L I CCCC DDDDDDDDD SSSSSSSSS CFGPINS D,S,#2 (waits for alt)
--LS 1111001 1L I CCCC DDDDDDDDD SSSSSSSSS JMPTASK D,S (mask,address)
--LS 1111010 0L I CCCC DDDDDDDDD SSSSSSSSS JP D,S
--LS 1111010 1L I CCCC DDDDDDDDD SSSSSSSSS JPD D,S
--LS 1111011 0L I CCCC DDDDDDDDD SSSSSSSSS JNP D,S
--LS 1111011 1L I CCCC DDDDDDDDD SSSSSSSSS JNPD D,S
--RS 1111100 00 I CCCC DDDDDDDDD SSSSSSSSS TJZ D,S
--RS 1111100 01 I CCCC DDDDDDDDD SSSSSSSSS TJZD D,S
--RS 1111100 10 I CCCC DDDDDDDDD SSSSSSSSS TJNZ D,S
--RS 1111100 11 I CCCC DDDDDDDDD SSSSSSSSS TJNZD D,S
<gap>
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000000 COGID D (waits for hub)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000001 LOCKNEW D (waits for hub)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000010 GETCNT D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000011 GETCNTX D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000100 GETLFSR D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000101 GETTOPS D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000110 GETACAL D (waits for mac)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000111 GETACAH D (waits for mac)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001000 GETACBL D (waits for mac)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001001 GETACBH D (waits for mac)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001010 GETPTRA D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001011 GETPTRB D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001100 GETSPA D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001101 GETSPB D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001110 GETMULL D (waits for mul if single-task, loops if multi-task)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001111 GETMULH D (waits for mul if single-task, loops if multi-task)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010000 GETDIVQ D (waits for div if single-task, loops if multi-task)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010001 GETDIVR D (waits for div if single-task, loops if multi-task)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010010 GETSQRT D (waits for sqrt if single-task, loops if multi-task)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010011 GETQX D (waits for cordic if single-task, loops if multi-task)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010100 GETQY D (waits for cordic if single-task, loops if multi-task)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010101 GETQZ D (waits for cordic if single-task, loops if multi-task)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010110 SERINA D (waits for rx if single-task, loops if multi-task, releases if wc)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010111 SERINB D (waits for rx if single-task, loops if multi-task, releases if wc)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011000 GETPHSA D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011001 GETPHZA D (clears phsa)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011010 GETCOSA D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011011 GETSINA D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011100 GETPHSB D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011101 GETPHZB D (clears phsb)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011110 GETCOSB D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011111 GETSINB D
ZCM- 1111110 ZC x CCCC DDDDDDDDD x00100000 PUSHZC D
ZCM- 1111110 ZC x CCCC DDDDDDDDD x00100001 POPZC D
ZCM- 1111110 ZC x CCCC DDDDDDDDD x00100010 SUBCNT D (subtracts D from cnt[31:0], then cntl if same thread)
ZCM- 1111110 ZC x CCCC DDDDDDDDD x00100011 GETPIX D (waits two clocks)
--M- 1111110 xx x CCCC DDDDDDDDD x00100100 INCD D (add $200 to D)
--M- 1111110 xx x CCCC DDDDDDDDD x00100101 DECD D (subtract $200 from D)
--M- 1111110 xx x CCCC DDDDDDDDD x00100110 INCDS D (add $201 to D)
--M- 1111110 xx x CCCC DDDDDDDDD x00100111 DECDS D (subtract $201 from D)
--L- 1111110 xx L CCCC DDDDDDDDD x00101000 CLKSET D (waits for hub)
-CL- 1111110 xC L CCCC DDDDDDDDD x00101001 COGIDX D (waits for hub)
--L- 1111110 xx L CCCC DDDDDDDDD x00101010 COGSTOP D (waits for hub)
--L- 1111110 xx L CCCC DDDDDDDDD x00101011 LOCKRET D (waits for hub)
-CL- 1111110 xC L CCCC DDDDDDDDD x00101100 LOCKSET D (waits for hub)
-CL- 1111110 xC L CCCC DDDDDDDDD x00101101 LOCKCLR D (waits for hub)
--L- 1111110 xx L CCCC DDDDDDDDD x00101110 WRQUAD D/PTR (waits for hub)
--L- 1111110 x0 L CCCC DDDDDDDDD x00101111 RDQUAD D/PTR (waits for hub)
--L- 1111110 x1 L CCCC DDDDDDDDD x00101111 RDQUADC D/PTR (waits for hub if cache miss)
ZCL- 1111110 ZC L CCCC DDDDDDDDD x00110000 GETP D (pin into !z/c via wz/wc)
ZCL- 1111110 ZC L CCCC DDDDDDDDD x00110001 GETNP D (pin into z/!c via wz/wc)
-CL- 1111110 xC L CCCC DDDDDDDDD x00110010 SEROUTA D (waits for tx if single-task, loops if multi-task, releases if wc)
-CL- 1111110 xC L CCCC DDDDDDDDD x00110011 SEROUTB D (waits for tx if single-task, loops if multi-task, releases if wc)
-CL- 1111110 xC L CCCC DDDDDDDDD x00110100 CMPCNT D (subtracts S from cnt[31:0], then cntl if same thread)
-CL- 1111110 xC L CCCC DDDDDDDDD x00110101 WAITCHG D (waits for edge)
-CL- 1111110 xC L CCCC DDDDDDDDD x00110110 WAITPOS D (waits for edge)
-CL- 1111110 xC L CCCC DDDDDDDDD x00110111 WAITNEG D (waits for edge)
ZCL- 1111110 ZC L CCCC DDDDDDDDD x00111000 SETZC D (D[1:0] into z/c via wz/wc)
--L- 1111110 xx L CCCC DDDDDDDDD x00111001 SETTASK D
--L- 1111110 xx L CCCC DDDDDDDDD x00111010 SETMAP D
--L- 1111110 xx L CCCC DDDDDDDDD x00111011 SETXCH D
--L- 1111110 xx L CCCC DDDDDDDDD x00111100 SETXFR D
--L- 1111110 xx L CCCC DDDDDDDDD x00111101 SARACA D (waits for mac)
--L- 1111110 xx L CCCC DDDDDDDDD x00111110 SARACB D (waits for mac)
--L- 1111110 xx L CCCC DDDDDDDDD x00111111 SARACS D (waits for mac)
--L- 1111110 xx L CCCC DDDDDDDDD x01iiiiii REPD D,#i (REPD $1FF,#i = infinite repeat)
--L- 1111110 xx L CCCC DDDDDDDDD x10000000 SETSPA D
--L- 1111110 xx L CCCC DDDDDDDDD x10000001 SETSPB D
--L- 1111110 xx L CCCC DDDDDDDDD x10000010 ADDSPA D
--L- 1111110 xx L CCCC DDDDDDDDD x10000011 ADDSPB D
--L- 1111110 xx L CCCC DDDDDDDDD x10000100 SUBSPA D
--L- 1111110 xx L CCCC DDDDDDDDD x10000101 SUBSPB D
--L- 1111110 xx L CCCC DDDDDDDDD x10000110 SETQUAD D
--L- 1111110 xx L CCCC DDDDDDDDD x10000111 SETQUAZ D
--L- 1111110 xx L CCCC DDDDDDDDD x10001000 SETPTRA D
--L- 1111110 xx L CCCC DDDDDDDDD x10001001 SETPTRB D
--L- 1111110 xx L CCCC DDDDDDDDD x10001010 ADDPTRA D
--L- 1111110 xx L CCCC DDDDDDDDD x10001011 ADDPTRB D
--L- 1111110 xx L CCCC DDDDDDDDD x10001100 SUBPTRA D
--L- 1111110 xx L CCCC DDDDDDDDD x10001101 SUBPTRB D
--L- 1111110 xx L CCCC DDDDDDDDD x10001110 PASSCNT D (loops if (cnt[31:0] - D) msb set)
--L- 1111110 xx L CCCC DDDDDDDDD x10001111 NOPX D (waits)
--L- 1111110 xx L CCCC DDDDDDDDD x10010000 CALLA D
--L- 1111110 xx L CCCC DDDDDDDDD x10010001 CALLB D
--L- 1111110 xx L CCCC DDDDDDDDD x10010010 CALLAD D
--L- 1111110 xx L CCCC DDDDDDDDD x10010011 CALLBD D
--L- 1111110 xx L CCCC DDDDDDDDD x10010100 CALLAR D
--L- 1111110 xx L CCCC DDDDDDDDD x10010101 CALLBR D
--L- 1111110 xx L CCCC DDDDDDDDD x10010110 CALLARD D
--L- 1111110 xx L CCCC DDDDDDDDD x10010111 CALLBRD D
--L- 1111110 xx L CCCC DDDDDDDDD x10011000 OFFP D
--L- 1111110 xx L CCCC DDDDDDDDD x10011001 NOTP D
--L- 1111110 xx L CCCC DDDDDDDDD x10011010 CLRP D
--L- 1111110 xx L CCCC DDDDDDDDD x10011011 SETP D
--L- 1111110 xx L CCCC DDDDDDDDD x10011100 SETPC D
--L- 1111110 xx L CCCC DDDDDDDDD x10011101 SETPNC D
--L- 1111110 xx L CCCC DDDDDDDDD x10011110 SETPZ D
--L- 1111110 xx L CCCC DDDDDDDDD x10011111 SETPNZ D
--L- 1111110 xx L CCCC DDDDDDDDD x10100000 DIV64D D
--L- 1111110 xx L CCCC DDDDDDDDD x10100001 SQRT32 D
--L- 1111110 xx L CCCC DDDDDDDDD x10100010 QLOG D
--L- 1111110 xx L CCCC DDDDDDDDD x10100011 QEXP D
--L- 1111110 xx L CCCC DDDDDDDDD x10100100 SETQI D
--L- 1111110 xx L CCCC DDDDDDDDD x10100101 SETQZ D
--L- 1111110 xx L CCCC DDDDDDDDD x10100110 CFGDACS D
--L- 1111110 xx L CCCC DDDDDDDDD x10100111 SETDACS D
--L- 1111110 xx L CCCC DDDDDDDDD x10101000 CFGDAC0 D
--L- 1111110 xx L CCCC DDDDDDDDD x10101001 CFGDAC1 D
--L- 1111110 xx L CCCC DDDDDDDDD x10101010 CFGDAC2 D
--L- 1111110 xx L CCCC DDDDDDDDD x10101011 CFGDAC3 D
--L- 1111110 xx L CCCC DDDDDDDDD x10101100 SETDAC0 D
--L- 1111110 xx L CCCC DDDDDDDDD x10101101 SETDAC1 D
--L- 1111110 xx L CCCC DDDDDDDDD x10101110 SETDAC2 D
--L- 1111110 xx L CCCC DDDDDDDDD x10101111 SETDAC3 D
--L- 1111110 xx L CCCC DDDDDDDDD x10110000 SETCTRA D
--L- 1111110 xx L CCCC DDDDDDDDD x10110001 SETWAVA D
--L- 1111110 xx L CCCC DDDDDDDDD x10110010 SETFRQA D
--L- 1111110 xx L CCCC DDDDDDDDD x10110011 SETPHSA D
--L- 1111110 xx L CCCC DDDDDDDDD x10110100 ADDPHSA D
--L- 1111110 xx L CCCC DDDDDDDDD x10110101 SUBPHSA D
--L- 1111110 xx L CCCC DDDDDDDDD x10110110 SETVID D
--L- 1111110 xx L CCCC DDDDDDDDD x10110111 SETVIDY D
--L- 1111110 xx L CCCC DDDDDDDDD x10111000 SETCTRB D
--L- 1111110 xx L CCCC DDDDDDDDD x10111001 SETWAVB D
--L- 1111110 xx L CCCC DDDDDDDDD x10111010 SETFRQB D
--L- 1111110 xx L CCCC DDDDDDDDD x10111011 SETPHSB D
--L- 1111110 xx L CCCC DDDDDDDDD x10111100 ADDPHSB D
--L- 1111110 xx L CCCC DDDDDDDDD x10111101 SUBPHSB D
--L- 1111110 xx L CCCC DDDDDDDDD x10111110 SETVIDI D
--L- 1111110 xx L CCCC DDDDDDDDD x10111111 SETVIDQ D
--L- 1111110 xx L CCCC DDDDDDDDD x11000000 SETPORA D
--L- 1111110 xx L CCCC DDDDDDDDD x11000001 SETPORB D
--L- 1111110 xx L CCCC DDDDDDDDD x11000010 SETPORC D
--L- 1111110 xx L CCCC DDDDDDDDD x11000011 SETPORD D
<gap>
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100000 RETA
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100001 RETB
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100010 RETAD
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100011 RETBD
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100100 RETAR
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100101 RETBR
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100110 RETARD
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100111 RETBRD
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11101000 TESTSPA
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11101001 TESTSPB
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11101010 POLCTRA (CTRA rollover into !Z/C)
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11101011 POLCTRB (CTRB rollover into !Z/C)
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11101100 POLVID (VID ready into !Z/C)
---- 1111110 xx x CCCC xxxxxxxxx x11101101 CAPCTRA
---- 1111110 xx x CCCC xxxxxxxxx x11101110 CAPCTRB
---- 1111110 xx x CCCC xxxxxxxxx x11101111 CAPCTRS
---- 1111110 xx L CCCC xxxxxxxxx x11110000 CACHEX
---- 1111110 xx L CCCC xxxxxxxxx x11110001 CLRACA
---- 1111110 xx L CCCC xxxxxxxxx x11110010 CLRACB
---- 1111110 xx L CCCC xxxxxxxxx x11110011 CLRACS
---- 1111110 xx x CCCC xxxxxxxxx x11110100 SYNCTRA (waits for ctra if single-task, loops if multi-task))
---- 1111110 xx x CCCC xxxxxxxxx x11110101 SYNCTRB (waits for ctrb if single-task, loops if multi-task))
<gap>
---- 1111111 0n n nnnn nnnnnnnnn nnniiiiii REPS #n,#i
---- 1111111 10 x BBAA DDDDDDDDD SSSSSSSSS SETINDx #D,#S (SETINDA S / SETINDB D / SETINDS D,S)
---- 1111111 11 x 0B0A DDDDDDDDD SSSSSSSSS FIXINDx #D,#S (FIXINDA D,S / FIXINDB D,S / FIXINDS D,S)
x = don't care, use 0
---------------------------------------------------------------------------------------------------------------------------------------------------------------
Now I've got to change the Verilog and the assembler in PNUT to reflect this new map. This will take several days.
I've been busy for the last few days reorganizing the op-code mapping and I think I've got it about done:
Propeller II Revised Op-Codes (16 October 2013)
ZCDS (for D column: W=write, M=modify, R=read, L=read/immediate)
---------------------------------------------------------------------------------------------------------------------------------------------------------------
ZCWS 0000000 ZC I CCCC DDDDDDDDD SSSSSSSSS RDBYTE D,S/PTRx (waits for hub)
ZCWS 0000001 ZC I CCCC DDDDDDDDD SSSSSSSSS RDBYTEC D,S/PTRx (waits for hub if cache miss)
ZCWS 0000010 ZC I CCCC DDDDDDDDD SSSSSSSSS RDWORD D,S/PTRx (waits for hub)
ZCWS 0000011 ZC I CCCC DDDDDDDDD SSSSSSSSS RDWORDC D,S/PTRx (waits for hub if cache miss)
ZCWS 0000100 ZC I CCCC DDDDDDDDD SSSSSSSSS RDLONG D,S/PTRx (waits for hub)
ZCWS 0000101 ZC I CCCC DDDDDDDDD SSSSSSSSS RDLONGC D,S/PTRx (waits for hub if cache miss)
ZCWS 0000110 ZC I CCCC DDDDDDDDD SSSSSSSSS RDAUX D,S/#/SPx
ZCWS 0000111 ZC I CCCC DDDDDDDDD SSSSSSSSS RDAUXR D,S/#/SPx
ZCMS 0001000 ZC I CCCC DDDDDDDDD SSSSSSSSS ISOB D,S
ZCMS 0001001 ZC I CCCC DDDDDDDDD SSSSSSSSS NOTB D,S
ZCMS 0001010 ZC I CCCC DDDDDDDDD SSSSSSSSS CLRB D,S
ZCMS 0001011 ZC I CCCC DDDDDDDDD SSSSSSSSS SETB D,S
ZCMS 0001100 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBC D,S
ZCMS 0001101 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBNC D,S
ZCMS 0001110 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBZ D,S
ZCMS 0001111 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBNZ D,S
ZCMS 0010000 ZC I CCCC DDDDDDDDD SSSSSSSSS ANDN D,S
ZCMS 0010001 ZC I CCCC DDDDDDDDD SSSSSSSSS AND D,S
ZCMS 0010010 ZC I CCCC DDDDDDDDD SSSSSSSSS OR D,S
ZCMS 0010011 ZC I CCCC DDDDDDDDD SSSSSSSSS XOR D,S
ZCMS 0010100 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXC D,S
ZCMS 0010101 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXNC D,S
ZCMS 0010110 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXZ D,S
ZCMS 0010111 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXNZ D,S
ZCMS 0011000 ZC I CCCC DDDDDDDDD SSSSSSSSS ROR D,S
ZCMS 0011001 ZC I CCCC DDDDDDDDD SSSSSSSSS ROL D,S
ZCMS 0011010 ZC I CCCC DDDDDDDDD SSSSSSSSS SHR D,S
ZCMS 0011011 ZC I CCCC DDDDDDDDD SSSSSSSSS SHL D,S
ZCMS 0011100 ZC I CCCC DDDDDDDDD SSSSSSSSS RCR D,S
ZCMS 0011101 ZC I CCCC DDDDDDDDD SSSSSSSSS RCL D,S
ZCMS 0011110 ZC I CCCC DDDDDDDDD SSSSSSSSS SAR D,S
ZCMS 0011111 ZC I CCCC DDDDDDDDD SSSSSSSSS REV D,S
ZCWS 0100000 ZC I CCCC DDDDDDDDD SSSSSSSSS MOV D,S
ZCWS 0100001 ZC I CCCC DDDDDDDDD SSSSSSSSS NOT D,S
ZCWS 0100010 ZC I CCCC DDDDDDDDD SSSSSSSSS ABS D,S
ZCWS 0100011 ZC I CCCC DDDDDDDDD SSSSSSSSS NEG D,S
ZCWS 0100100 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGC D,S
ZCWS 0100101 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGNC D,S
ZCWS 0100110 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGZ D,S
ZCWS 0100111 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGNZ D,S
ZCMS 0101000 ZC I CCCC DDDDDDDDD SSSSSSSSS ADD D,S
ZCMS 0101001 ZC I CCCC DDDDDDDDD SSSSSSSSS SUB D,S
ZCMS 0101010 ZC I CCCC DDDDDDDDD SSSSSSSSS ADDX D,S
ZCMS 0101011 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBX D,S
ZCMS 0101100 ZC I CCCC DDDDDDDDD SSSSSSSSS ADDS D,S
ZCMS 0101101 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBS D,S
ZCMS 0101110 ZC I CCCC DDDDDDDDD SSSSSSSSS ADDSX D,S
ZCMS 0101111 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBSX D,S
ZCMS 0110000 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMC D,S
ZCMS 0110001 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMNC D,S
ZCMS 0110010 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMZ D,S
ZCMS 0110011 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMNZ D,S
ZCMS 0110100 ZC I CCCC DDDDDDDDD SSSSSSSSS MINS D,S
ZCMS 0110101 ZC I CCCC DDDDDDDDD SSSSSSSSS MAXS D,S
ZCMS 0110110 ZC I CCCC DDDDDDDDD SSSSSSSSS MIN D,S
ZCMS 0110111 ZC I CCCC DDDDDDDDD SSSSSSSSS MAX D,S
ZCMS 0111000 ZC I CCCC DDDDDDDDD SSSSSSSSS ADDABS D,S
ZCMS 0111001 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBABS D,S
ZCMS 0111010 ZC I CCCC DDDDDDDDD SSSSSSSSS INCMOD D,S
ZCMS 0111011 ZC I CCCC DDDDDDDDD SSSSSSSSS DECMOD D,S
ZCMS 0111100 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPSUB D,S
ZCMS 0111101 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBR D,S
ZCMS 0111110 ZC I CCCC DDDDDDDDD SSSSSSSSS MUL D,S (waits one clock)
ZCMS 0111111 ZC I CCCC DDDDDDDDD SSSSSSSSS SCL D,S (waits one clock)
ZCWS 1000000 ZC I CCCC DDDDDDDDD SSSSSSSSS DECOD3 D,S
ZCWS 1000001 ZC I CCCC DDDDDDDDD SSSSSSSSS DECOD4 D,S
ZCWS 1000010 ZC I CCCC DDDDDDDDD SSSSSSSSS DECOD5 D,S
Z-WS 1000011 Z0 I CCCC DDDDDDDDD SSSSSSSSS ENCOD D,S
Z-WS 1000011 Z1 I CCCC DDDDDDDDD SSSSSSSSS BLMASK D,S
Z-WS 1000100 Z0 I CCCC DDDDDDDDD SSSSSSSSS ONECNT D,S (waits one clock)
Z-WS 1000100 Z1 I CCCC DDDDDDDDD SSSSSSSSS ZERCNT D,S (waits one clock)
-CWS 1000101 0C I CCCC DDDDDDDDD SSSSSSSSS INCPAT D,S (waits three clocks)
-CWS 1000101 1C I CCCC DDDDDDDDD SSSSSSSSS DECPAT D,S (waits three clocks)
--WS 1000110 00 I CCCC DDDDDDDDD SSSSSSSSS SPLITW D,S
--WS 1000110 01 I CCCC DDDDDDDDD SSSSSSSSS MERGEW D,S
--WS 1000110 10 I CCCC DDDDDDDDD SSSSSSSSS ESWAP4 D,S
--WS 1000110 11 I CCCC DDDDDDDDD SSSSSSSSS ESWAP8 D,S
--WS 1000111 00 I CCCC DDDDDDDDD SSSSSSSSS SEUSSF D,S
--WS 1000111 01 I CCCC DDDDDDDDD SSSSSSSSS SEUSSR D,S
--WS 1000111 10 I CCCC DDDDDDDDD SSSSSSSSS BINGRY D,S
--WS 1000111 11 I CCCC DDDDDDDDD SSSSSSSSS GRYBIN D,S (waits one clock)
--MS 10010nn n0 I CCCC DDDDDDDDD SSSSSSSSS GETNIB D,S,#n
--MS 10010nn n1 I CCCC DDDDDDDDD SSSSSSSSS SETNIB D,S,#n
--MS 1001100 n0 I CCCC DDDDDDDDD SSSSSSSSS GETWORD D,S,#n
--MS 1001100 n1 I CCCC DDDDDDDDD SSSSSSSSS SETWORD D,S,#n
--MS 1001110 00 I CCCC DDDDDDDDD SSSSSSSSS ROLNIB D,S
--MS 1001110 01 I CCCC DDDDDDDDD SSSSSSSSS ROLBYTE D,S
--MS 1001110 10 I CCCC DDDDDDDDD SSSSSSSSS ROLWORD D,S
--MS 1001110 11 I CCCC DDDDDDDDD SSSSSSSSS SWBYTES D,S (switch/copy bytes in D, S = _10_01_00 = D same)
--MS 1001111 00 I CCCC DDDDDDDDD SSSSSSSSS PACKRGB D,S (8:8:8 -> 5:5:5 << 16 | D >> 16)
--MS 1001111 01 I CCCC DDDDDDDDD SSSSSSSSS SETS D,S
--MS 1001111 10 I CCCC DDDDDDDDD SSSSSSSSS SETD D,S
--MS 1001111 11 I CCCC DDDDDDDDD SSSSSSSSS SETI D,S
--MS 101000n n0 I CCCC DDDDDDDDD SSSSSSSSS GETBYTE D,S,#n
--MS 101000n n1 I CCCC DDDDDDDDD SSSSSSSSS SETBYTE D,S,#n
-CMS 1010010 0C I CCCC DDDDDDDDD SSSSSSSSS COGNEW D,S (waits for hub)
-CMS 1010010 1C I CCCC DDDDDDDDD SSSSSSSSS WAITCNT D,S (waits for cnt)
--MS 1010011 00 I CCCC DDDDDDDDD SSSSSSSSS MIXPIX D,S (waits two clocks)
--MS 1010011 01 I CCCC DDDDDDDDD SSSSSSSSS MULPIX D,S (waits two clocks)
--MS 1010011 10 I CCCC DDDDDDDDD SSSSSSSSS MULPIX2 D,S (waits two clocks)
--MS 1010011 11 I CCCC DDDDDDDDD SSSSSSSSS ADDPIX D,S
ZCWS 1010100 ZC I CCCC DDDDDDDDD SSSSSSSSS JMPRET D,S (set D to INA for JMP/RET)
ZCWS 1010101 ZC I CCCC DDDDDDDDD SSSSSSSSS JMPRETD D,S (set D to INA for JMP/RET)
--MS 1010110 00 I CCCC DDDDDDDDD SSSSSSSSS IJZ D,S
--MS 1010110 01 I CCCC DDDDDDDDD SSSSSSSSS IJZD D,S
--MS 1010110 10 I CCCC DDDDDDDDD SSSSSSSSS IJNZ D,S
--MS 1010110 11 I CCCC DDDDDDDDD SSSSSSSSS IJNZD D,S
--MS 1010111 00 I CCCC DDDDDDDDD SSSSSSSSS DJZ D,S
--MS 1010111 01 I CCCC DDDDDDDDD SSSSSSSSS DJZD D,S
--MS 1010111 10 I CCCC DDDDDDDDD SSSSSSSSS DJNZ D,S
--MS 1010111 11 I CCCC DDDDDDDDD SSSSSSSSS DJNZD D,S
ZCRS 1011000 ZC I CCCC DDDDDDDDD SSSSSSSSS TESTB D,S
ZCRS 1011001 ZC I CCCC DDDDDDDDD SSSSSSSSS TESTN D,S
ZCRS 1011010 ZC I CCCC DDDDDDDDD SSSSSSSSS TEST D,S
ZCRS 1011011 ZC I CCCC DDDDDDDDD SSSSSSSSS CMP D,S
ZCRS 1011100 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPX D,S
ZCRS 1011101 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPS D,S
ZCRS 1011110 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPSX D,S
ZCRS 1011111 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPR D,S
--RS 11000nn n0 I CCCC DDDDDDDDD SSSSSSSSS COGINIT D,S,#0..7 (waits for hub) (SETNIB :coginit,cog,#6)
---S 11000nn n1 I CCCC nnnnnnnnn SSSSSSSSS WAITVID #n,S (waits for vid if single-task, loops if multi-task)
--RS 1100011 11 I CCCC DDDDDDDDD SSSSSSSSS WAITVID D,S (waits for vid if single-task, loops if multi-task)
-CRS 110010n nC I CCCC DDDDDDDDD SSSSSSSSS WAITPEQ D,S,#port (waits for pins, +cnt32 if wc) (4)
-CRS 110011n nC I CCCC DDDDDDDDD SSSSSSSSS WAITPNE D,S,#port (waits for pins, +cnt32 if wc) (4)
--LS 1101000 0L I CCCC DDDDDDDDD SSSSSSSSS WRBYTE D,S/PTR (waits for hub)
--LS 1101000 1L I CCCC DDDDDDDDD SSSSSSSSS WRWORD D,S/PTR (waits for hub)
--LS 1101001 0L I CCCC DDDDDDDDD SSSSSSSSS WRLONG D,S/PTR (waits for hub)
--LS 1101001 1L I CCCC DDDDDDDDD SSSSSSSSS FRAC32 D,S
--LS 1101010 0L I CCCC DDDDDDDDD SSSSSSSSS WRAUX D,S/#0..FF/SPx
--LS 1101010 1L I CCCC DDDDDDDDD SSSSSSSSS WRAUXR D,S/#0..FF/SPx
--LS 1101011 0L I CCCC DDDDDDDDD SSSSSSSSS SETACA D,S
--LS 1101011 1L I CCCC DDDDDDDDD SSSSSSSSS SETACB D,S
--LS 1101100 0L I CCCC DDDDDDDDD SSSSSSSSS MACA D,S
--LS 1101100 1L I CCCC DDDDDDDDD SSSSSSSSS MACB D,S
--LS 1101101 0L I CCCC DDDDDDDDD SSSSSSSSS DIV32 D,S
--LS 1101101 1L I CCCC DDDDDDDDD SSSSSSSSS DIV32U D,S
--LS 1101110 0L I CCCC DDDDDDDDD SSSSSSSSS DIV64 D,S
--LS 1101110 1L I CCCC DDDDDDDDD SSSSSSSSS DIV64U D,S
--LS 1101111 0L I CCCC DDDDDDDDD SSSSSSSSS MUL32 D,S
--LS 1101111 1L I CCCC DDDDDDDDD SSSSSSSSS MUL32U D,S
--LS 1110000 0L I CCCC DDDDDDDDD SSSSSSSSS SQRT64 D,S
--LS 1110000 1L I CCCC DDDDDDDDD SSSSSSSSS QSINCOS D,S
--LS 1110001 0L I CCCC DDDDDDDDD SSSSSSSSS QARCTAN D,S
--LS 1110001 1L I CCCC DDDDDDDDD SSSSSSSSS QROTATE D,S
--LS 1110010 0L I CCCC DDDDDDDDD SSSSSSSSS SETSERA D,S (config,baud)
--LS 1110010 1L I CCCC DDDDDDDDD SSSSSSSSS SETSERB D,S (config,baud)
--LS 1110011 0L I CCCC DDDDDDDDD SSSSSSSSS SETCTRS D,S
--LS 1110011 1L I CCCC DDDDDDDDD SSSSSSSSS SETWAVS D,S
--LS 1110100 0L I CCCC DDDDDDDDD SSSSSSSSS SETFRQS D,S
--LS 1110100 1L I CCCC DDDDDDDDD SSSSSSSSS SETPHSS D,S
--LS 1110101 0L I CCCC DDDDDDDDD SSSSSSSSS ADDPHSS D,S
--LS 1110101 1L I CCCC DDDDDDDDD SSSSSSSSS SUBPHSS D,S
--LS 1110110 0L I CCCC DDDDDDDDD SSSSSSSSS SETPIX0 D,S (config,Z)
--LS 1110110 1L I CCCC DDDDDDDDD SSSSSSSSS SETPIX1 D,S (U, V)
--LS 1110111 0L I CCCC DDDDDDDDD SSSSSSSSS SETPIX2 D,S (A, R)
--LS 1110111 1L I CCCC DDDDDDDDD SSSSSSSSS SETPIX3 D,S (G, B)
--LS 1111000 0L I CCCC DDDDDDDDD SSSSSSSSS CFGPINS D,S,#0 (waits for alt)
--LS 1111000 1L I CCCC DDDDDDDDD SSSSSSSSS CFGPINS D,S,#1 (waits for alt)
--LS 1111001 0L I CCCC DDDDDDDDD SSSSSSSSS CFGPINS D,S,#2 (waits for alt)
--LS 1111001 1L I CCCC DDDDDDDDD SSSSSSSSS JMPTASK D,S (mask,address)
--LS 1111010 0L I CCCC DDDDDDDDD SSSSSSSSS JP D,S
--LS 1111010 1L I CCCC DDDDDDDDD SSSSSSSSS JPD D,S
--LS 1111011 0L I CCCC DDDDDDDDD SSSSSSSSS JNP D,S
--LS 1111011 1L I CCCC DDDDDDDDD SSSSSSSSS JNPD D,S
--RS 1111100 00 I CCCC DDDDDDDDD SSSSSSSSS TJZ D,S
--RS 1111100 01 I CCCC DDDDDDDDD SSSSSSSSS TJZD D,S
--RS 1111100 10 I CCCC DDDDDDDDD SSSSSSSSS TJNZ D,S
--RS 1111100 11 I CCCC DDDDDDDDD SSSSSSSSS TJNZD D,S
<gap>
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000000 COGID D (waits for hub)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000001 LOCKNEW D (waits for hub)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000010 GETCNT D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000011 GETCNTX D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000100 GETLFSR D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000101 GETTOPS D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000110 GETACAL D (waits for mac)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000111 GETACAH D (waits for mac)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001000 GETACBL D (waits for mac)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001001 GETACBH D (waits for mac)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001010 GETPTRA D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001011 GETPTRB D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001100 GETSPA D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001101 GETSPB D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001110 GETMULL D (waits for mul if single-task, loops if multi-task)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001111 GETMULH D (waits for mul if single-task, loops if multi-task)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010000 GETDIVQ D (waits for div if single-task, loops if multi-task)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010001 GETDIVR D (waits for div if single-task, loops if multi-task)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010010 GETSQRT D (waits for sqrt if single-task, loops if multi-task)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010011 GETQX D (waits for cordic if single-task, loops if multi-task)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010100 GETQY D (waits for cordic if single-task, loops if multi-task)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010101 GETQZ D (waits for cordic if single-task, loops if multi-task)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010110 SERINA D (waits for rx if single-task, loops if multi-task, releases if wc)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010111 SERINB D (waits for rx if single-task, loops if multi-task, releases if wc)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011000 GETPHSA D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011001 GETPHZA D (clears phsa)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011010 GETCOSA D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011011 GETSINA D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011100 GETPHSB D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011101 GETPHZB D (clears phsb)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011110 GETCOSB D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011111 GETSINB D
ZCM- 1111110 ZC x CCCC DDDDDDDDD x00100000 PUSHZC D
ZCM- 1111110 ZC x CCCC DDDDDDDDD x00100001 POPZC D
ZCM- 1111110 ZC x CCCC DDDDDDDDD x00100010 SUBCNT D (subtracts D from cnt[31:0], then cntl if same thread)
ZCM- 1111110 ZC x CCCC DDDDDDDDD x00100011 GETPIX D (waits two clocks)
--M- 1111110 xx x CCCC DDDDDDDDD x00100100 INCD D (add $200 to D)
--M- 1111110 xx x CCCC DDDDDDDDD x00100101 DECD D (subtract $200 from D)
--M- 1111110 xx x CCCC DDDDDDDDD x00100110 INCDS D (add $201 to D)
--M- 1111110 xx x CCCC DDDDDDDDD x00100111 DECDS D (subtract $201 from D)
--L- 1111110 xx L CCCC DDDDDDDDD x00101000 CLKSET D (waits for hub)
-CL- 1111110 xC L CCCC DDDDDDDDD x00101001 COGIDX D (waits for hub)
--L- 1111110 xx L CCCC DDDDDDDDD x00101010 COGSTOP D (waits for hub)
--L- 1111110 xx L CCCC DDDDDDDDD x00101011 LOCKRET D (waits for hub)
-CL- 1111110 xC L CCCC DDDDDDDDD x00101100 LOCKSET D (waits for hub)
-CL- 1111110 xC L CCCC DDDDDDDDD x00101101 LOCKCLR D (waits for hub)
--L- 1111110 xx L CCCC DDDDDDDDD x00101110 WRQUAD D/PTR (waits for hub)
--L- 1111110 x0 L CCCC DDDDDDDDD x00101111 RDQUAD D/PTR (waits for hub)
--L- 1111110 x1 L CCCC DDDDDDDDD x00101111 RDQUADC D/PTR (waits for hub if cache miss)
ZCL- 1111110 ZC L CCCC DDDDDDDDD x00110000 GETP D (pin into !z/c via wz/wc)
ZCL- 1111110 ZC L CCCC DDDDDDDDD x00110001 GETNP D (pin into z/!c via wz/wc)
-CL- 1111110 xC L CCCC DDDDDDDDD x00110010 SEROUTA D (waits for tx if single-task, loops if multi-task, releases if wc)
-CL- 1111110 xC L CCCC DDDDDDDDD x00110011 SEROUTB D (waits for tx if single-task, loops if multi-task, releases if wc)
-CL- 1111110 xC L CCCC DDDDDDDDD x00110100 CMPCNT D (subtracts S from cnt[31:0], then cntl if same thread)
-CL- 1111110 xC L CCCC DDDDDDDDD x00110101 WAITCHG D (waits for edge)
-CL- 1111110 xC L CCCC DDDDDDDDD x00110110 WAITPOS D (waits for edge)
-CL- 1111110 xC L CCCC DDDDDDDDD x00110111 WAITNEG D (waits for edge)
ZCL- 1111110 ZC L CCCC DDDDDDDDD x00111000 SETZC D (D[1:0] into z/c via wz/wc)
--L- 1111110 xx L CCCC DDDDDDDDD x00111001 SETTASK D
--L- 1111110 xx L CCCC DDDDDDDDD x00111010 SETMAP D
--L- 1111110 xx L CCCC DDDDDDDDD x00111011 SETXCH D
--L- 1111110 xx L CCCC DDDDDDDDD x00111100 SETXFR D
--L- 1111110 xx L CCCC DDDDDDDDD x00111101 SARACA D (waits for mac)
--L- 1111110 xx L CCCC DDDDDDDDD x00111110 SARACB D (waits for mac)
--L- 1111110 xx L CCCC DDDDDDDDD x00111111 SARACS D (waits for mac)
--L- 1111110 xx L CCCC DDDDDDDDD x01iiiiii REPD D,#i (REPD $1FF,#i = infinite repeat)
--L- 1111110 xx L CCCC DDDDDDDDD x10000000 SETSPA D
--L- 1111110 xx L CCCC DDDDDDDDD x10000001 SETSPB D
--L- 1111110 xx L CCCC DDDDDDDDD x10000010 ADDSPA D
--L- 1111110 xx L CCCC DDDDDDDDD x10000011 ADDSPB D
--L- 1111110 xx L CCCC DDDDDDDDD x10000100 SUBSPA D
--L- 1111110 xx L CCCC DDDDDDDDD x10000101 SUBSPB D
--L- 1111110 xx L CCCC DDDDDDDDD x10000110 SETQUAD D
--L- 1111110 xx L CCCC DDDDDDDDD x10000111 SETQUAZ D
--L- 1111110 xx L CCCC DDDDDDDDD x10001000 SETPTRA D
--L- 1111110 xx L CCCC DDDDDDDDD x10001001 SETPTRB D
--L- 1111110 xx L CCCC DDDDDDDDD x10001010 ADDPTRA D
--L- 1111110 xx L CCCC DDDDDDDDD x10001011 ADDPTRB D
--L- 1111110 xx L CCCC DDDDDDDDD x10001100 SUBPTRA D
--L- 1111110 xx L CCCC DDDDDDDDD x10001101 SUBPTRB D
--L- 1111110 xx L CCCC DDDDDDDDD x10001110 PASSCNT D (loops if (cnt[31:0] - D) msb set)
--L- 1111110 xx L CCCC DDDDDDDDD x10001111 NOPX D (waits)
--L- 1111110 xx L CCCC DDDDDDDDD x10010000 CALLA D
--L- 1111110 xx L CCCC DDDDDDDDD x10010001 CALLB D
--L- 1111110 xx L CCCC DDDDDDDDD x10010010 CALLAD D
--L- 1111110 xx L CCCC DDDDDDDDD x10010011 CALLBD D
--L- 1111110 xx L CCCC DDDDDDDDD x10010100 CALLAR D
--L- 1111110 xx L CCCC DDDDDDDDD x10010101 CALLBR D
--L- 1111110 xx L CCCC DDDDDDDDD x10010110 CALLARD D
--L- 1111110 xx L CCCC DDDDDDDDD x10010111 CALLBRD D
--L- 1111110 xx L CCCC DDDDDDDDD x10011000 OFFP D
--L- 1111110 xx L CCCC DDDDDDDDD x10011001 NOTP D
--L- 1111110 xx L CCCC DDDDDDDDD x10011010 CLRP D
--L- 1111110 xx L CCCC DDDDDDDDD x10011011 SETP D
--L- 1111110 xx L CCCC DDDDDDDDD x10011100 SETPC D
--L- 1111110 xx L CCCC DDDDDDDDD x10011101 SETPNC D
--L- 1111110 xx L CCCC DDDDDDDDD x10011110 SETPZ D
--L- 1111110 xx L CCCC DDDDDDDDD x10011111 SETPNZ D
--L- 1111110 xx L CCCC DDDDDDDDD x10100000 DIV64D D
--L- 1111110 xx L CCCC DDDDDDDDD x10100001 SQRT32 D
--L- 1111110 xx L CCCC DDDDDDDDD x10100010 QLOG D
--L- 1111110 xx L CCCC DDDDDDDDD x10100011 QEXP D
--L- 1111110 xx L CCCC DDDDDDDDD x10100100 SETQI D
--L- 1111110 xx L CCCC DDDDDDDDD x10100101 SETQZ D
--L- 1111110 xx L CCCC DDDDDDDDD x10100110 CFGDACS D
--L- 1111110 xx L CCCC DDDDDDDDD x10100111 SETDACS D
--L- 1111110 xx L CCCC DDDDDDDDD x10101000 CFGDAC0 D
--L- 1111110 xx L CCCC DDDDDDDDD x10101001 CFGDAC1 D
--L- 1111110 xx L CCCC DDDDDDDDD x10101010 CFGDAC2 D
--L- 1111110 xx L CCCC DDDDDDDDD x10101011 CFGDAC3 D
--L- 1111110 xx L CCCC DDDDDDDDD x10101100 SETDAC0 D
--L- 1111110 xx L CCCC DDDDDDDDD x10101101 SETDAC1 D
--L- 1111110 xx L CCCC DDDDDDDDD x10101110 SETDAC2 D
--L- 1111110 xx L CCCC DDDDDDDDD x10101111 SETDAC3 D
--L- 1111110 xx L CCCC DDDDDDDDD x10110000 SETCTRA D
--L- 1111110 xx L CCCC DDDDDDDDD x10110001 SETWAVA D
--L- 1111110 xx L CCCC DDDDDDDDD x10110010 SETFRQA D
--L- 1111110 xx L CCCC DDDDDDDDD x10110011 SETPHSA D
--L- 1111110 xx L CCCC DDDDDDDDD x10110100 ADDPHSA D
--L- 1111110 xx L CCCC DDDDDDDDD x10110101 SUBPHSA D
--L- 1111110 xx L CCCC DDDDDDDDD x10110110 SETVID D
--L- 1111110 xx L CCCC DDDDDDDDD x10110111 SETVIDY D
--L- 1111110 xx L CCCC DDDDDDDDD x10111000 SETCTRB D
--L- 1111110 xx L CCCC DDDDDDDDD x10111001 SETWAVB D
--L- 1111110 xx L CCCC DDDDDDDDD x10111010 SETFRQB D
--L- 1111110 xx L CCCC DDDDDDDDD x10111011 SETPHSB D
--L- 1111110 xx L CCCC DDDDDDDDD x10111100 ADDPHSB D
--L- 1111110 xx L CCCC DDDDDDDDD x10111101 SUBPHSB D
--L- 1111110 xx L CCCC DDDDDDDDD x10111110 SETVIDI D
--L- 1111110 xx L CCCC DDDDDDDDD x10111111 SETVIDQ D
--L- 1111110 xx L CCCC DDDDDDDDD x11000000 SETPORA D
--L- 1111110 xx L CCCC DDDDDDDDD x11000001 SETPORB D
--L- 1111110 xx L CCCC DDDDDDDDD x11000010 SETPORC D
--L- 1111110 xx L CCCC DDDDDDDDD x11000011 SETPORD D
<gap>
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100000 RETA
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100001 RETB
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100010 RETAD
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100011 RETBD
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100100 RETAR
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100101 RETBR
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100110 RETARD
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100111 RETBRD
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11101000 TESTSPA
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11101001 TESTSPB
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11101010 POLCTRA (CTRA rollover into !Z/C)
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11101011 POLCTRB (CTRB rollover into !Z/C)
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11101100 POLVID (VID ready into !Z/C)
---- 1111110 xx x CCCC xxxxxxxxx x11101101 CAPCTRA
---- 1111110 xx x CCCC xxxxxxxxx x11101110 CAPCTRB
---- 1111110 xx x CCCC xxxxxxxxx x11101111 CAPCTRS
---- 1111110 xx L CCCC xxxxxxxxx x11110000 CACHEX
---- 1111110 xx L CCCC xxxxxxxxx x11110001 CLRACA
---- 1111110 xx L CCCC xxxxxxxxx x11110010 CLRACB
---- 1111110 xx L CCCC xxxxxxxxx x11110011 CLRACS
---- 1111110 xx x CCCC xxxxxxxxx x11110100 SYNCTRA (waits for ctra if single-task, loops if multi-task))
---- 1111110 xx x CCCC xxxxxxxxx x11110101 SYNCTRB (waits for ctrb if single-task, loops if multi-task))
<gap>
---- 1111111 0n n nnnn nnnnnnnnn nnniiiiii REPS #n,#i
---- 1111111 10 x BBAA DDDDDDDDD SSSSSSSSS SETINDx #D,#S (SETINDA S / SETINDB D / SETINDS D,S)
---- 1111111 11 x 0B0A DDDDDDDDD SSSSSSSSS FIXINDx #D,#S (FIXINDA D,S / FIXINDB D,S / FIXINDS D,S)
x = don't care, use 0
---------------------------------------------------------------------------------------------------------------------------------------------------------------
Now I've got to change the Verilog to reflect this new map. This will take several days.
Nice reorganization! Out of curiosity, why did you leave those last few instructions at %1111111 instead of placing the extended instruction set (currently at %1111110) at the end? I'm not asking for it to switched, just curious if there's a technical reason for it.
Nice reorganization! Out of curiosity, why did you leave those last few instructions at %1111111 instead of placing the extended instruction set (currently at %1111110) at the end? I'm not asking for it to switched, just curious if there's a technical reason for it.
Edit: And for all our sake, get some sleep!
I needed more bits than were available in the %1111110 set. Do you see a better way? I may not be thinking straight.
Those last 3 instructions were real odd-balls, so I put them at the end. Everything before those three is pretty regular. Weirdos to the back of the bus!
May I make a suggestion Chip for a replacement for the now obsolete ESWAP8 instruction.
In many PCB I/O layouts it quite common for pins to connected to dual row headers (0.1 inch for example).
Most PCB layouts tend to fan-out the pins so that one side of the connector is odd numbered I/o and the other even.
The F{GA boards are an example of this. P0,P2,P4 on one side and P1,P3,P5 the other.
In a lot of cases it would be nice to use a group of pins on one side of the connector.
My idea is a SPREAD instruction that does the following.
SPREAD D,S
where s = %11001 for example
D would = %0101000001 after
A simple shift could align to odd/even bits or maybe WC could be used to shift left 1 bit optionally.
Basically the 9 bits of an immediate or the lower 16 bits of S are spread over 32 bits
A reverse instruction SQUISH could do the opposite. Every 2nd bit is aligned to create a 16 bit result. WC could be used to grab odd/even bits.
This would simplify/reduce code required to mask/modify IO pins.
I've been busy for the last few days reorganizing the op-code mapping and I think I've got it about done. In the new scheme, instructions' result-writing is fixed. For the cases where it was useful to not write the result (SUB NR = CMP), there are now dedicated non-result-writing instructions. Z and C writing is still controllable, of course, since that is mission critical.
By getting rid of the R bit, the instruction set was able to expand, so that things like unary operations can have separate source and destination registers. This new instruction coding is much simpler and more regular than before. It will make assemblers and compilers easier to write. Also, a lot of configuration operations take fewer instructions now, since both D and S can convey immediate or register data. For example: SETSERA D,S (config,baud). It now takes 4 instructions to configure the texture mapper, where it used to take 8.
Roy Eltham and I have been talking about what can be done to improve the texture mapper and he suggested quite a few byte/pixel transforms and new blending methods, such as additive and multiplicative (both 1x and 2x). All these pixel blends will now be able to be done directly, without engaging the texture mapper, through simple instructions.
Propeller II Revised Op-Codes (16 October 2013)
ZCDS (for D column: W=write, M=modify, R=read, L=read/immediate)
---------------------------------------------------------------------------------------------------------------------------------------------------------------
ZCWS 0000000 ZC I CCCC DDDDDDDDD SSSSSSSSS RDBYTE D,S/PTRx (waits for hub)
ZCWS 0000001 ZC I CCCC DDDDDDDDD SSSSSSSSS RDBYTEC D,S/PTRx (waits for hub if cache miss)
ZCWS 0000010 ZC I CCCC DDDDDDDDD SSSSSSSSS RDWORD D,S/PTRx (waits for hub)
ZCWS 0000011 ZC I CCCC DDDDDDDDD SSSSSSSSS RDWORDC D,S/PTRx (waits for hub if cache miss)
ZCWS 0000100 ZC I CCCC DDDDDDDDD SSSSSSSSS RDLONG D,S/PTRx (waits for hub)
ZCWS 0000101 ZC I CCCC DDDDDDDDD SSSSSSSSS RDLONGC D,S/PTRx (waits for hub if cache miss)
ZCWS 0000110 ZC I CCCC DDDDDDDDD SSSSSSSSS RDAUX D,S/#/SPx
ZCWS 0000111 ZC I CCCC DDDDDDDDD SSSSSSSSS RDAUXR D,S/#/SPx
ZCMS 0001000 ZC I CCCC DDDDDDDDD SSSSSSSSS ISOB D,S
ZCMS 0001001 ZC I CCCC DDDDDDDDD SSSSSSSSS NOTB D,S
ZCMS 0001010 ZC I CCCC DDDDDDDDD SSSSSSSSS CLRB D,S
ZCMS 0001011 ZC I CCCC DDDDDDDDD SSSSSSSSS SETB D,S
ZCMS 0001100 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBC D,S
ZCMS 0001101 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBNC D,S
ZCMS 0001110 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBZ D,S
ZCMS 0001111 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBNZ D,S
ZCMS 0010000 ZC I CCCC DDDDDDDDD SSSSSSSSS ANDN D,S
ZCMS 0010001 ZC I CCCC DDDDDDDDD SSSSSSSSS AND D,S
ZCMS 0010010 ZC I CCCC DDDDDDDDD SSSSSSSSS OR D,S
ZCMS 0010011 ZC I CCCC DDDDDDDDD SSSSSSSSS XOR D,S
ZCMS 0010100 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXC D,S
ZCMS 0010101 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXNC D,S
ZCMS 0010110 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXZ D,S
ZCMS 0010111 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXNZ D,S
ZCMS 0011000 ZC I CCCC DDDDDDDDD SSSSSSSSS ROR D,S
ZCMS 0011001 ZC I CCCC DDDDDDDDD SSSSSSSSS ROL D,S
ZCMS 0011010 ZC I CCCC DDDDDDDDD SSSSSSSSS SHR D,S
ZCMS 0011011 ZC I CCCC DDDDDDDDD SSSSSSSSS SHL D,S
ZCMS 0011100 ZC I CCCC DDDDDDDDD SSSSSSSSS RCR D,S
ZCMS 0011101 ZC I CCCC DDDDDDDDD SSSSSSSSS RCL D,S
ZCMS 0011110 ZC I CCCC DDDDDDDDD SSSSSSSSS SAR D,S
ZCMS 0011111 ZC I CCCC DDDDDDDDD SSSSSSSSS REV D,S
ZCWS 0100000 ZC I CCCC DDDDDDDDD SSSSSSSSS MOV D,S
ZCWS 0100001 ZC I CCCC DDDDDDDDD SSSSSSSSS NOT D,S
ZCWS 0100010 ZC I CCCC DDDDDDDDD SSSSSSSSS ABS D,S
ZCWS 0100011 ZC I CCCC DDDDDDDDD SSSSSSSSS NEG D,S
ZCWS 0100100 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGC D,S
ZCWS 0100101 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGNC D,S
ZCWS 0100110 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGZ D,S
ZCWS 0100111 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGNZ D,S
ZCMS 0101000 ZC I CCCC DDDDDDDDD SSSSSSSSS ADD D,S
ZCMS 0101001 ZC I CCCC DDDDDDDDD SSSSSSSSS SUB D,S
ZCMS 0101010 ZC I CCCC DDDDDDDDD SSSSSSSSS ADDX D,S
ZCMS 0101011 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBX D,S
ZCMS 0101100 ZC I CCCC DDDDDDDDD SSSSSSSSS ADDS D,S
ZCMS 0101101 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBS D,S
ZCMS 0101110 ZC I CCCC DDDDDDDDD SSSSSSSSS ADDSX D,S
ZCMS 0101111 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBSX D,S
ZCMS 0110000 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMC D,S
ZCMS 0110001 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMNC D,S
ZCMS 0110010 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMZ D,S
ZCMS 0110011 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMNZ D,S
ZCMS 0110100 ZC I CCCC DDDDDDDDD SSSSSSSSS MINS D,S
ZCMS 0110101 ZC I CCCC DDDDDDDDD SSSSSSSSS MAXS D,S
ZCMS 0110110 ZC I CCCC DDDDDDDDD SSSSSSSSS MIN D,S
ZCMS 0110111 ZC I CCCC DDDDDDDDD SSSSSSSSS MAX D,S
ZCMS 0111000 ZC I CCCC DDDDDDDDD SSSSSSSSS ADDABS D,S
ZCMS 0111001 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBABS D,S
ZCMS 0111010 ZC I CCCC DDDDDDDDD SSSSSSSSS INCMOD D,S
ZCMS 0111011 ZC I CCCC DDDDDDDDD SSSSSSSSS DECMOD D,S
ZCMS 0111100 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPSUB D,S
ZCMS 0111101 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBR D,S
ZCMS 0111110 ZC I CCCC DDDDDDDDD SSSSSSSSS MUL D,S (waits one clock)
ZCMS 0111111 ZC I CCCC DDDDDDDDD SSSSSSSSS SCL D,S (waits one clock)
ZCWS 1000000 ZC I CCCC DDDDDDDDD SSSSSSSSS DECOD3 D,S
ZCWS 1000001 ZC I CCCC DDDDDDDDD SSSSSSSSS DECOD4 D,S
ZCWS 1000010 ZC I CCCC DDDDDDDDD SSSSSSSSS DECOD5 D,S
Z-WS 1000011 Z0 I CCCC DDDDDDDDD SSSSSSSSS ENCOD D,S
Z-WS 1000011 Z1 I CCCC DDDDDDDDD SSSSSSSSS BLMASK D,S
Z-WS 1000100 Z0 I CCCC DDDDDDDDD SSSSSSSSS ONECNT D,S (waits one clock)
Z-WS 1000100 Z1 I CCCC DDDDDDDDD SSSSSSSSS ZERCNT D,S (waits one clock)
-CWS 1000101 0C I CCCC DDDDDDDDD SSSSSSSSS INCPAT D,S (waits three clocks)
-CWS 1000101 1C I CCCC DDDDDDDDD SSSSSSSSS DECPAT D,S (waits three clocks)
--WS 1000110 00 I CCCC DDDDDDDDD SSSSSSSSS SPLITW D,S
--WS 1000110 01 I CCCC DDDDDDDDD SSSSSSSSS MERGEW D,S
--WS 1000110 10 I CCCC DDDDDDDDD SSSSSSSSS ESWAP4 D,S
--WS 1000110 11 I CCCC DDDDDDDDD SSSSSSSSS ESWAP8 D,S
--WS 1000111 00 I CCCC DDDDDDDDD SSSSSSSSS SEUSSF D,S
--WS 1000111 01 I CCCC DDDDDDDDD SSSSSSSSS SEUSSR D,S
--WS 1000111 10 I CCCC DDDDDDDDD SSSSSSSSS BINGRY D,S
--WS 1000111 11 I CCCC DDDDDDDDD SSSSSSSSS GRYBIN D,S (waits one clock)
--MS 10010nn n0 I CCCC DDDDDDDDD SSSSSSSSS GETNIB D,S,#n
--MS 10010nn n1 I CCCC DDDDDDDDD SSSSSSSSS SETNIB D,S,#n
--MS 1001100 n0 I CCCC DDDDDDDDD SSSSSSSSS GETWORD D,S,#n
--MS 1001100 n1 I CCCC DDDDDDDDD SSSSSSSSS SETWORD D,S,#n
--MS 1001110 00 I CCCC DDDDDDDDD SSSSSSSSS ROLNIB D,S
--MS 1001110 01 I CCCC DDDDDDDDD SSSSSSSSS ROLBYTE D,S
--MS 1001110 10 I CCCC DDDDDDDDD SSSSSSSSS ROLWORD D,S
--MS 1001110 11 I CCCC DDDDDDDDD SSSSSSSSS SWBYTES D,S (switch/copy bytes in D, S = %11_10_01_00 = D same)
--MS 1001111 00 I CCCC DDDDDDDDD SSSSSSSSS PACKRGB D,S (8:8:8 -> 5:5:5 << 16 | D >> 16)
--MS 1001111 01 I CCCC DDDDDDDDD SSSSSSSSS SETS D,S
--MS 1001111 10 I CCCC DDDDDDDDD SSSSSSSSS SETD D,S
--MS 1001111 11 I CCCC DDDDDDDDD SSSSSSSSS SETI D,S
--MS 101000n n0 I CCCC DDDDDDDDD SSSSSSSSS GETBYTE D,S,#n
--MS 101000n n1 I CCCC DDDDDDDDD SSSSSSSSS SETBYTE D,S,#n
-CMS 1010010 0C I CCCC DDDDDDDDD SSSSSSSSS COGNEW D,S (waits for hub)
-CMS 1010010 1C I CCCC DDDDDDDDD SSSSSSSSS WAITCNT D,S (waits for cnt)
--MS 1010011 00 I CCCC DDDDDDDDD SSSSSSSSS MIXPIX D,S (waits two clocks)
--MS 1010011 01 I CCCC DDDDDDDDD SSSSSSSSS MULPIX D,S (waits two clocks)
--MS 1010011 10 I CCCC DDDDDDDDD SSSSSSSSS MULPIX2 D,S (waits two clocks)
--MS 1010011 11 I CCCC DDDDDDDDD SSSSSSSSS ADDPIX D,S
ZCWS 1010100 ZC I CCCC DDDDDDDDD SSSSSSSSS JMPRET D,S (set D to INA for JMP/RET)
ZCWS 1010101 ZC I CCCC DDDDDDDDD SSSSSSSSS JMPRETD D,S (set D to INA for JMP/RET)
--MS 1010110 00 I CCCC DDDDDDDDD SSSSSSSSS IJZ D,S
--MS 1010110 01 I CCCC DDDDDDDDD SSSSSSSSS IJZD D,S
--MS 1010110 10 I CCCC DDDDDDDDD SSSSSSSSS IJNZ D,S
--MS 1010110 11 I CCCC DDDDDDDDD SSSSSSSSS IJNZD D,S
--MS 1010111 00 I CCCC DDDDDDDDD SSSSSSSSS DJZ D,S
--MS 1010111 01 I CCCC DDDDDDDDD SSSSSSSSS DJZD D,S
--MS 1010111 10 I CCCC DDDDDDDDD SSSSSSSSS DJNZ D,S
--MS 1010111 11 I CCCC DDDDDDDDD SSSSSSSSS DJNZD D,S
ZCRS 1011000 ZC I CCCC DDDDDDDDD SSSSSSSSS TESTB D,S
ZCRS 1011001 ZC I CCCC DDDDDDDDD SSSSSSSSS TESTN D,S
ZCRS 1011010 ZC I CCCC DDDDDDDDD SSSSSSSSS TEST D,S
ZCRS 1011011 ZC I CCCC DDDDDDDDD SSSSSSSSS CMP D,S
ZCRS 1011100 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPX D,S
ZCRS 1011101 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPS D,S
ZCRS 1011110 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPSX D,S
ZCRS 1011111 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPR D,S
--RS 11000nn n0 I CCCC DDDDDDDDD SSSSSSSSS COGINIT D,S,#0..7 (waits for hub) (SETNIB :coginit,cog,#6)
---S 11000nn n1 I CCCC nnnnnnnnn SSSSSSSSS WAITVID #n,S (waits for vid if single-task, loops if multi-task)
--RS 1100011 11 I CCCC DDDDDDDDD SSSSSSSSS WAITVID D,S (waits for vid if single-task, loops if multi-task)
-CRS 110010n nC I CCCC DDDDDDDDD SSSSSSSSS WAITPEQ D,S,#port (waits for pins, +cnt32 if wc) (4)
-CRS 110011n nC I CCCC DDDDDDDDD SSSSSSSSS WAITPNE D,S,#port (waits for pins, +cnt32 if wc) (4)
--LS 1101000 0L I CCCC DDDDDDDDD SSSSSSSSS WRBYTE D,S/PTR (waits for hub)
--LS 1101000 1L I CCCC DDDDDDDDD SSSSSSSSS WRWORD D,S/PTR (waits for hub)
--LS 1101001 0L I CCCC DDDDDDDDD SSSSSSSSS WRLONG D,S/PTR (waits for hub)
--LS 1101001 1L I CCCC DDDDDDDDD SSSSSSSSS FRAC32 D,S
--LS 1101010 0L I CCCC DDDDDDDDD SSSSSSSSS WRAUX D,S/#0..FF/SPx
--LS 1101010 1L I CCCC DDDDDDDDD SSSSSSSSS WRAUXR D,S/#0..FF/SPx
--LS 1101011 0L I CCCC DDDDDDDDD SSSSSSSSS SETACA D,S
--LS 1101011 1L I CCCC DDDDDDDDD SSSSSSSSS SETACB D,S
--LS 1101100 0L I CCCC DDDDDDDDD SSSSSSSSS MACA D,S
--LS 1101100 1L I CCCC DDDDDDDDD SSSSSSSSS MACB D,S
--LS 1101101 0L I CCCC DDDDDDDDD SSSSSSSSS DIV32 D,S
--LS 1101101 1L I CCCC DDDDDDDDD SSSSSSSSS DIV32U D,S
--LS 1101110 0L I CCCC DDDDDDDDD SSSSSSSSS DIV64 D,S
--LS 1101110 1L I CCCC DDDDDDDDD SSSSSSSSS DIV64U D,S
--LS 1101111 0L I CCCC DDDDDDDDD SSSSSSSSS MUL32 D,S
--LS 1101111 1L I CCCC DDDDDDDDD SSSSSSSSS MUL32U D,S
--LS 1110000 0L I CCCC DDDDDDDDD SSSSSSSSS SQRT64 D,S
--LS 1110000 1L I CCCC DDDDDDDDD SSSSSSSSS QSINCOS D,S
--LS 1110001 0L I CCCC DDDDDDDDD SSSSSSSSS QARCTAN D,S
--LS 1110001 1L I CCCC DDDDDDDDD SSSSSSSSS QROTATE D,S
--LS 1110010 0L I CCCC DDDDDDDDD SSSSSSSSS SETSERA D,S (config,baud)
--LS 1110010 1L I CCCC DDDDDDDDD SSSSSSSSS SETSERB D,S (config,baud)
--LS 1110011 0L I CCCC DDDDDDDDD SSSSSSSSS SETCTRS D,S
--LS 1110011 1L I CCCC DDDDDDDDD SSSSSSSSS SETWAVS D,S
--LS 1110100 0L I CCCC DDDDDDDDD SSSSSSSSS SETFRQS D,S
--LS 1110100 1L I CCCC DDDDDDDDD SSSSSSSSS SETPHSS D,S
--LS 1110101 0L I CCCC DDDDDDDDD SSSSSSSSS ADDPHSS D,S
--LS 1110101 1L I CCCC DDDDDDDDD SSSSSSSSS SUBPHSS D,S
--LS 1110110 0L I CCCC DDDDDDDDD SSSSSSSSS SETPIX0 D,S (config,Z)
--LS 1110110 1L I CCCC DDDDDDDDD SSSSSSSSS SETPIX1 D,S (U, V)
--LS 1110111 0L I CCCC DDDDDDDDD SSSSSSSSS SETPIX2 D,S (A, R)
--LS 1110111 1L I CCCC DDDDDDDDD SSSSSSSSS SETPIX3 D,S (G, B)
--LS 1111000 0L I CCCC DDDDDDDDD SSSSSSSSS CFGPINS D,S,#0 (waits for alt)
--LS 1111000 1L I CCCC DDDDDDDDD SSSSSSSSS CFGPINS D,S,#1 (waits for alt)
--LS 1111001 0L I CCCC DDDDDDDDD SSSSSSSSS CFGPINS D,S,#2 (waits for alt)
--LS 1111001 1L I CCCC DDDDDDDDD SSSSSSSSS JMPTASK D,S (mask,address)
--LS 1111010 0L I CCCC DDDDDDDDD SSSSSSSSS JP D,S
--LS 1111010 1L I CCCC DDDDDDDDD SSSSSSSSS JPD D,S
--LS 1111011 0L I CCCC DDDDDDDDD SSSSSSSSS JNP D,S
--LS 1111011 1L I CCCC DDDDDDDDD SSSSSSSSS JNPD D,S
--RS 1111100 00 I CCCC DDDDDDDDD SSSSSSSSS TJZ D,S
--RS 1111100 01 I CCCC DDDDDDDDD SSSSSSSSS TJZD D,S
--RS 1111100 10 I CCCC DDDDDDDDD SSSSSSSSS TJNZ D,S
--RS 1111100 11 I CCCC DDDDDDDDD SSSSSSSSS TJNZD D,S
<gap>
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000000 COGID D (waits for hub)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000001 LOCKNEW D (waits for hub)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000010 GETCNT D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000011 GETCNTX D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000100 GETLFSR D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000101 GETTOPS D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000110 GETACAL D (waits for mac)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000111 GETACAH D (waits for mac)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001000 GETACBL D (waits for mac)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001001 GETACBH D (waits for mac)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001010 GETPTRA D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001011 GETPTRB D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001100 GETSPA D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001101 GETSPB D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001110 GETMULL D (waits for mul if single-task, loops if multi-task)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001111 GETMULH D (waits for mul if single-task, loops if multi-task)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010000 GETDIVQ D (waits for div if single-task, loops if multi-task)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010001 GETDIVR D (waits for div if single-task, loops if multi-task)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010010 GETSQRT D (waits for sqrt if single-task, loops if multi-task)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010011 GETQX D (waits for cordic if single-task, loops if multi-task)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010100 GETQY D (waits for cordic if single-task, loops if multi-task)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010101 GETQZ D (waits for cordic if single-task, loops if multi-task)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010110 SERINA D (waits for rx if single-task, loops if multi-task, releases if wc)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010111 SERINB D (waits for rx if single-task, loops if multi-task, releases if wc)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011000 GETPHSA D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011001 GETPHZA D (clears phsa)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011010 GETCOSA D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011011 GETSINA D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011100 GETPHSB D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011101 GETPHZB D (clears phsb)
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011110 GETCOSB D
ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011111 GETSINB D
ZCM- 1111110 ZC x CCCC DDDDDDDDD x00100000 PUSHZC D
ZCM- 1111110 ZC x CCCC DDDDDDDDD x00100001 POPZC D
ZCM- 1111110 ZC x CCCC DDDDDDDDD x00100010 SUBCNT D (subtracts D from cnt[31:0], then cntl if same thread)
ZCM- 1111110 ZC x CCCC DDDDDDDDD x00100011 GETPIX D (waits two clocks)
--M- 1111110 xx x CCCC DDDDDDDDD x00100100 INCD D (add $200 to D)
--M- 1111110 xx x CCCC DDDDDDDDD x00100101 DECD D (subtract $200 from D)
--M- 1111110 xx x CCCC DDDDDDDDD x00100110 INCDS D (add $201 to D)
--M- 1111110 xx x CCCC DDDDDDDDD x00100111 DECDS D (subtract $201 from D)
--L- 1111110 xx L CCCC DDDDDDDDD x00101000 CLKSET D (waits for hub)
-CL- 1111110 xC L CCCC DDDDDDDDD x00101001 COGIDX D (waits for hub)
--L- 1111110 xx L CCCC DDDDDDDDD x00101010 COGSTOP D (waits for hub)
--L- 1111110 xx L CCCC DDDDDDDDD x00101011 LOCKRET D (waits for hub)
-CL- 1111110 xC L CCCC DDDDDDDDD x00101100 LOCKSET D (waits for hub)
-CL- 1111110 xC L CCCC DDDDDDDDD x00101101 LOCKCLR D (waits for hub)
--L- 1111110 xx L CCCC DDDDDDDDD x00101110 WRQUAD D/PTR (waits for hub)
--L- 1111110 x0 L CCCC DDDDDDDDD x00101111 RDQUAD D/PTR (waits for hub)
--L- 1111110 x1 L CCCC DDDDDDDDD x00101111 RDQUADC D/PTR (waits for hub if cache miss)
ZCL- 1111110 ZC L CCCC DDDDDDDDD x00110000 GETP D (pin into !z/c via wz/wc)
ZCL- 1111110 ZC L CCCC DDDDDDDDD x00110001 GETNP D (pin into z/!c via wz/wc)
-CL- 1111110 xC L CCCC DDDDDDDDD x00110010 SEROUTA D (waits for tx if single-task, loops if multi-task, releases if wc)
-CL- 1111110 xC L CCCC DDDDDDDDD x00110011 SEROUTB D (waits for tx if single-task, loops if multi-task, releases if wc)
-CL- 1111110 xC L CCCC DDDDDDDDD x00110100 CMPCNT D (subtracts S from cnt[31:0], then cntl if same thread)
-CL- 1111110 xC L CCCC DDDDDDDDD x00110101 WAITCHG D (waits for edge)
-CL- 1111110 xC L CCCC DDDDDDDDD x00110110 WAITPOS D (waits for edge)
-CL- 1111110 xC L CCCC DDDDDDDDD x00110111 WAITNEG D (waits for edge)
ZCL- 1111110 ZC L CCCC DDDDDDDDD x00111000 SETZC D (D[1:0] into z/c via wz/wc)
--L- 1111110 xx L CCCC DDDDDDDDD x00111001 SETTASK D
--L- 1111110 xx L CCCC DDDDDDDDD x00111010 SETMAP D
--L- 1111110 xx L CCCC DDDDDDDDD x00111011 SETXCH D
--L- 1111110 xx L CCCC DDDDDDDDD x00111100 SETXFR D
--L- 1111110 xx L CCCC DDDDDDDDD x00111101 SARACA D (waits for mac)
--L- 1111110 xx L CCCC DDDDDDDDD x00111110 SARACB D (waits for mac)
--L- 1111110 xx L CCCC DDDDDDDDD x00111111 SARACS D (waits for mac)
--L- 1111110 xx L CCCC DDDDDDDDD x01iiiiii REPD D,#i (REPD $1FF,#i = infinite repeat)
--L- 1111110 xx L CCCC DDDDDDDDD x10000000 SETSPA D
--L- 1111110 xx L CCCC DDDDDDDDD x10000001 SETSPB D
--L- 1111110 xx L CCCC DDDDDDDDD x10000010 ADDSPA D
--L- 1111110 xx L CCCC DDDDDDDDD x10000011 ADDSPB D
--L- 1111110 xx L CCCC DDDDDDDDD x10000100 SUBSPA D
--L- 1111110 xx L CCCC DDDDDDDDD x10000101 SUBSPB D
--L- 1111110 xx L CCCC DDDDDDDDD x10000110 SETQUAD D
--L- 1111110 xx L CCCC DDDDDDDDD x10000111 SETQUAZ D
--L- 1111110 xx L CCCC DDDDDDDDD x10001000 SETPTRA D
--L- 1111110 xx L CCCC DDDDDDDDD x10001001 SETPTRB D
--L- 1111110 xx L CCCC DDDDDDDDD x10001010 ADDPTRA D
--L- 1111110 xx L CCCC DDDDDDDDD x10001011 ADDPTRB D
--L- 1111110 xx L CCCC DDDDDDDDD x10001100 SUBPTRA D
--L- 1111110 xx L CCCC DDDDDDDDD x10001101 SUBPTRB D
--L- 1111110 xx L CCCC DDDDDDDDD x10001110 PASSCNT D (loops if (cnt[31:0] - D) msb set)
--L- 1111110 xx L CCCC DDDDDDDDD x10001111 NOPX D (waits)
--L- 1111110 xx L CCCC DDDDDDDDD x10010000 CALLA D
--L- 1111110 xx L CCCC DDDDDDDDD x10010001 CALLB D
--L- 1111110 xx L CCCC DDDDDDDDD x10010010 CALLAD D
--L- 1111110 xx L CCCC DDDDDDDDD x10010011 CALLBD D
--L- 1111110 xx L CCCC DDDDDDDDD x10010100 CALLAR D
--L- 1111110 xx L CCCC DDDDDDDDD x10010101 CALLBR D
--L- 1111110 xx L CCCC DDDDDDDDD x10010110 CALLARD D
--L- 1111110 xx L CCCC DDDDDDDDD x10010111 CALLBRD D
--L- 1111110 xx L CCCC DDDDDDDDD x10011000 OFFP D
--L- 1111110 xx L CCCC DDDDDDDDD x10011001 NOTP D
--L- 1111110 xx L CCCC DDDDDDDDD x10011010 CLRP D
--L- 1111110 xx L CCCC DDDDDDDDD x10011011 SETP D
--L- 1111110 xx L CCCC DDDDDDDDD x10011100 SETPC D
--L- 1111110 xx L CCCC DDDDDDDDD x10011101 SETPNC D
--L- 1111110 xx L CCCC DDDDDDDDD x10011110 SETPZ D
--L- 1111110 xx L CCCC DDDDDDDDD x10011111 SETPNZ D
--L- 1111110 xx L CCCC DDDDDDDDD x10100000 DIV64D D
--L- 1111110 xx L CCCC DDDDDDDDD x10100001 SQRT32 D
--L- 1111110 xx L CCCC DDDDDDDDD x10100010 QLOG D
--L- 1111110 xx L CCCC DDDDDDDDD x10100011 QEXP D
--L- 1111110 xx L CCCC DDDDDDDDD x10100100 SETQI D
--L- 1111110 xx L CCCC DDDDDDDDD x10100101 SETQZ D
--L- 1111110 xx L CCCC DDDDDDDDD x10100110 CFGDACS D
--L- 1111110 xx L CCCC DDDDDDDDD x10100111 SETDACS D
--L- 1111110 xx L CCCC DDDDDDDDD x10101000 CFGDAC0 D
--L- 1111110 xx L CCCC DDDDDDDDD x10101001 CFGDAC1 D
--L- 1111110 xx L CCCC DDDDDDDDD x10101010 CFGDAC2 D
--L- 1111110 xx L CCCC DDDDDDDDD x10101011 CFGDAC3 D
--L- 1111110 xx L CCCC DDDDDDDDD x10101100 SETDAC0 D
--L- 1111110 xx L CCCC DDDDDDDDD x10101101 SETDAC1 D
--L- 1111110 xx L CCCC DDDDDDDDD x10101110 SETDAC2 D
--L- 1111110 xx L CCCC DDDDDDDDD x10101111 SETDAC3 D
--L- 1111110 xx L CCCC DDDDDDDDD x10110000 SETCTRA D
--L- 1111110 xx L CCCC DDDDDDDDD x10110001 SETWAVA D
--L- 1111110 xx L CCCC DDDDDDDDD x10110010 SETFRQA D
--L- 1111110 xx L CCCC DDDDDDDDD x10110011 SETPHSA D
--L- 1111110 xx L CCCC DDDDDDDDD x10110100 ADDPHSA D
--L- 1111110 xx L CCCC DDDDDDDDD x10110101 SUBPHSA D
--L- 1111110 xx L CCCC DDDDDDDDD x10110110 SETVID D
--L- 1111110 xx L CCCC DDDDDDDDD x10110111 SETVIDY D
--L- 1111110 xx L CCCC DDDDDDDDD x10111000 SETCTRB D
--L- 1111110 xx L CCCC DDDDDDDDD x10111001 SETWAVB D
--L- 1111110 xx L CCCC DDDDDDDDD x10111010 SETFRQB D
--L- 1111110 xx L CCCC DDDDDDDDD x10111011 SETPHSB D
--L- 1111110 xx L CCCC DDDDDDDDD x10111100 ADDPHSB D
--L- 1111110 xx L CCCC DDDDDDDDD x10111101 SUBPHSB D
--L- 1111110 xx L CCCC DDDDDDDDD x10111110 SETVIDI D
--L- 1111110 xx L CCCC DDDDDDDDD x10111111 SETVIDQ D
--L- 1111110 xx L CCCC DDDDDDDDD x11000000 SETPORA D
--L- 1111110 xx L CCCC DDDDDDDDD x11000001 SETPORB D
--L- 1111110 xx L CCCC DDDDDDDDD x11000010 SETPORC D
--L- 1111110 xx L CCCC DDDDDDDDD x11000011 SETPORD D
<gap>
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100000 RETA
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100001 RETB
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100010 RETAD
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100011 RETBD
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100100 RETAR
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100101 RETBR
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100110 RETARD
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100111 RETBRD
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11101000 TESTSPA
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11101001 TESTSPB
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11101010 POLCTRA (CTRA rollover into !Z/C)
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11101011 POLCTRB (CTRB rollover into !Z/C)
ZC-- 1111110 ZC x CCCC xxxxxxxxx x11101100 POLVID (VID ready into !Z/C)
---- 1111110 xx x CCCC xxxxxxxxx x11101101 CAPCTRA
---- 1111110 xx x CCCC xxxxxxxxx x11101110 CAPCTRB
---- 1111110 xx x CCCC xxxxxxxxx x11101111 CAPCTRS
---- 1111110 xx L CCCC xxxxxxxxx x11110000 CACHEX
---- 1111110 xx L CCCC xxxxxxxxx x11110001 CLRACA
---- 1111110 xx L CCCC xxxxxxxxx x11110010 CLRACB
---- 1111110 xx L CCCC xxxxxxxxx x11110011 CLRACS
---- 1111110 xx x CCCC xxxxxxxxx x11110100 SYNCTRA (waits for ctra if single-task, loops if multi-task))
---- 1111110 xx x CCCC xxxxxxxxx x11110101 SYNCTRB (waits for ctrb if single-task, loops if multi-task))
<gap>
---- 1111111 0n n nnnn nnnnnnnnn nnniiiiii REPS #n,#i
---- 1111111 10 x BBAA DDDDDDDDD SSSSSSSSS SETINDx #D,#S (SETINDA S / SETINDB D / SETINDS D,S)
---- 1111111 11 x 0B0A DDDDDDDDD SSSSSSSSS FIXINDx #D,#S (FIXINDA D,S / FIXINDB D,S / FIXINDS D,S)
x = don't care, use 0
---------------------------------------------------------------------------------------------------------------------------------------------------------------
Now I've got to change the Verilog and the assembler in PNUT to reflect this new map. This will take several days.
I am curious about what the 'R' stands for in {RD|WR}AUXR
There's also a CALLAR, CALLBR, CALLARD, and CALLBRD. Since STACK is now AUX, I think the "R" refers to "reverse" (like the old PUSHA[R] and POPA[R]). For the RDAUX/WRAUX operations, I'm guessing that the "R" is only differentiated from the non-"R" version when using SPA/SPB. Going out on a limb, I'm guessing SPA/SPB is used when the MSB of S-field is set (otherwise, it's an absolute offset between 0 and 255). However, why have the separate "R" version in that case? Couldn't the increment/decrement of SPA/SPB be encoded in the lower eight bits (similar to the INDA/INDB encoding)?
Looks nice Chip! MIXPIX could be BLNDPIX maybe? or just have both with one being an alias.
Couldn't ESWAP8 also be done with SWBYTES? Would free an instruction there. Could have an alias for ESWAP8 to the appropriate SWBYTES maybe?
ESWAP8 moves the value from S to D, whereas SWBYTES works on D using S. I'll leave them for now. There are plenty of opportunities for new instruction slots, if we need them.
Comments
You guys might have noticed how adding all these new instructions was introducing many caveats into the op-code mapping. It had become a big Swiss cheese. A lot of waste was occurring, too because of WR bits (R) that never practically changed, effectively cutting the number of possible instructions in half. There needs to be individual control of Z and C writing, but only a few cases of controlling D writing offered any value, like SUB versus CMP.
I'm combing through the op-codes now, grouping them by D-writing and flag-affecting. It's freed up tons of instruction space we can now have D,S instructions wherever they're beneficial. I'll post the list a little later today when it's more final.
That's right.
By the way, I added the timeout via WC, just like WAITPEQ/WAITPNE.
Interesting idea :
Then the edge detector becomes a mini cell (one per COG) that always operates, but discards any history if Index changes.
That would allow a sticky/not-sticky option however starting it could get tricky ?
One pin value would need to be illegal/reset value, and to set the pin index, you would need to execute the opcode.
[ with 3 choices already, Rise, Fall, Change, is there a free 4th value, that can be used to set the pin index, but not wait ? ]
That would allow SW to prime the detector, then do other stuff then check /wait when it was ready.
A loop tail case that took longer, would still proceed with some jitter, (but no missing edges) and as long as the next loop was shorter, re-sync would resume.
If someone used in this in 2 threads, I think it proceeds on an interleave-stall basis ?
Magic
I'm doing a lot of work in P1 using the global clock, and keeping track of individual threads' timings relative to that. Very frequently I need to know whether or not the global counter is ahead or behind a target value, and I do that with a subtract. Trouble always is what to do about roll-overs. So the answer is to do a subtract, and examine the most significant bit (31) of the result, because just looking at the subtract's borrow will not work when rollovers are present. A left shift puts bit31 into the carry, and this works great, but takes more instructions than is desired for fast operations.
For the P2, could you invent a single cycle instruction that does a subtract, and copies bit31 into the carry ? It will reduce 3 instructions down to 1 for many locations in my code.
Cheers,
Peter (pjv)
I'd posted this question on another thread, but since it's important to me to know, I'll repeat it here:
On the subject of QUAD-related instructions operation, despite the last documents doesn't describe it that way, could you confirm or deny, if a SETQUAD or SETQUAZ instruction execution, inherently implies a CACHEX-like operation too?
Yanomani
P.S. Answered by Chip, at the original thread.
"No, only CACHEX causes the cache to be invalidated."
"Even driven" seems to be quite a woolly term. So what I meant by it is a bit different. What you have described there sounds like traditional interrupt handling except instead of jumping to an interrupt routine a whole new COG is started to handle it.
What I had in mind my "event driven" is a bit more fine grained. A single program might have many things it needs to wait for at different stages of it's processing. A UART for example needs to wait on:
a) Arrival of a character from the user program to be transmitted.
b) A timer so that it can bit-bang the TX at the right time.
c) An input pin so it can respond to incoming start bits.
d) Another timer so it can clock in the Rx bits on time.
e) Perhaps other signals for flow control.
Here we have code halting exection and waiting for the next event, when the event arrives it ressumes execution immediately. No context saving and jumping to an interrupt routine, no loading of a COG, it's just ready to run.
This kind of event driven processing can be done by having many processors each of which can wait on anything when ever it likes without blocking others. Or it can be be done with hardware scheduled threads.
The UART is better done in hardware, it was only an example of what I mean by "event driven programming". The same style can be used for many other things. The idea is a code goes around it can have many points where it has to wait for some condition to become true, an event.
Now interrupts are a way to respond to events but they do have the problem that whatever is running is stopped whilst the interrupt handler run. They can also suffer form latency issues as you have to save processor context prior to executing the handler.
On a single processor machine an RTOS is what is used to get processes to wait on events, and interrupts are used to kick the RTOS around. Here we have all the problems of interrupts plus the latency and overheads of an OS and it thread switching etc.
You solution, starting a COG to handle an even, can no doubt work but how do we get around the huge latency of loading a COG and starting it?
Good point. An ideal implementation of events would have the instruction waiting for an event halt until the event occurs. Thus consuming a lot less power. Isn't this what happens with WAITPxx, WAITVID etc. Not sure how it works with multi-threading on the Prop II.
Are those instructions the eq. to a dormant cog, in terms of power consumption? As for P2 and threads, I'm not sure either. I suspect, though, that power will be squandered to some degree.
By getting rid of the R bit, the instruction set was able to expand, so that things like unary operations can have separate source and destination registers. This new instruction coding is much simpler and more regular than before. It will make assemblers and compilers easier to write. Also, a lot of configuration operations take fewer instructions now, since both D and S can convey immediate or register data. For example: SETSERA D,S (config,baud). It now takes 4 instructions to configure the texture mapper, where it used to take 8.
Roy Eltham and I have been talking about what can be done to improve the texture mapper and he suggested quite a few byte/pixel transforms and new blending methods, such as additive and multiplicative (both 1x and 2x). All these pixel blends will now be able to be done directly, without engaging the texture mapper, through simple instructions.
Propeller II Revised Op-Codes (16 October 2013) ZCDS (for D column: W=write, M=modify, R=read, L=read/immediate) --------------------------------------------------------------------------------------------------------------------------------------------------------------- ZCWS 0000000 ZC I CCCC DDDDDDDDD SSSSSSSSS RDBYTE D,S/PTRx (waits for hub) ZCWS 0000001 ZC I CCCC DDDDDDDDD SSSSSSSSS RDBYTEC D,S/PTRx (waits for hub if cache miss) ZCWS 0000010 ZC I CCCC DDDDDDDDD SSSSSSSSS RDWORD D,S/PTRx (waits for hub) ZCWS 0000011 ZC I CCCC DDDDDDDDD SSSSSSSSS RDWORDC D,S/PTRx (waits for hub if cache miss) ZCWS 0000100 ZC I CCCC DDDDDDDDD SSSSSSSSS RDLONG D,S/PTRx (waits for hub) ZCWS 0000101 ZC I CCCC DDDDDDDDD SSSSSSSSS RDLONGC D,S/PTRx (waits for hub if cache miss) ZCWS 0000110 ZC I CCCC DDDDDDDDD SSSSSSSSS RDAUX D,S/#/SPx ZCWS 0000111 ZC I CCCC DDDDDDDDD SSSSSSSSS RDAUXR D,S/#/SPx ZCMS 0001000 ZC I CCCC DDDDDDDDD SSSSSSSSS ISOB D,S ZCMS 0001001 ZC I CCCC DDDDDDDDD SSSSSSSSS NOTB D,S ZCMS 0001010 ZC I CCCC DDDDDDDDD SSSSSSSSS CLRB D,S ZCMS 0001011 ZC I CCCC DDDDDDDDD SSSSSSSSS SETB D,S ZCMS 0001100 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBC D,S ZCMS 0001101 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBNC D,S ZCMS 0001110 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBZ D,S ZCMS 0001111 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBNZ D,S ZCMS 0010000 ZC I CCCC DDDDDDDDD SSSSSSSSS ANDN D,S ZCMS 0010001 ZC I CCCC DDDDDDDDD SSSSSSSSS AND D,S ZCMS 0010010 ZC I CCCC DDDDDDDDD SSSSSSSSS OR D,S ZCMS 0010011 ZC I CCCC DDDDDDDDD SSSSSSSSS XOR D,S ZCMS 0010100 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXC D,S ZCMS 0010101 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXNC D,S ZCMS 0010110 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXZ D,S ZCMS 0010111 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXNZ D,S ZCMS 0011000 ZC I CCCC DDDDDDDDD SSSSSSSSS ROR D,S ZCMS 0011001 ZC I CCCC DDDDDDDDD SSSSSSSSS ROL D,S ZCMS 0011010 ZC I CCCC DDDDDDDDD SSSSSSSSS SHR D,S ZCMS 0011011 ZC I CCCC DDDDDDDDD SSSSSSSSS SHL D,S ZCMS 0011100 ZC I CCCC DDDDDDDDD SSSSSSSSS RCR D,S ZCMS 0011101 ZC I CCCC DDDDDDDDD SSSSSSSSS RCL D,S ZCMS 0011110 ZC I CCCC DDDDDDDDD SSSSSSSSS SAR D,S ZCMS 0011111 ZC I CCCC DDDDDDDDD SSSSSSSSS REV D,S ZCWS 0100000 ZC I CCCC DDDDDDDDD SSSSSSSSS MOV D,S ZCWS 0100001 ZC I CCCC DDDDDDDDD SSSSSSSSS NOT D,S ZCWS 0100010 ZC I CCCC DDDDDDDDD SSSSSSSSS ABS D,S ZCWS 0100011 ZC I CCCC DDDDDDDDD SSSSSSSSS NEG D,S ZCWS 0100100 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGC D,S ZCWS 0100101 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGNC D,S ZCWS 0100110 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGZ D,S ZCWS 0100111 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGNZ D,S ZCMS 0101000 ZC I CCCC DDDDDDDDD SSSSSSSSS ADD D,S ZCMS 0101001 ZC I CCCC DDDDDDDDD SSSSSSSSS SUB D,S ZCMS 0101010 ZC I CCCC DDDDDDDDD SSSSSSSSS ADDX D,S ZCMS 0101011 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBX D,S ZCMS 0101100 ZC I CCCC DDDDDDDDD SSSSSSSSS ADDS D,S ZCMS 0101101 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBS D,S ZCMS 0101110 ZC I CCCC DDDDDDDDD SSSSSSSSS ADDSX D,S ZCMS 0101111 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBSX D,S ZCMS 0110000 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMC D,S ZCMS 0110001 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMNC D,S ZCMS 0110010 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMZ D,S ZCMS 0110011 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMNZ D,S ZCMS 0110100 ZC I CCCC DDDDDDDDD SSSSSSSSS MINS D,S ZCMS 0110101 ZC I CCCC DDDDDDDDD SSSSSSSSS MAXS D,S ZCMS 0110110 ZC I CCCC DDDDDDDDD SSSSSSSSS MIN D,S ZCMS 0110111 ZC I CCCC DDDDDDDDD SSSSSSSSS MAX D,S ZCMS 0111000 ZC I CCCC DDDDDDDDD SSSSSSSSS ADDABS D,S ZCMS 0111001 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBABS D,S ZCMS 0111010 ZC I CCCC DDDDDDDDD SSSSSSSSS INCMOD D,S ZCMS 0111011 ZC I CCCC DDDDDDDDD SSSSSSSSS DECMOD D,S ZCMS 0111100 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPSUB D,S ZCMS 0111101 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBR D,S ZCMS 0111110 ZC I CCCC DDDDDDDDD SSSSSSSSS MUL D,S (waits one clock) ZCMS 0111111 ZC I CCCC DDDDDDDDD SSSSSSSSS SCL D,S (waits one clock) ZCWS 1000000 ZC I CCCC DDDDDDDDD SSSSSSSSS DECOD3 D,S ZCWS 1000001 ZC I CCCC DDDDDDDDD SSSSSSSSS DECOD4 D,S ZCWS 1000010 ZC I CCCC DDDDDDDDD SSSSSSSSS DECOD5 D,S Z-WS 1000011 Z0 I CCCC DDDDDDDDD SSSSSSSSS ENCOD D,S Z-WS 1000011 Z1 I CCCC DDDDDDDDD SSSSSSSSS BLMASK D,S Z-WS 1000100 Z0 I CCCC DDDDDDDDD SSSSSSSSS ONECNT D,S (waits one clock) Z-WS 1000100 Z1 I CCCC DDDDDDDDD SSSSSSSSS ZERCNT D,S (waits one clock) -CWS 1000101 0C I CCCC DDDDDDDDD SSSSSSSSS INCPAT D,S (waits three clocks) -CWS 1000101 1C I CCCC DDDDDDDDD SSSSSSSSS DECPAT D,S (waits three clocks) --WS 1000110 00 I CCCC DDDDDDDDD SSSSSSSSS SPLITW D,S --WS 1000110 01 I CCCC DDDDDDDDD SSSSSSSSS MERGEW D,S --WS 1000110 10 I CCCC DDDDDDDDD SSSSSSSSS ESWAP4 D,S --WS 1000110 11 I CCCC DDDDDDDDD SSSSSSSSS ESWAP8 D,S --WS 1000111 00 I CCCC DDDDDDDDD SSSSSSSSS SEUSSF D,S --WS 1000111 01 I CCCC DDDDDDDDD SSSSSSSSS SEUSSR D,S --WS 1000111 10 I CCCC DDDDDDDDD SSSSSSSSS BINGRY D,S --WS 1000111 11 I CCCC DDDDDDDDD SSSSSSSSS GRYBIN D,S (waits one clock) --MS 10010nn n0 I CCCC DDDDDDDDD SSSSSSSSS GETNIB D,S,#n --MS 10010nn n1 I CCCC DDDDDDDDD SSSSSSSSS SETNIB D,S,#n --MS 1001100 n0 I CCCC DDDDDDDDD SSSSSSSSS GETWORD D,S,#n --MS 1001100 n1 I CCCC DDDDDDDDD SSSSSSSSS SETWORD D,S,#n --MS 1001110 00 I CCCC DDDDDDDDD SSSSSSSSS ROLNIB D,S --MS 1001110 01 I CCCC DDDDDDDDD SSSSSSSSS ROLBYTE D,S --MS 1001110 10 I CCCC DDDDDDDDD SSSSSSSSS ROLWORD D,S --MS 1001110 11 I CCCC DDDDDDDDD SSSSSSSSS SWBYTES D,S (switch/copy bytes in D, S = %11_10_01_00 = D same) --MS 1001111 00 I CCCC DDDDDDDDD SSSSSSSSS PACKRGB D,S (8:8:8 -> 5:5:5 << 16 | D >> 16) --MS 1001111 01 I CCCC DDDDDDDDD SSSSSSSSS SETS D,S --MS 1001111 10 I CCCC DDDDDDDDD SSSSSSSSS SETD D,S --MS 1001111 11 I CCCC DDDDDDDDD SSSSSSSSS SETI D,S --MS 101000n n0 I CCCC DDDDDDDDD SSSSSSSSS GETBYTE D,S,#n --MS 101000n n1 I CCCC DDDDDDDDD SSSSSSSSS SETBYTE D,S,#n -CMS 1010010 0C I CCCC DDDDDDDDD SSSSSSSSS COGNEW D,S (waits for hub) -CMS 1010010 1C I CCCC DDDDDDDDD SSSSSSSSS WAITCNT D,S (waits for cnt) --MS 1010011 00 I CCCC DDDDDDDDD SSSSSSSSS MIXPIX D,S (waits two clocks) --MS 1010011 01 I CCCC DDDDDDDDD SSSSSSSSS MULPIX D,S (waits two clocks) --MS 1010011 10 I CCCC DDDDDDDDD SSSSSSSSS MULPIX2 D,S (waits two clocks) --MS 1010011 11 I CCCC DDDDDDDDD SSSSSSSSS ADDPIX D,S ZCWS 1010100 ZC I CCCC DDDDDDDDD SSSSSSSSS JMPRET D,S (set D to INA for JMP/RET) ZCWS 1010101 ZC I CCCC DDDDDDDDD SSSSSSSSS JMPRETD D,S (set D to INA for JMP/RET) --MS 1010110 00 I CCCC DDDDDDDDD SSSSSSSSS IJZ D,S --MS 1010110 01 I CCCC DDDDDDDDD SSSSSSSSS IJZD D,S --MS 1010110 10 I CCCC DDDDDDDDD SSSSSSSSS IJNZ D,S --MS 1010110 11 I CCCC DDDDDDDDD SSSSSSSSS IJNZD D,S --MS 1010111 00 I CCCC DDDDDDDDD SSSSSSSSS DJZ D,S --MS 1010111 01 I CCCC DDDDDDDDD SSSSSSSSS DJZD D,S --MS 1010111 10 I CCCC DDDDDDDDD SSSSSSSSS DJNZ D,S --MS 1010111 11 I CCCC DDDDDDDDD SSSSSSSSS DJNZD D,S ZCRS 1011000 ZC I CCCC DDDDDDDDD SSSSSSSSS TESTB D,S ZCRS 1011001 ZC I CCCC DDDDDDDDD SSSSSSSSS TESTN D,S ZCRS 1011010 ZC I CCCC DDDDDDDDD SSSSSSSSS TEST D,S ZCRS 1011011 ZC I CCCC DDDDDDDDD SSSSSSSSS CMP D,S ZCRS 1011100 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPX D,S ZCRS 1011101 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPS D,S ZCRS 1011110 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPSX D,S ZCRS 1011111 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPR D,S --RS 11000nn n0 I CCCC DDDDDDDDD SSSSSSSSS COGINIT D,S,#0..7 (waits for hub) (SETNIB :coginit,cog,#6) ---S 11000nn n1 I CCCC nnnnnnnnn SSSSSSSSS WAITVID #n,S (waits for vid if single-task, loops if multi-task) --RS 1100011 11 I CCCC DDDDDDDDD SSSSSSSSS WAITVID D,S (waits for vid if single-task, loops if multi-task) -CRS 110010n nC I CCCC DDDDDDDDD SSSSSSSSS WAITPEQ D,S,#port (waits for pins, +cnt32 if wc) (4) -CRS 110011n nC I CCCC DDDDDDDDD SSSSSSSSS WAITPNE D,S,#port (waits for pins, +cnt32 if wc) (4) --LS 1101000 0L I CCCC DDDDDDDDD SSSSSSSSS WRBYTE D,S/PTR (waits for hub) --LS 1101000 1L I CCCC DDDDDDDDD SSSSSSSSS WRWORD D,S/PTR (waits for hub) --LS 1101001 0L I CCCC DDDDDDDDD SSSSSSSSS WRLONG D,S/PTR (waits for hub) --LS 1101001 1L I CCCC DDDDDDDDD SSSSSSSSS FRAC32 D,S --LS 1101010 0L I CCCC DDDDDDDDD SSSSSSSSS WRAUX D,S/#0..FF/SPx --LS 1101010 1L I CCCC DDDDDDDDD SSSSSSSSS WRAUXR D,S/#0..FF/SPx --LS 1101011 0L I CCCC DDDDDDDDD SSSSSSSSS SETACA D,S --LS 1101011 1L I CCCC DDDDDDDDD SSSSSSSSS SETACB D,S --LS 1101100 0L I CCCC DDDDDDDDD SSSSSSSSS MACA D,S --LS 1101100 1L I CCCC DDDDDDDDD SSSSSSSSS MACB D,S --LS 1101101 0L I CCCC DDDDDDDDD SSSSSSSSS DIV32 D,S --LS 1101101 1L I CCCC DDDDDDDDD SSSSSSSSS DIV32U D,S --LS 1101110 0L I CCCC DDDDDDDDD SSSSSSSSS DIV64 D,S --LS 1101110 1L I CCCC DDDDDDDDD SSSSSSSSS DIV64U D,S --LS 1101111 0L I CCCC DDDDDDDDD SSSSSSSSS MUL32 D,S --LS 1101111 1L I CCCC DDDDDDDDD SSSSSSSSS MUL32U D,S --LS 1110000 0L I CCCC DDDDDDDDD SSSSSSSSS SQRT64 D,S --LS 1110000 1L I CCCC DDDDDDDDD SSSSSSSSS QSINCOS D,S --LS 1110001 0L I CCCC DDDDDDDDD SSSSSSSSS QARCTAN D,S --LS 1110001 1L I CCCC DDDDDDDDD SSSSSSSSS QROTATE D,S --LS 1110010 0L I CCCC DDDDDDDDD SSSSSSSSS SETSERA D,S (config,baud) --LS 1110010 1L I CCCC DDDDDDDDD SSSSSSSSS SETSERB D,S (config,baud) --LS 1110011 0L I CCCC DDDDDDDDD SSSSSSSSS SETCTRS D,S --LS 1110011 1L I CCCC DDDDDDDDD SSSSSSSSS SETWAVS D,S --LS 1110100 0L I CCCC DDDDDDDDD SSSSSSSSS SETFRQS D,S --LS 1110100 1L I CCCC DDDDDDDDD SSSSSSSSS SETPHSS D,S --LS 1110101 0L I CCCC DDDDDDDDD SSSSSSSSS ADDPHSS D,S --LS 1110101 1L I CCCC DDDDDDDDD SSSSSSSSS SUBPHSS D,S --LS 1110110 0L I CCCC DDDDDDDDD SSSSSSSSS SETPIX0 D,S (config,Z) --LS 1110110 1L I CCCC DDDDDDDDD SSSSSSSSS SETPIX1 D,S (U, V) --LS 1110111 0L I CCCC DDDDDDDDD SSSSSSSSS SETPIX2 D,S (A, R) --LS 1110111 1L I CCCC DDDDDDDDD SSSSSSSSS SETPIX3 D,S (G, B) --LS 1111000 0L I CCCC DDDDDDDDD SSSSSSSSS CFGPINS D,S,#0 (waits for alt) --LS 1111000 1L I CCCC DDDDDDDDD SSSSSSSSS CFGPINS D,S,#1 (waits for alt) --LS 1111001 0L I CCCC DDDDDDDDD SSSSSSSSS CFGPINS D,S,#2 (waits for alt) --LS 1111001 1L I CCCC DDDDDDDDD SSSSSSSSS JMPTASK D,S (mask,address) --LS 1111010 0L I CCCC DDDDDDDDD SSSSSSSSS JP D,S --LS 1111010 1L I CCCC DDDDDDDDD SSSSSSSSS JPD D,S --LS 1111011 0L I CCCC DDDDDDDDD SSSSSSSSS JNP D,S --LS 1111011 1L I CCCC DDDDDDDDD SSSSSSSSS JNPD D,S --RS 1111100 00 I CCCC DDDDDDDDD SSSSSSSSS TJZ D,S --RS 1111100 01 I CCCC DDDDDDDDD SSSSSSSSS TJZD D,S --RS 1111100 10 I CCCC DDDDDDDDD SSSSSSSSS TJNZ D,S --RS 1111100 11 I CCCC DDDDDDDDD SSSSSSSSS TJNZD D,S <gap> ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000000 COGID D (waits for hub) ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000001 LOCKNEW D (waits for hub) ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000010 GETCNT D ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000011 GETCNTX D ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000100 GETLFSR D ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000101 GETTOPS D ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000110 GETACAL D (waits for mac) ZCW- 1111110 ZC x CCCC DDDDDDDDD x00000111 GETACAH D (waits for mac) ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001000 GETACBL D (waits for mac) ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001001 GETACBH D (waits for mac) ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001010 GETPTRA D ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001011 GETPTRB D ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001100 GETSPA D ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001101 GETSPB D ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001110 GETMULL D (waits for mul if single-task, loops if multi-task) ZCW- 1111110 ZC x CCCC DDDDDDDDD x00001111 GETMULH D (waits for mul if single-task, loops if multi-task) ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010000 GETDIVQ D (waits for div if single-task, loops if multi-task) ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010001 GETDIVR D (waits for div if single-task, loops if multi-task) ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010010 GETSQRT D (waits for sqrt if single-task, loops if multi-task) ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010011 GETQX D (waits for cordic if single-task, loops if multi-task) ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010100 GETQY D (waits for cordic if single-task, loops if multi-task) ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010101 GETQZ D (waits for cordic if single-task, loops if multi-task) ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010110 SERINA D (waits for rx if single-task, loops if multi-task, releases if wc) ZCW- 1111110 ZC x CCCC DDDDDDDDD x00010111 SERINB D (waits for rx if single-task, loops if multi-task, releases if wc) ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011000 GETPHSA D ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011001 GETPHZA D (clears phsa) ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011010 GETCOSA D ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011011 GETSINA D ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011100 GETPHSB D ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011101 GETPHZB D (clears phsb) ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011110 GETCOSB D ZCW- 1111110 ZC x CCCC DDDDDDDDD x00011111 GETSINB D ZCM- 1111110 ZC x CCCC DDDDDDDDD x00100000 PUSHZC D ZCM- 1111110 ZC x CCCC DDDDDDDDD x00100001 POPZC D ZCM- 1111110 ZC x CCCC DDDDDDDDD x00100010 SUBCNT D (subtracts D from cnt[31:0], then cntl if same thread) ZCM- 1111110 ZC x CCCC DDDDDDDDD x00100011 GETPIX D (waits two clocks) --M- 1111110 xx x CCCC DDDDDDDDD x00100100 INCD D (add $200 to D) --M- 1111110 xx x CCCC DDDDDDDDD x00100101 DECD D (subtract $200 from D) --M- 1111110 xx x CCCC DDDDDDDDD x00100110 INCDS D (add $201 to D) --M- 1111110 xx x CCCC DDDDDDDDD x00100111 DECDS D (subtract $201 from D) --L- 1111110 xx L CCCC DDDDDDDDD x00101000 CLKSET D (waits for hub) -CL- 1111110 xC L CCCC DDDDDDDDD x00101001 COGIDX D (waits for hub) --L- 1111110 xx L CCCC DDDDDDDDD x00101010 COGSTOP D (waits for hub) --L- 1111110 xx L CCCC DDDDDDDDD x00101011 LOCKRET D (waits for hub) -CL- 1111110 xC L CCCC DDDDDDDDD x00101100 LOCKSET D (waits for hub) -CL- 1111110 xC L CCCC DDDDDDDDD x00101101 LOCKCLR D (waits for hub) --L- 1111110 xx L CCCC DDDDDDDDD x00101110 WRQUAD D/PTR (waits for hub) --L- 1111110 x0 L CCCC DDDDDDDDD x00101111 RDQUAD D/PTR (waits for hub) --L- 1111110 x1 L CCCC DDDDDDDDD x00101111 RDQUADC D/PTR (waits for hub if cache miss) ZCL- 1111110 ZC L CCCC DDDDDDDDD x00110000 GETP D (pin into !z/c via wz/wc) ZCL- 1111110 ZC L CCCC DDDDDDDDD x00110001 GETNP D (pin into z/!c via wz/wc) -CL- 1111110 xC L CCCC DDDDDDDDD x00110010 SEROUTA D (waits for tx if single-task, loops if multi-task, releases if wc) -CL- 1111110 xC L CCCC DDDDDDDDD x00110011 SEROUTB D (waits for tx if single-task, loops if multi-task, releases if wc) -CL- 1111110 xC L CCCC DDDDDDDDD x00110100 CMPCNT D (subtracts S from cnt[31:0], then cntl if same thread) -CL- 1111110 xC L CCCC DDDDDDDDD x00110101 WAITCHG D (waits for edge) -CL- 1111110 xC L CCCC DDDDDDDDD x00110110 WAITPOS D (waits for edge) -CL- 1111110 xC L CCCC DDDDDDDDD x00110111 WAITNEG D (waits for edge) ZCL- 1111110 ZC L CCCC DDDDDDDDD x00111000 SETZC D (D[1:0] into z/c via wz/wc) --L- 1111110 xx L CCCC DDDDDDDDD x00111001 SETTASK D --L- 1111110 xx L CCCC DDDDDDDDD x00111010 SETMAP D --L- 1111110 xx L CCCC DDDDDDDDD x00111011 SETXCH D --L- 1111110 xx L CCCC DDDDDDDDD x00111100 SETXFR D --L- 1111110 xx L CCCC DDDDDDDDD x00111101 SARACA D (waits for mac) --L- 1111110 xx L CCCC DDDDDDDDD x00111110 SARACB D (waits for mac) --L- 1111110 xx L CCCC DDDDDDDDD x00111111 SARACS D (waits for mac) --L- 1111110 xx L CCCC DDDDDDDDD x01iiiiii REPD D,#i (REPD $1FF,#i = infinite repeat) --L- 1111110 xx L CCCC DDDDDDDDD x10000000 SETSPA D --L- 1111110 xx L CCCC DDDDDDDDD x10000001 SETSPB D --L- 1111110 xx L CCCC DDDDDDDDD x10000010 ADDSPA D --L- 1111110 xx L CCCC DDDDDDDDD x10000011 ADDSPB D --L- 1111110 xx L CCCC DDDDDDDDD x10000100 SUBSPA D --L- 1111110 xx L CCCC DDDDDDDDD x10000101 SUBSPB D --L- 1111110 xx L CCCC DDDDDDDDD x10000110 SETQUAD D --L- 1111110 xx L CCCC DDDDDDDDD x10000111 SETQUAZ D --L- 1111110 xx L CCCC DDDDDDDDD x10001000 SETPTRA D --L- 1111110 xx L CCCC DDDDDDDDD x10001001 SETPTRB D --L- 1111110 xx L CCCC DDDDDDDDD x10001010 ADDPTRA D --L- 1111110 xx L CCCC DDDDDDDDD x10001011 ADDPTRB D --L- 1111110 xx L CCCC DDDDDDDDD x10001100 SUBPTRA D --L- 1111110 xx L CCCC DDDDDDDDD x10001101 SUBPTRB D --L- 1111110 xx L CCCC DDDDDDDDD x10001110 PASSCNT D (loops if (cnt[31:0] - D) msb set) --L- 1111110 xx L CCCC DDDDDDDDD x10001111 NOPX D (waits) --L- 1111110 xx L CCCC DDDDDDDDD x10010000 CALLA D --L- 1111110 xx L CCCC DDDDDDDDD x10010001 CALLB D --L- 1111110 xx L CCCC DDDDDDDDD x10010010 CALLAD D --L- 1111110 xx L CCCC DDDDDDDDD x10010011 CALLBD D --L- 1111110 xx L CCCC DDDDDDDDD x10010100 CALLAR D --L- 1111110 xx L CCCC DDDDDDDDD x10010101 CALLBR D --L- 1111110 xx L CCCC DDDDDDDDD x10010110 CALLARD D --L- 1111110 xx L CCCC DDDDDDDDD x10010111 CALLBRD D --L- 1111110 xx L CCCC DDDDDDDDD x10011000 OFFP D --L- 1111110 xx L CCCC DDDDDDDDD x10011001 NOTP D --L- 1111110 xx L CCCC DDDDDDDDD x10011010 CLRP D --L- 1111110 xx L CCCC DDDDDDDDD x10011011 SETP D --L- 1111110 xx L CCCC DDDDDDDDD x10011100 SETPC D --L- 1111110 xx L CCCC DDDDDDDDD x10011101 SETPNC D --L- 1111110 xx L CCCC DDDDDDDDD x10011110 SETPZ D --L- 1111110 xx L CCCC DDDDDDDDD x10011111 SETPNZ D --L- 1111110 xx L CCCC DDDDDDDDD x10100000 DIV64D D --L- 1111110 xx L CCCC DDDDDDDDD x10100001 SQRT32 D --L- 1111110 xx L CCCC DDDDDDDDD x10100010 QLOG D --L- 1111110 xx L CCCC DDDDDDDDD x10100011 QEXP D --L- 1111110 xx L CCCC DDDDDDDDD x10100100 SETQI D --L- 1111110 xx L CCCC DDDDDDDDD x10100101 SETQZ D --L- 1111110 xx L CCCC DDDDDDDDD x10100110 CFGDACS D --L- 1111110 xx L CCCC DDDDDDDDD x10100111 SETDACS D --L- 1111110 xx L CCCC DDDDDDDDD x10101000 CFGDAC0 D --L- 1111110 xx L CCCC DDDDDDDDD x10101001 CFGDAC1 D --L- 1111110 xx L CCCC DDDDDDDDD x10101010 CFGDAC2 D --L- 1111110 xx L CCCC DDDDDDDDD x10101011 CFGDAC3 D --L- 1111110 xx L CCCC DDDDDDDDD x10101100 SETDAC0 D --L- 1111110 xx L CCCC DDDDDDDDD x10101101 SETDAC1 D --L- 1111110 xx L CCCC DDDDDDDDD x10101110 SETDAC2 D --L- 1111110 xx L CCCC DDDDDDDDD x10101111 SETDAC3 D --L- 1111110 xx L CCCC DDDDDDDDD x10110000 SETCTRA D --L- 1111110 xx L CCCC DDDDDDDDD x10110001 SETWAVA D --L- 1111110 xx L CCCC DDDDDDDDD x10110010 SETFRQA D --L- 1111110 xx L CCCC DDDDDDDDD x10110011 SETPHSA D --L- 1111110 xx L CCCC DDDDDDDDD x10110100 ADDPHSA D --L- 1111110 xx L CCCC DDDDDDDDD x10110101 SUBPHSA D --L- 1111110 xx L CCCC DDDDDDDDD x10110110 SETVID D --L- 1111110 xx L CCCC DDDDDDDDD x10110111 SETVIDY D --L- 1111110 xx L CCCC DDDDDDDDD x10111000 SETCTRB D --L- 1111110 xx L CCCC DDDDDDDDD x10111001 SETWAVB D --L- 1111110 xx L CCCC DDDDDDDDD x10111010 SETFRQB D --L- 1111110 xx L CCCC DDDDDDDDD x10111011 SETPHSB D --L- 1111110 xx L CCCC DDDDDDDDD x10111100 ADDPHSB D --L- 1111110 xx L CCCC DDDDDDDDD x10111101 SUBPHSB D --L- 1111110 xx L CCCC DDDDDDDDD x10111110 SETVIDI D --L- 1111110 xx L CCCC DDDDDDDDD x10111111 SETVIDQ D --L- 1111110 xx L CCCC DDDDDDDDD x11000000 SETPORA D --L- 1111110 xx L CCCC DDDDDDDDD x11000001 SETPORB D --L- 1111110 xx L CCCC DDDDDDDDD x11000010 SETPORC D --L- 1111110 xx L CCCC DDDDDDDDD x11000011 SETPORD D <gap> ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100000 RETA ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100001 RETB ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100010 RETAD ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100011 RETBD ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100100 RETAR ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100101 RETBR ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100110 RETARD ZC-- 1111110 ZC x CCCC xxxxxxxxx x11100111 RETBRD ZC-- 1111110 ZC x CCCC xxxxxxxxx x11101000 TESTSPA ZC-- 1111110 ZC x CCCC xxxxxxxxx x11101001 TESTSPB ZC-- 1111110 ZC x CCCC xxxxxxxxx x11101010 POLCTRA (CTRA rollover into !Z/C) ZC-- 1111110 ZC x CCCC xxxxxxxxx x11101011 POLCTRB (CTRB rollover into !Z/C) ZC-- 1111110 ZC x CCCC xxxxxxxxx x11101100 POLVID (VID ready into !Z/C) ---- 1111110 xx x CCCC xxxxxxxxx x11101101 CAPCTRA ---- 1111110 xx x CCCC xxxxxxxxx x11101110 CAPCTRB ---- 1111110 xx x CCCC xxxxxxxxx x11101111 CAPCTRS ---- 1111110 xx L CCCC xxxxxxxxx x11110000 CACHEX ---- 1111110 xx L CCCC xxxxxxxxx x11110001 CLRACA ---- 1111110 xx L CCCC xxxxxxxxx x11110010 CLRACB ---- 1111110 xx L CCCC xxxxxxxxx x11110011 CLRACS ---- 1111110 xx x CCCC xxxxxxxxx x11110100 SYNCTRA (waits for ctra if single-task, loops if multi-task)) ---- 1111110 xx x CCCC xxxxxxxxx x11110101 SYNCTRB (waits for ctrb if single-task, loops if multi-task)) <gap> ---- 1111111 0n n nnnn nnnnnnnnn nnniiiiii REPS #n,#i ---- 1111111 10 x BBAA DDDDDDDDD SSSSSSSSS SETINDx #D,#S (SETINDA S / SETINDB D / SETINDS D,S) ---- 1111111 11 x 0B0A DDDDDDDDD SSSSSSSSS FIXINDx #D,#S (FIXINDA D,S / FIXINDB D,S / FIXINDS D,S) x = don't care, use 0 ---------------------------------------------------------------------------------------------------------------------------------------------------------------Now I've got to change the Verilog and the assembler in PNUT to reflect this new map. This will take several days.
Can't You attach that list as HELP in PNut?.
That's a good idea. If I forget to do that when the next PNUT comes out, please remind me.
Thanks.
Edit: And for all our sake, get some sleep!
I needed more bits than were available in the %1111110 set. Do you see a better way? I may not be thinking straight.
Those last 3 instructions were real odd-balls, so I put them at the end. Everything before those three is pretty regular. Weirdos to the back of the bus!
Couldn't ESWAP8 also be done with SWBYTES? Would free an instruction there. Could have an alias for ESWAP8 to the appropriate SWBYTES maybe?
Stands not E in ESWAP8 for --- Edian?
Looking at Chip's notes it appears your right Roy. ESWAP8 is now obsolete!
In many PCB I/O layouts it quite common for pins to connected to dual row headers (0.1 inch for example).
Most PCB layouts tend to fan-out the pins so that one side of the connector is odd numbered I/o and the other even.
The F{GA boards are an example of this. P0,P2,P4 on one side and P1,P3,P5 the other.
In a lot of cases it would be nice to use a group of pins on one side of the connector.
My idea is a SPREAD instruction that does the following.
SPREAD D,S
where s = %11001 for example
D would = %0101000001 after
A simple shift could align to odd/even bits or maybe WC could be used to shift left 1 bit optionally.
Basically the 9 bits of an immediate or the lower 16 bits of S are spread over 32 bits
A reverse instruction SQUISH could do the opposite. Every 2nd bit is aligned to create a 16 bit result. WC could be used to grab odd/even bits.
This would simplify/reduce code required to mask/modify IO pins.
I figure it's just a basic MUX function?
Initial observations:
- I am curious about what the 'R' stands for in {RD|WR}AUXR
- I really like the niblle/byte/word moves and endian reversal
I second this suggestion, just so I can use "SQUISH" in my code!
Actually, couldn't you do that with MERGEW and SPLITW?
There's also a CALLAR, CALLBR, CALLARD, and CALLBRD. Since STACK is now AUX, I think the "R" refers to "reverse" (like the old PUSHA[R] and POPA[R]). For the RDAUX/WRAUX operations, I'm guessing that the "R" is only differentiated from the non-"R" version when using SPA/SPB. Going out on a limb, I'm guessing SPA/SPB is used when the MSB of S-field is set (otherwise, it's an absolute offset between 0 and 255). However, why have the separate "R" version in that case? Couldn't the increment/decrement of SPA/SPB be encoded in the lower eight bits (similar to the INDA/INDB encoding)?
Ok. Maybe I should wait until Chip clarifies.
ESWAP8 moves the value from S to D, whereas SWBYTES works on D using S. I'll leave them for now. There are plenty of opportunities for new instruction slots, if we need them.