Note that Microchip does have three wafer fabrication facilities (Chandler and Tempe, Arizona and Gresham, Oregon), but it's also true that you can get cheaper chips without building your own facility.
Microchip has said that that they don't actually build any of their fabs, they buy unwanted ones cheap.
An an observer who hasn't (yet) used the propeller, I have a lot of interest in the P2 due to what I've heard about the ADC capabilities really. Sure, it isn't competitive with the $1 PICs/ARMs in the areas that fit those best, and from what I understand are it's individual ADCs definitely won't be competing with the serious quality ADCs out there, but unless what I've heard is wrong, it sounds like one can run 32 true (no muxing) ADC channels at a time at a reasonably high sampling rate, which is really quite impressive. The only true 32-channel ADC chip on Digikey for instance, is a $120 chip that can only sample at 3kHz-ish (not a totally fair comparison for various reasons, that being a real high quality ADC chip and such... but still, the point is, 32 true ADC channels without muxing is a rare capability)
I think I heard that each cog could service 4 pins as ADCs at a time, without muxing between them at a lower than maximum rate (muxing a delta-sigma bitream I'm guessing?). That's where the 32 I said came from. I'm not 100% sure if my source or memory is reliable though.
Is it only 32 ADC channel? I thought every pin had an ADC... Seems like could have 92 or so ADC...
Every pin has a delta-sigma integrator which can send a stream of bits down its read signal to all the cogs. Any cog's CTR can be used to sum any pin's input stream to generate an A/D conversion value. If you sum 256 clocks' worth, you get an 8-bit sample, and so on. You can put every pin in delta-sigma ADC mode, if you want, and then use any number of cogs' CTRs to sum those bit streams.
Every pin has a delta-sigma integrator which can send a stream of bits down its read signal to all the cogs. Any cog's CTR can be used to sum any pin's input stream to generate an A/D conversion value. If you sum 256 clocks' worth, you get an 8-bit sample, and so on. You can put every pin in delta-sigma ADC mode, if you want, and then use any number of cogs' CTRs to sum those bit streams.
That's pretty nifty, so you can trade off resolution (how many clocks you sum for), sample rate (how often you sample that pin (If you are multiplexing or not on that CTR) and overall ADC pins based on how much resources you want to commit to all this.
Every pin has a delta-sigma integrator which can send a stream of bits down its read signal to all the cogs. Any cog's CTR can be used to sum any pin's input stream to generate an A/D conversion value. If you sum 256 clocks' worth, you get an 8-bit sample, and so on. You can put every pin in delta-sigma ADC mode, if you want, and then use any number of cogs' CTRs to sum those bit streams.
Thanks for clarifying/confirming that Chip.
So I suppose if one were to compare something like, say... the atmega328... the atmega328 has up to 8 pins that can act as analog inputs, but only 1 can be giving you samples at a time. The P2 on the other hand has 92 pins that can act as analog inputs, but how many can be giving you samples at the exact same time is limited by total number of counters in the cogs. Kind of similar effect with the muxing, though a different design philosophy, with the atmega328 muxing a few analog levels to one ADC, versus the P2 muxing numerous delta-sigma bitstreams to the counters.
So I suppose if one were to compare something like, say... the atmega328... the atmega328 has up to 8 pins that can act as analog inputs, but only 1 can be giving you samples at a time. The P2 on the other hand has 92 pins that can act as analog inputs, but how many can be giving you samples at the exact same time is limited by total number of counters in the cogs. Kind of similar effect with the muxing, though a different design philosophy, with the atmega328 muxing a few analog levels to one ADC, versus the P2 muxing numerous delta-sigma bitstreams to the counters.
Each CTR can sum two different streams. With two CTRs per cog, that means each cog can do four simultaneous summations. So, with eight cogs, that makes 32 simultaneous conversions possible. You can steer the CTRs to look at other pins, of course, at the expense of sample rate.
Every pin has a delta-sigma integrator which can send a stream of bits down its read signal to all the cogs. Any cog's CTR can be used to sum any pin's input stream to generate an A/D conversion value. If you sum 256 clocks' worth, you get an 8-bit sample, and so on. You can put every pin in delta-sigma ADC mode, if you want, and then use any number of cogs' CTRs to sum those bit streams.
Some clarify questions - Do you mean this can have
a) The classic D-FF and Q output, for external Analog Sw and external integrator
and/or ?
b) The pin has a true inbuilt analog opamp integrator, which needs a CAP, and a reference voltage.
and/or
c) Pin is like a Prop 1, which uses Logic threshold as reference, and is like a high-gain D-FF and needs a 2nd pin for !Q feedback
What control over the FF clock rate is there ?
( Often you want to scale this down, to match affordable external integrators.)
You can steer the CTRs to look at other pins, of course, at the expense of sample rate.
These are still pin pairs, per ADC right ? so that becomes (allowing 2 pins for talking) 32 readings, from a possible 45 ADC sets.
(Those not being read, are still running in charge balance)
Some clarify questions - Do you mean this can have
a) The classic D-FF and Q output, for external Analog Sw and external integrator
and/or ?
b) The pin has a true inbuilt analog opamp integrator, which needs a CAP, and a reference voltage.
and/or
c) Pin is like a Prop 1, which uses Logic threshold as reference, and is like a high-gain D-FF and needs a 2nd pin for !Q feedback
What control over the FF clock rate is there ?
( Often you want to scale this down, to match affordable external integrators.)
Inside each pin is a complete delta-sigma circuit comprised of a Vsup/2 reference, a fast comparator, precision resistors, a summing cap, precision current sources and low-parasitic current switches for feedback, and a D flip-flop. This forms a complete integrator which is much more accurate than what you wind up with, externally, on a Prop1. The input impedance is several mega-ohms.
When you put a pin into delta-sigma mode, it quickly finds the balance point and issues a perpetual stream of feedback bits, timed to the system clock (normally 160MHz). The ratio of 1's to 0's over any interval is your sample. 1/8th duty is GND and 7/8 duty is Vsup, giving you resolving capability beyond the rails (about 0.4V's worth, before the pin's catch diodes turn on). There are also calibration switches to determine what GND and Vsup actually measure.
To do lots of channels of A/D, put any number of pins into ADC mode and then sum each bit stream using the CTR(s).
Inside each pin is a complete delta-sigma circuit comprised of a Vsup/2 reference, a fast comparator, precision resistors, a summing cap, precision current sources and low-parasitic current switches for feedback, and a D flip-flop. This forms a complete integrator which is much more accurate than what you wind up with, externally, on a Prop1. The input impedance is several mega-ohms.
When you put a pin into delta-sigma mode, it quickly finds the balance point and issues a perpetual stream of feedback bits, timed to the system clock (normally 160MHz). The ratio of 1's to 0's over any interval is your sample. 1/8th duty is GND and 7/8 duty is Vsup, giving you resolving capability beyond the rails (about 0.4V's worth, before the pin's catch diodes turn on). There are also calibration switches to determine what GND and Vsup actually measure.
To do lots of channels of A/D, put any number of pins into ADC mode and then sum each bit stream using the CTR(s).
Very interested to see the final performance numbers on that.
Did that cell make it onto any of your test silicon ?
Do we need a new thread for "Prop 2 Testing Progress Reports" ?
When you put a pin into delta-sigma mode, it quickly finds the balance point and issues a perpetual stream of feedback bits, timed to the system clock (normally 160MHz).
So you could run 90 pins as tracking ADC, and read-from any 32 of those. (use 2 for IO)
Is that 160MHz separately adjustable, and what is the projected current consumption budget of each pin in this mode ?
Very interested to see the final performance numbers on that.
Did that cell make it onto any of your test silicon ?
Do we need a new thread for "Prop 2 Testing Progress Reports" ?
We had the pin circuit in our test chip a few years ago, but I didn't try to learn its accuracy because we had huge ground-bounce issues due to the power wiring inside the chip. I'm thinking it's going to be a lot more easy to play with in the actual chip.
A thread like that will be useful when we get chips sent out to people.
So you could run 90 pins as tracking ADC, and read-from any 32 of those. (use 2 for IO)
Is that 160MHz separately adjustable, and what is the projected current consumption budget of each pin in this mode ?
That's right.
The bit rate is whatever the clock rate is for the chip. The current consumption, if I recall, is around 500uA @160MHz per integrator (pin).
Do you have packaged chips in internal testing yet ? Does it have a pulse ?
Internal testing will consist of David Carrier soldering a few chips onto some SMT breakout boards, hoping that if the design is good, at least one of those parts will show signs of life. If the monitor comes up, we're over a huge hurdle. If not, we will have to deduce what is wrong, somehow.
Can an integrator output be read like a normal i/o pin? Or does its output have to feed into a counter for accumulation?
If you can read the integrator output with a single instruction you could probably add up to another 32 ADC channels to the 32 being accumulated by counters in the background, by using a tight foreground REPS loop (it could grab say 4 integrator states {corresponding to say P0 P8 P16 P24}, and accumulate into 4 individual bytes inside of a long, for instance). You could time slice if you didn't want to tie up 8 cogs at 160 MHz
Can an integrator output be read like a normal i/o pin? Or does its output have to feed into a counter for accumulation?
If you can read the integrator output with a single instruction you could probably add up to another 32 ADC channels to the 32 being accumulated by counters in the background, by using a tight foreground REPS loop (it could grab say 4 integrator states {corresponding to say P0 P8 P16 P24}, and accumulate into 4 individual bytes inside of a long, for instance). You could time slice if you didn't want to tie up 8 cogs at 160 MHz
The integrators read like normal pins, but on every clock cycle there is new data. You could do what you are saying, but P0/P8/P16/P24 would have to be the only potentially-high pins.
Are we there yet?. Are we there yet? Are we there yet?. Are we there yet?
I think the wafers are back but they're out for packaging. Until the packaged parts are delivered to Parallax, the testing can't begin. We have to be patient. :-)
Inside each pin is a complete delta-sigma circuit comprised of a Vsup/2 reference, a fast comparator, precision resistors, a summing cap, precision current sources and low-parasitic current switches for feedback, and a D flip-flop. This forms a complete integrator which is much more accurate than what you wind up with, externally, on a Prop1. The input impedance is several mega-ohms.
When you put a pin into delta-sigma mode, it quickly finds the balance point and issues a perpetual stream of feedback bits, timed to the system clock (normally 160MHz). The ratio of 1's to 0's over any interval is your sample. 1/8th duty is GND and 7/8 duty is Vsup, giving you resolving capability beyond the rails (about 0.4V's worth, before the pin's catch diodes turn on). There are also calibration switches to determine what GND and Vsup actually measure.
I was thinking of pairing the P2 up with this thermocouple (http://www.adafruit.com/products/270). From what I've read, this thing outputs ~50uV/C (adafruit recommends using an amplifier). Given the temperature range, I should only see between 0 and 20mV. So, if I were to sample approximately every 50000 clocks (e.g. at about 3KHz), I should be able to get at least that much resolution?
Also, in order to know how many actual clock cycles have passed, I assume it's left up to the programmer to keep track (e.g. use system counter, free running CTR, etc.)?
It's a little late but we've gotten custom sockets built by Aries (http://www.arieselec.com/) for low pin count (36-64 pins) WLBGAs and fpBGAs for about $400 each, and TTS (http://tts-grp.com/) for about 3X that. If you're using a standard package, then maybe one of them has an off-the-shelf product that would work.
Every pin has a delta-sigma integrator which can send a stream of bits down its read signal to all the cogs. Any cog's CTR can be used to sum any pin's input stream to generate an A/D conversion value. If you sum 256 clocks' worth, you get an 8-bit sample, and so on. You can put every pin in delta-sigma ADC mode, if you want, and then use any number of cogs' CTRs to sum those bit streams.
I never grokked the math with 1-bit converters. Is this a generic mechanism in terms of the ratio-metric handling?
The MDAT %-Hi is counter-ready, but it is designed for MDAT=CLKEN and MCLKOUT=CLK
ie Ideally, it would use 2 pins, and also clock the counter from the MCLKOUT
- not sure if P2 counters have external CLK and CLKEN ? (I know it was requested by many )
As a compromise, you could feed MDAT only as CLKEN, but now skews in rise/fall and async sampling aperture effects affect the numbers.
That AD7400 is a 2nd-order delta-sigma modulator which requires a complicated digital filter after it to produce 16-bit samples.
The Prop2 has simple 1st-order delta-sigma modulators which output 0's and 1's in proportion to the input signal level. for example, a Vsup/2 level would produce the stream: %01010101010101.... which is 1/2. A GND level would produce %000000010000000100000001... which is 1/8. A Vsup level would produce %111111101111111011111110... which is 7/8. So, you only need to count 1's over some number of clocks to get a sample. If you count for 256 clocks, you'll get an 8-bit quality sample ranging from 0 to 256. If the input is between GND and Vsup (1/8 and 7/8), you'll get values from 32 to 224.
Comments
Microchip has said that that they don't actually build any of their fabs, they buy unwanted ones cheap.
Every pin has a delta-sigma integrator which can send a stream of bits down its read signal to all the cogs. Any cog's CTR can be used to sum any pin's input stream to generate an A/D conversion value. If you sum 256 clocks' worth, you get an 8-bit sample, and so on. You can put every pin in delta-sigma ADC mode, if you want, and then use any number of cogs' CTRs to sum those bit streams.
That's pretty nifty, so you can trade off resolution (how many clocks you sum for), sample rate (how often you sample that pin (If you are multiplexing or not on that CTR) and overall ADC pins based on how much resources you want to commit to all this.
Wow!
Thanks for clarifying/confirming that Chip.
So I suppose if one were to compare something like, say... the atmega328... the atmega328 has up to 8 pins that can act as analog inputs, but only 1 can be giving you samples at a time. The P2 on the other hand has 92 pins that can act as analog inputs, but how many can be giving you samples at the exact same time is limited by total number of counters in the cogs. Kind of similar effect with the muxing, though a different design philosophy, with the atmega328 muxing a few analog levels to one ADC, versus the P2 muxing numerous delta-sigma bitstreams to the counters.
Each CTR can sum two different streams. With two CTRs per cog, that means each cog can do four simultaneous summations. So, with eight cogs, that makes 32 simultaneous conversions possible. You can steer the CTRs to look at other pins, of course, at the expense of sample rate.
Some clarify questions - Do you mean this can have
a) The classic D-FF and Q output, for external Analog Sw and external integrator
and/or ?
b) The pin has a true inbuilt analog opamp integrator, which needs a CAP, and a reference voltage.
and/or
c) Pin is like a Prop 1, which uses Logic threshold as reference, and is like a high-gain D-FF and needs a 2nd pin for !Q feedback
What control over the FF clock rate is there ?
( Often you want to scale this down, to match affordable external integrators.)
These are still pin pairs, per ADC right ? so that becomes (allowing 2 pins for talking) 32 readings, from a possible 45 ADC sets.
(Those not being read, are still running in charge balance)
Inside each pin is a complete delta-sigma circuit comprised of a Vsup/2 reference, a fast comparator, precision resistors, a summing cap, precision current sources and low-parasitic current switches for feedback, and a D flip-flop. This forms a complete integrator which is much more accurate than what you wind up with, externally, on a Prop1. The input impedance is several mega-ohms.
When you put a pin into delta-sigma mode, it quickly finds the balance point and issues a perpetual stream of feedback bits, timed to the system clock (normally 160MHz). The ratio of 1's to 0's over any interval is your sample. 1/8th duty is GND and 7/8 duty is Vsup, giving you resolving capability beyond the rails (about 0.4V's worth, before the pin's catch diodes turn on). There are also calibration switches to determine what GND and Vsup actually measure.
To do lots of channels of A/D, put any number of pins into ADC mode and then sum each bit stream using the CTR(s).
Very interested to see the final performance numbers on that.
Did that cell make it onto any of your test silicon ?
Do we need a new thread for "Prop 2 Testing Progress Reports" ?
So you could run 90 pins as tracking ADC, and read-from any 32 of those. (use 2 for IO)
Is that 160MHz separately adjustable, and what is the projected current consumption budget of each pin in this mode ?
We had the pin circuit in our test chip a few years ago, but I didn't try to learn its accuracy because we had huge ground-bounce issues due to the power wiring inside the chip. I'm thinking it's going to be a lot more easy to play with in the actual chip.
A thread like that will be useful when we get chips sent out to people.
Do you have packaged chips in internal testing yet ? Does it have a pulse ?
That's right.
The bit rate is whatever the clock rate is for the chip. The current consumption, if I recall, is around 500uA @160MHz per integrator (pin).
Internal testing will consist of David Carrier soldering a few chips onto some SMT breakout boards, hoping that if the design is good, at least one of those parts will show signs of life. If the monitor comes up, we're over a huge hurdle. If not, we will have to deduce what is wrong, somehow.
http://www.ironwoodelectronics.com/press/spring_pin_socket_exposed.cfm
Not cheap, but a very fast way to check many devices...
Adit:
this is less eye watering
http://www.xeltek.com/adapter/detail.php?id=EX3055&productid=17996
and a surprising range here, some ~ $100
http://www.aliexpress.com/wholesale/wholesale-tqfp128-socket.html
Yowza!: Pricing for the SS-QFE128SD-01 is $1916 at qty 1 with reduced pricing available depending on quantity required.
$400 for the other one is more reasonable for what we need. Thanks for finding these.
Hehe, so you are not going to order a dozen ?
the latest link I added seems to even come down to US $106.70 / OTQ-128-0.4
for an open-top model.
Emulation Technology S-QFP-00-128-E
Only $228, but not in stock, in the past they could usually get one in a week or 2
Are we there yet?. Are we there yet? Are we there yet?. Are we there yet?
If you can read the integrator output with a single instruction you could probably add up to another 32 ADC channels to the 32 being accumulated by counters in the background, by using a tight foreground REPS loop (it could grab say 4 integrator states {corresponding to say P0 P8 P16 P24}, and accumulate into 4 individual bytes inside of a long, for instance). You could time slice if you didn't want to tie up 8 cogs at 160 MHz
The integrators read like normal pins, but on every clock cycle there is new data. You could do what you are saying, but P0/P8/P16/P24 would have to be the only potentially-high pins.
I was thinking of pairing the P2 up with this thermocouple (http://www.adafruit.com/products/270). From what I've read, this thing outputs ~50uV/C (adafruit recommends using an amplifier). Given the temperature range, I should only see between 0 and 20mV. So, if I were to sample approximately every 50000 clocks (e.g. at about 3KHz), I should be able to get at least that much resolution?
Also, in order to know how many actual clock cycles have passed, I assume it's left up to the programmer to keep track (e.g. use system counter, free running CTR, etc.)?
I never grokked the math with 1-bit converters. Is this a generic mechanism in terms of the ratio-metric handling?
For example, ignoring the clocking issues for a moment, what if I attached something like this to a Prop2 counter - http://www.analog.com/en/analog-to-digital-converters/isolated-ad-converters/ad7400/products/product.html
Does the data format itself suit?
The MDAT %-Hi is counter-ready, but it is designed for MDAT=CLKEN and MCLKOUT=CLK
ie Ideally, it would use 2 pins, and also clock the counter from the MCLKOUT
- not sure if P2 counters have external CLK and CLKEN ? (I know it was requested by many )
As a compromise, you could feed MDAT only as CLKEN, but now skews in rise/fall and async sampling aperture effects affect the numbers.
That AD7400 is a 2nd-order delta-sigma modulator which requires a complicated digital filter after it to produce 16-bit samples.
The Prop2 has simple 1st-order delta-sigma modulators which output 0's and 1's in proportion to the input signal level. for example, a Vsup/2 level would produce the stream: %01010101010101.... which is 1/2. A GND level would produce %000000010000000100000001... which is 1/8. A Vsup level would produce %111111101111111011111110... which is 7/8. So, you only need to count 1's over some number of clocks to get a sample. If you count for 256 clocks, you'll get an 8-bit quality sample ranging from 0 to 256. If the input is between GND and Vsup (1/8 and 7/8), you'll get values from 32 to 224.