That's the same as the SSD1963 chip I use for graphics... It's difficult to solder by hand, but not impossible. I got right on the third try.
(ruined the first 2 chips though).
It's acceptably difficult when you have a solder stencil. But, I often need manual clean up with solder wick...
Here's hoping it's not 0.4mm pitch. I find 0.65mm pitch quite tight but I can manage it. Not really looking forward to 0.5mm or 0.4mm
I best get my oven working!
I asked above. Perhaps you did not see it. How is the SD boot code going?
My preference is to read a 4K block (same specs as the Flash initial boot block)
1. The specific 16 bytes from $1A0 on the MBR (sector 0) would contain...
Master Boot Record (Sector #0 of SD Card)
Offset $1A0...
xx xx xx xx '[URL="file://\\ 4"]\\ 4[/URL] bytes of identifier (these 8 bytes can be the P2's part no with the last byte being say $A5)
xx xx xx xx '// 4 bytes of identifier
ss ss ss ss ' 4 byte sector no. where the 4KB block of boot code will be found
zz zz zz zz ' 4 byte (optional second sector no. or alternately length or anything else that the 4KB boot block may require)
The 4KB block can be anywhere on the SD card. It can be the data in a file within a FAT system or any other file system. It can be the start of a partitions data. Simply put, it does not matter and is oblivious to any card formatting - this provides the most flexibility.
This 4KB block, if required, will have the appropriate hash for security.
This 4KB block will have sufficient code space to enable further booting. This code will decide if it is to take more code following the 4KB block on the SD card, or whether it is to use the second 4 zz zz zz zz bytes from the SD card as another sector base location. This is immaterial to the whole mechanism. It is totally under the users control, depending on the code within the original 4KB boot block.
To me, this is the simplest, minimal, and with virtually no risk to predefined formatting possible.
I'm just finishing the monitor program, so I haven't gotten into the SD issue yet. Our synthesis work should be done on 10/15/12, so we still have a month to finish the ROM code.
The TQFP-128 has a 14x14mm body and 0.4mm pin pitch.
I'm just finishing the monitor program, so I haven't gotten into the SD issue yet. Our synthesis work should be done on 10/15/12, so we still have a month to finish the ROM code.
The TQFP-128 has a 14x14mm body and 0.4mm pin pitch.
I'm just finishing the monitor program, so I haven't gotten into the SD issue yet. Our synthesis work should be done on 10/15/12, so we still have a month to finish the ROM code.
The TQFP-128 has a 14x14mm body and 0.4mm pin pitch.
That's a long time. From what I learned in school, synthesis is inherently non-parallelizable. So, I wonder about chips that are much larger (Intel). Surely they can't take years to synthesize? And that's assuming it's O(n), not O(n^2) or something.
Maybe they synthesize sections of the core, instead of everything at once. It might be less efficient in terms of die usage, but it could the be parallelized.
That's a long time. From what I learned in school, synthesis is inherently non-parallelizable. So, I wonder about chips that are much larger (Intel). Surely they can't take years to synthesize? And that's assuming it's O(n), not O(n^2) or something.
Maybe they synthesize sections of the core, instead of everything at once. It might be less efficient in terms of die usage, but it could the be parallelized.
It actually only takes 2-3 hours to do a synthesis run and another couple of hours to do a detailed route, but after that, there is a lot of post-layout work to be commandeered through scripts which must be developed. That's what's going on now.
I'm just finishing the monitor program, so I haven't gotten into the SD issue yet. Our synthesis work should be done on 10/15/12, so we still have a month to finish the ROM code.
The TQFP-128 has a 14x14mm body and 0.4mm pin pitch.
Thanks Chip.
A toaster oven is going to be required for this fine pitch - ouch.
I think Spaieha is asking, is there a centre ground pad underneath the TQFP-128 ?
At this time, we are planning on NO center pad. It would be good to have one, but our die is too big for the package with center pad that our packager has shown us.
After working with that package a bit, it could be that it really doesn't need that center pad...
There are so many pins on each side with so little space between them, that it's almost as if the sides are all metal.
That makes it a very good heat sink.
Trying to remove the chip from a board with a hot air gun actually takes a lot of work...
Directly dealing with .4mm and home equipment is a challenge. Due to some past troubles using a 100pin .4mm package, I have considered building something like these.
where the pads would wrap around the edge of the board.
The only way to do it consistently in my experience is to use a metal stencil. Running a solder paste strip leaves too much residue, under magnification it looks like big bbs, and it only takes a few to bridge a .4mm gap. A flood and suck type hand solder works ok, but its still a challenge.
I'll probably go down in flames for this, but a 64 pin device with a larger pad spacing would be nice, even if the internal io wasn't connected. It could be the same core, perhaps?
I'll probably go down in flames for this, but a 64 pin device with a larger pad spacing would be nice, even if the internal io wasn't connected. It could be the same core, perhaps?
Actually not a dumb idea at all, and I've seen Renesas offer multiple package pitch.
In the Prop the Die sets the package size, and Vcc/GND would need bonding, but there is a 14mm package 64 pins at 0.8mm
If you bonded very second IO (minus some) then BYTE IO could get tricky, and Video modes could presume adjacent-pins.
Boot pins would of course all need bonding... so it may depend in the Physical bonding, and the practical pin-maps co-operate to allow a workable end result.
At this time, we are planning on NO center pad. It would be good to have one, but our die is too big for the package with center pad that our packager has shown us.
Given the frequency and Icc, a center pad certainly would be good to have.
I have seen some packages with a slightly smaller center pad, that allows vias between the pins, and the PAD.
Some have much smaller exposed centre pads, so I'm not sure the exposed PAD has to be larger than the die ?
(eg XMOS show a QFN one with a 2.8mm PAD, and a TQFP one with 4.8mm Pad )
Directly dealing with .4mm and home equipment is a challenge. Due to some past troubles using a 100pin .4mm package, I have considered building something like these.... where the pads would wrap around the edge of the board.
.
I see you can also get PinGrid type adaptors, for bread-board 0.1" pitch work :
A 1mm-pitch BGA-128 would probably actually be nice to work with. Would that be a possibility?
Only possible if the die size is smaller which I very much doubt. Plus BGA in anything more than low density pin count is a royal pain to assemble but also requires multi-layer pcbs, another royal pain.
At this time, we are planning on NO center pad. It would be good to have one, but our die is too big for the package with center pad that our packager has shown us.
Center pads on fine pitch TQFP is another royal pain as this almost forces the pcb designer to multi-layer and very small vias seeing the inside of the pin pad is basically unavailable. It's a pity they can't do a version with a small center pad however. At this present moment I would like to see the P2 as it is now and worry about more specialized packages later on if the demand is there. Going any further than a 128 pin 0.4mm pitch TQFP is going to limit the number of designs that are produced and unnecessarily hamper uptake of the chip in new board designs.
At this time, we are planning on NO center pad. It would be good to have one, but our die is too big for the package with center pad that our packager has shown us.
I don't asked this question -- For at I will have that one.
Only to be sure I use correct Footprint on my PCB.
Top parts on PCB in picture are not definitive AS it is still to little information how BOOT system will use pin's.
I still don't have placed any boot Flash / EEProm - as that is un-know to.
As You can see I have place for any type of Footprint so no problems for me.
As I pointed before it is Experimenters PCB -- It is why it is that minimal in design and have only parts needed for Turbo-Propeller to function correctly and give possibility to use most already available modules form Propeller I.with 10 pin's subsystem from ProtoBoard -- I have 10+1 pin's that pin 11 are 5V to some modules that need it.
Ps. to them that will build theirs own PCB's. --- This pin spacing need usage of 6 mils trace with.
Could this be offered by Parallax in a version where the P2 is already soldered to a tiny PCB that uses .65 pitch 'legs' or pads simulating an SSOP? A DIP is to big, but some option would be nice.
I'm not sure a breakout board would be a big seller, but who knows... It would be nice to have a small board with boot flash, big SDRAM, vga connector, and SD card though...
Who says that's impossible? So it bulges in one part. No worries. Just make it a bit taller and have the pins go underneath. Big fan of the DIP format here.
If You can find SMT mounted DIL40 pins --- That can be possible --- (MAYBE).
You need count about 15 caps that need be mounted near Voltage pins --- Usualy most of them on bottom side of Propeller IC.
That give You not much space for traces needed for SDRAM and traces to DIL40 pin's header connector.
To that You need place at least one V-Regulator for 1.8V for CPU core.
Who says that's impossible? So it bulges in one part. No worries. Just make it a bit taller and have the pins go underneath. Big fan of
the DIP format here.
OK, I'll accept that a DIP format is impossible. Instead of of DIP format, would it be possible to put a crystall, Prop2, power regulators, flash and SDRAM on a small board with dual rows of inline pins, with each row on either side of the board instead?
EDIT: Looks like I was a little slow in responding. Maybe my use of the term DIP was confusing. I probably should have said DIL instead. Oh, and the spacing between the two rows doesn't have to be 0.6 inches, or whatever the DIP spacing implied. It can be whatever multiple of 0.1" will accomodate the Prop2.
Comments
(ruined the first 2 chips though).
It's acceptably difficult when you have a solder stencil. But, I often need manual clean up with solder wick...
I best get my oven working!
I asked above. Perhaps you did not see it. How is the SD boot code going?
My preference is to read a 4K block (same specs as the Flash initial boot block)
1. The specific 16 bytes from $1A0 on the MBR (sector 0) would contain...
The 4KB block can be anywhere on the SD card. It can be the data in a file within a FAT system or any other file system. It can be the start of a partitions data. Simply put, it does not matter and is oblivious to any card formatting - this provides the most flexibility.
This 4KB block, if required, will have the appropriate hash for security.
This 4KB block will have sufficient code space to enable further booting. This code will decide if it is to take more code following the 4KB block on the SD card, or whether it is to use the second 4 zz zz zz zz bytes from the SD card as another sector base location. This is immaterial to the whole mechanism. It is totally under the users control, depending on the code within the original 4KB boot block.
To me, this is the simplest, minimal, and with virtually no risk to predefined formatting possible.
For reference, here it the testing thread link http://forums.parallax.com/showthread.php?141952-SD-Card-Test-(Please-test-may-be-used-for-boot-code-for-the-Prop2)/page3
I'm just finishing the monitor program, so I haven't gotten into the SD issue yet. Our synthesis work should be done on 10/15/12, so we still have a month to finish the ROM code.
The TQFP-128 has a 14x14mm body and 0.4mm pin pitch.
With else without --- CenterPad
Look on picture attached.
That's a long time. From what I learned in school, synthesis is inherently non-parallelizable. So, I wonder about chips that are much larger (Intel). Surely they can't take years to synthesize? And that's assuming it's O(n), not O(n^2) or something.
Maybe they synthesize sections of the core, instead of everything at once. It might be less efficient in terms of die usage, but it could the be parallelized.
It actually only takes 2-3 hours to do a synthesis run and another couple of hours to do a detailed route, but after that, there is a lot of post-layout work to be commandeered through scripts which must be developed. That's what's going on now.
Thanks Chip.
A toaster oven is going to be required for this fine pitch - ouch.
I think Spaieha is asking, is there a centre ground pad underneath the TQFP-128 ?
At this time, we are planning on NO center pad. It would be good to have one, but our die is too big for the package with center pad that our packager has shown us.
There are so many pins on each side with so little space between them, that it's almost as if the sides are all metal.
That makes it a very good heat sink.
Trying to remove the chip from a board with a hot air gun actually takes a lot of work...
The only way to do it consistently in my experience is to use a metal stencil. Running a solder paste strip leaves too much residue, under magnification it looks like big bbs, and it only takes a few to bridge a .4mm gap. A flood and suck type hand solder works ok, but its still a challenge.
Actually not a dumb idea at all, and I've seen Renesas offer multiple package pitch.
In the Prop the Die sets the package size, and Vcc/GND would need bonding, but there is a 14mm package 64 pins at 0.8mm
If you bonded very second IO (minus some) then BYTE IO could get tricky, and Video modes could presume adjacent-pins.
Boot pins would of course all need bonding... so it may depend in the Physical bonding, and the practical pin-maps co-operate to allow a workable end result.
Example of Renesas - notice the Package size and pitch is nicely part of the Selection, not buried 4 layers deep.
http://am.renesas.com/products/mpumcu/rx/rx200/rx210/index.jsp
Here they have 64p and 80p, in a choice of pitch
Given the frequency and Icc, a center pad certainly would be good to have.
I have seen some packages with a slightly smaller center pad, that allows vias between the pins, and the PAD.
Some have much smaller exposed centre pads, so I'm not sure the exposed PAD has to be larger than the die ?
(eg XMOS show a QFN one with a 2.8mm PAD, and a TQFP one with 4.8mm Pad )
I see you can also get PinGrid type adaptors, for bread-board 0.1" pitch work :
http://www.aprilog.com/Breadboarding-adapters-QFP-TQFP.htm
perhaps a variant on that with mounted decoupling caps ?
Center pads on fine pitch TQFP is another royal pain as this almost forces the pcb designer to multi-layer and very small vias seeing the inside of the pin pad is basically unavailable. It's a pity they can't do a version with a small center pad however. At this present moment I would like to see the P2 as it is now and worry about more specialized packages later on if the demand is there. Going any further than a 128 pin 0.4mm pitch TQFP is going to limit the number of designs that are produced and unnecessarily hamper uptake of the chip in new board designs.
They do, see #1306
Drawings of some are here
https://www.xmos.com/download/public/Device-Package-User-Guide%28X4979D%29.pdf
I don't asked this question -- For at I will have that one.
Only to be sure I use correct Footprint on my PCB.
Top parts on PCB in picture are not definitive AS it is still to little information how BOOT system will use pin's.
I still don't have placed any boot Flash / EEProm - as that is un-know to.
As You can see I have place for any type of Footprint so no problems for me.
As I pointed before it is Experimenters PCB -- It is why it is that minimal in design and have only parts needed for Turbo-Propeller to function correctly and give possibility to use most already available modules form Propeller I.with 10 pin's subsystem from ProtoBoard -- I have 10+1 pin's that pin 11 are 5V to some modules that need it.
Ps. to them that will build theirs own PCB's. --- This pin spacing need usage of 6 mils trace with.
Let me add USB host connectors to that list...
As You can see it is physics impossible.
So forget that.
If You can find SMT mounted DIL40 pins --- That can be possible --- (MAYBE).
You need count about 15 caps that need be mounted near Voltage pins --- Usualy most of them on bottom side of Propeller IC.
That give You not much space for traces needed for SDRAM and traces to DIL40 pin's header connector.
To that You need place at least one V-Regulator for 1.8V for CPU core.
So how big that PCB need be to suit that ??
No VGA connector, but check out this FPGA board(the photos are at the bottom):
http://www.xess.com/prods/prod048.php
So it is possible as long as one doesn't try to hang off a bunch of connectors. Just build a expansion board for those.
EDIT: Looks like I was a little slow in responding. Maybe my use of the term DIP was confusing. I probably should have said DIL instead. Oh, and the spacing between the two rows doesn't have to be 0.6 inches, or whatever the DIP spacing implied. It can be whatever multiple of 0.1" will accomodate the Prop2.