That's an actual count... as part of the DRC (Design Rule Check) there is a rule that checks for any occurrence of poly crossing diffusion(a transistor), while it negates capacitors. (Capacitors are also formed from poly crossing diffusion, however the Source and Drain are shorted forming a single terminal, the other capacitor terminal is the Gate connection into the would-be transistor) .. and those were the reported numbers after negating the capacitors.
"I would expect the outer to have more area ... include R/C/ESD/IO/PSUrIng etc" - It does have more area, but you forget all of the analog ADC and DAC control that goes into each I/O. Only the power and ground pins are 'DUMB' with just ESD protection. All of the other I/O's have ESD protection plus all of the DAC and ADC circuitry. The 4 specialized pins reserved for BOE (Brownout enable), RES(Reset), and two for the Crystal (XI and XO) dont have the ADC or DAC, but thay do have some PLL and RC circuitry. By far the I/O's have the most transistors... I'd tell you, but the computer that I would have access to finding out the transistor count of just one I/O is currently busy.
EDIT - The memories were also inclusive of the outer core transistors which take up a huge chunk... I'll find out the actual numbers for each I/O, but off the top of my head I want to say it's close to 6 thousand for each I/O
I'd tell you, but the computer that I would have access to finding out the transistor count of just one I/O is currently busy.
A rough calc gives in the region of 100,000 transistors/pin (outer resource/96, rounded down), which is some impressive 'Smart IO'
Users will always pay for smart IO.
The first computer I ever bought was an Atari ST whose 68000 processor which had about 70000 transistors. The Prop II has 220 times more than that . The first microprocessors I designed with had less than half of that.
I apologize if this has been answered before - couldn't find any reference to it though.
Will the Prop2 provide some low-level USB primitives that would enable easier and more comprehensive USB Host and USB Device software emulation?
Micah Dowty has managed to push Prop1 into emulating USB Host with her usb-fs-host.spin, but she had to discard every other packet ("deferred ACK" scheme: sending ACK on the second retry only) thus effectively halving the throughput. From my reading of the comments in the source code (usb-fs-host.spin: Theory of Operation:98, ReadDataIN():1068 and NRZI Decoder/Bit un-stuffer:1896) the reason is that Prop1 is not being fast enough to decode USB bit stream (NRZI decoding plus bit unstuffing (removing extra bits)) and calculate CRC in order to send response (ACK or NAK) in time.
It would be great if Prop2 could do low-level USB operations in hardware (NRZI encoding/decoding, bit stuffing/unstuffing, CRC calculation and low level handshake).
Here are few references to Micah Dowty's USB host implementation for Prop1:
Will the Prop2 provide some low-level USB primitives that would enable easier and more comprehensive USB Host and USB Device software emulation?
Micah Dowty has managed to push Prop1 into emulating USB Host with her usb-fs-host.spin, but she had to discard every other packet ("deferred ACK" scheme: sending ACK on the second retry only) thus effectively halving the throughput.
If that otherwise works transparently OK, halving the thruput is still workable, at 12Mb - 6Mb is still fine for many apps.
I see mention of 4 COGS, but not of if that was time, or code limited ?
The Prop 2 has hard time slicing, and is 8x faster, so provided code size is ok, this could maybe even go into 1 COG ?
I apologize if this has been answered before - couldn't find any reference to it though.
Will the Prop2 provide some low-level USB primitives that would enable easier and more comprehensive USB Host and USB Device software emulation?
Micah Dowty has managed to push Prop1 into emulating USB Host with her usb-fs-host.spin, but she had to discard every other packet ("deferred ACK" scheme: sending ACK on the second retry only) thus effectively halving the throughput. From my reading of the comments in the source code (usb-fs-host.spin: Theory of Operation:98, ReadDataIN():1068 and NRZI Decoder/Bit un-stuffer:1896) the reason is that Prop1 is not being fast enough to decode USB bit stream (NRZI decoding plus bit unstuffing (removing extra bits)) and calculate CRC in order to send response (ACK or NAK) in time.
It would be great if Prop2 could do low-level USB operations in hardware (NRZI encoding/decoding, bit stuffing/unstuffing, CRC calculation and low level handshake).
Here are few references to Micah Dowty's USB host implementation for Prop1:
The Prop2 has some hardware at the I/O pins for USB (a switchable 1.5k Pullup and a differential input), so yes it is designed to do USB fullspeed (not high speed) in software. Micah needs 3 cogs for in- and output only because of speed. On Prop2 all should be possible with one cog.
The bad thing ist that there is no USB software in the ROM, otherwise you could program the Prop 2 directly over USB without an USB to Serial converter.
How did you go with the SD boot code?
Do you still need help?
My apologies... I have been tied up with other work and have while I have checked ocasionally, I have not had the time to post anything in the last few weeks.
I'm designing a P2 PCB based on the preliminary pinout and the information I'm aware of. This will basically have all the peripherals to host a stand-alone system. Network connectivity may be via a standard WiFi module or even USB. There will be some breadboarding area although I prefer to host the breadboarding on replaceable modules which also include common SMD footprints. These boards will be ready and made up this year in anticipation of the P2 release (not saying when I think that is) while I also complete my Tachyon system to a full stand-alone self-hosting system. The board and connectors are designed to fit into an enclosure with the connectors arranged in a usable fashion (not RPi fashion). The PASM kernel will be fairly easy to rewrite to get it running on the P2 after which I can play with optimizations and explore the P2 architecture interactively.
What I need to know is which 128-pin package the P2 will be supplied in? (thread tools are a bit lacking on such a long thread for me to find out more)
Experimenters version with all pin's drawn to 10 pin's headers in groups of 8 bit's. That connectors are compatible with -- Propeller I -- ProtoBoard -- +V, GND, and 0 to 7 - IO bits group.
Only active parts on PCB are V-Regulators.
Ps. to ALL that made theirs own PCB's to Propeller II
Decoupling Capacitors and theirs placement are very important.
What is suggested --- AND what will be used --- Can be big difference. It is why we need correct info.
Made any PCB that have that incorrect -- Is not so funny.
Comments
That's an actual count... as part of the DRC (Design Rule Check) there is a rule that checks for any occurrence of poly crossing diffusion(a transistor), while it negates capacitors. (Capacitors are also formed from poly crossing diffusion, however the Source and Drain are shorted forming a single terminal, the other capacitor terminal is the Gate connection into the would-be transistor) .. and those were the reported numbers after negating the capacitors.
"I would expect the outer to have more area ... include R/C/ESD/IO/PSUrIng etc" - It does have more area, but you forget all of the analog ADC and DAC control that goes into each I/O. Only the power and ground pins are 'DUMB' with just ESD protection. All of the other I/O's have ESD protection plus all of the DAC and ADC circuitry. The 4 specialized pins reserved for BOE (Brownout enable), RES(Reset), and two for the Crystal (XI and XO) dont have the ADC or DAC, but thay do have some PLL and RC circuitry. By far the I/O's have the most transistors... I'd tell you, but the computer that I would have access to finding out the transistor count of just one I/O is currently busy.
EDIT - The memories were also inclusive of the outer core transistors which take up a huge chunk... I'll find out the actual numbers for each I/O, but off the top of my head I want to say it's close to 6 thousand for each I/O
I was just about to ask about the transistor count per pin, it will be interesting to know
A rough calc gives in the region of 100,000 transistors/pin (outer resource/96, rounded down), which is some impressive 'Smart IO'
Users will always pay for smart IO.
Read my Edit, it's going to be closer to 6k transistors per I/O
These are just rough numbers....
6k per I/O x 92 I/O's = 552k
10771k - 552k = 10219k
There are 20 memory structures ... 10219k / 20 is about 511k per memory structure
Ah, I see you have Memories in the outside basket - that makes much more sense.
Is that COG memory too, or just Main memory ?
We're looking at an equivalent of an Intel 8085 *per pin*
And overall about 65% more transistors than the Pentium III, or about 1/3 of an Atom processor.
What a beast.
More like an Intel 486 ... remember divide by eight to compare apples to apples :-)
So you mean 8 x "486" on a pure count basis (ignoring process and clock )
WOW! Beastly indeed!
So that's roughly 'an intel 8085 per pin' ...
I wonder if I will be able to run Age of Empires on the new Propeller?
Whiper snapper.
The first computer I ever bought was an Atari ST whose 68000 processor which had about 70000 transistors. The Prop II has 220 times more than that . The first microprocessors I designed with had less than half of that.
Uh, no, You most definitely cannot say that you are old yet. You've got about 20 years at least to go.
Because if you are old, then what am I, or anyone else born before an american set foot on the Moon?
Will the Prop2 provide some low-level USB primitives that would enable easier and more comprehensive USB Host and USB Device software emulation?
Micah Dowty has managed to push Prop1 into emulating USB Host with her usb-fs-host.spin, but she had to discard every other packet ("deferred ACK" scheme: sending ACK on the second retry only) thus effectively halving the throughput. From my reading of the comments in the source code (usb-fs-host.spin: Theory of Operation:98, ReadDataIN():1068 and NRZI Decoder/Bit un-stuffer:1896) the reason is that Prop1 is not being fast enough to decode USB bit stream (NRZI decoding plus bit unstuffing (removing extra bits)) and calculate CRC in order to send response (ACK or NAK) in time.
It would be great if Prop2 could do low-level USB operations in hardware (NRZI encoding/decoding, bit stuffing/unstuffing, CRC calculation and low level handshake).
Here are few references to Micah Dowty's USB host implementation for Prop1:
Propeller Bluetooth Stack Demo
http://scanlime.org/2010/07/propeller-bluetooth-stack-demo/
Working full-speed (12 Mb/s) bit-banging USB Host controller
http://forums.parallax.com/showthread.php?121321-Working-full-speed-(12-Mb-s)-bit-banging-USB-Host-controller
USB and Bluetooth Host Stack
http://obex.parallax.com/objects/652/
Ta,
Boris
If that otherwise works transparently OK, halving the thruput is still workable, at 12Mb - 6Mb is still fine for many apps.
I see mention of 4 COGS, but not of if that was time, or code limited ?
The Prop 2 has hard time slicing, and is 8x faster, so provided code size is ok, this could maybe even go into 1 COG ?
Who would that be? Sir Francis Drake?
The Beatles??
Wow, my poor little 8080 only had 4500 transistors to play with....but they were REALLY BIG compared to transistors today!!
The bad thing ist that there is no USB software in the ROM, otherwise you could program the Prop 2 directly over USB without an USB to Serial converter.
Andy
How did you go with the SD boot code?
Do you still need help?
My apologies... I have been tied up with other work and have while I have checked ocasionally, I have not had the time to post anything in the last few weeks.
What I need to know is which 128-pin package the P2 will be supplied in? (thread tools are a bit lacking on such a long thread for me to find out more)
- Just a P2 chip w SPI Flash and Vreg and a ring of IO pins. Smallest pcb possible.
- An SBC / Emulation pcb - A P2 board with Vreg and...
- microSD
- SRAM/SDRAM
- miniUSB for PS2 Keyboard & Mouse
- TV or VGA (selectable options)
- Stereo Out
- maybe a few other tricks
- any remaining IO pins
I expect to have these pcbs ready to go before the first samples arriveExperimenters version with all pin's drawn to 10 pin's headers in groups of 8 bit's. That connectors are compatible with -- Propeller I -- ProtoBoard -- +V, GND, and 0 to 7 - IO bits group.
Only active parts on PCB are V-Regulators.
Ps. to ALL that made theirs own PCB's to Propeller II
Decoupling Capacitors and theirs placement are very important.
That is one of my question's to !!
CHIP: Packages... right now just planning on 14x14mm TQFP-128.
and a 14mm TQFP128, looks to be 0.4mm (!)
There is also a 14 x 20 mm body width, 0.5 mm pin pitch, but that is not the 14x14 mentioned,
What is suggested --- AND what will be used --- Can be big difference. It is why we need correct info.
Made any PCB that have that incorrect -- Is not so funny.