lol - perhaps I should have said 'That it was tedious' instead... :-) ... I don't mind it, there's so many other cool/fun things to layout.
@Cluso99,
Yes, the width of the buss to allow proper connection to all of the I/O's with all of the features has been known. There are 3 layers of metal used in the buss, leaving 2 layers for perpendicular escapement and connection to the buss. Metal layer 1 and Metal layer 3 'bump up' or 'bump down' to Metal layer 2 to make the connection, while Metal layer 5 bumps down to Metal layer 4. Metal layer 4 is also used to carry power across the buss from the I/O's into the core. I'm up for better ideas to make this more compact. (See attached images)
@goober-head,
I have layed out 'flip chip' designs before, and the problem is the yield isn't as high, the connections from one chip to the other are similar to BGA (Ball Grid Array), and the 'keep out' rules where you can't place active layout is really large around the area. Not to mention added cost.... as I see it has already been mentioned
Note: on Image #2, there should be Metal1 under Metal5 giving it a 'greyish-blue' or even 'lavender' look you see in Image #1... instead, it's just Metal 5... I missed grabbing it when putting together the illustration.
I do not care for all the Chip Bashing - I know how hard it is to cram 10 pounds of stuff into a 1 pound bag. I wish for a multi-megabucks R&D budget, but you get what you pay for. And a damn fine piece of work it is, considering all the irons in the fire. Could you do even a tenth as much?
@All - Before someone says, well, why don't you just place all of the buss wires (Metal 1, Metal 3, and Metal 5) in one stack? ... you can still 'bump up' or 'bump down' to Metal 2 or Metal 4 as needed. ... Yes, you could do that, but it really doesn't gain you much if any real estate over the span of many wires in the buss. By staggering the center buss metal, Metal 3, it helps to reduce parallel capacitance between buss wires. You still get some fringing capacitance with it staggared, but not as much as if it were stacked. (see attachment)
@All - Before someone says, well, why don't you just place all of the buss wires (Metal 1, Metal 3, and Metal 5) in one stack? ... you can still 'bump up' or 'bump down' to Metal 2 or Metal 4 as needed. ... Yes, you could do that, but it really doesn't gain you much if any real estate over the span of many wires in the buss. By staggering the center buss metal, Metal 3, it helps to reduce parallel capacitance between buss wires. You still get some fringing capacitance with it staggared, but not as much as if it were stacked. (see attachment)
Beau: Your connection scheme makes sense. IMHO its necessary to keep everything regular to ensure you only have to test a section. Everything then becomes quite "regularised". No wierd exceptions later.
Will it be possible later to simply/easily expand the outer bus ring outwards to allow for more internal die space (i.e. use a larger die) to get more hub ram on a later variant of prop2 ?
BTW I wasn't being critical. Until you explained the connections required, I had no concept (I guess I just hadn't thought about it) of just how many interconnects were in there, just for the I/Os. And of course, we know there is a lot of options in those I/O pins too. I guess this is why other chips have certain pins dedicated to certain functions. I appreciate having a "regular" set of pins that can all do anything other pins can do. Everything has its price.
@Cluso99 - "Will it be possible later to simply/easily expand the outer bus ring outwards to allow for more internal die space" - The corners are congested, but along the straight buss runs you can or I should say 'could' stretch it to make it larger, even slide the I/O's as a unit up/down/left/right along the buss. Still though that's a lot of work to do that... not impossible though.
We used to say "Foam It and Ship It". This was in 1975. The foaming process was an experimental procedure that produced a fair amount of exothermic heat. When it was done, it was one-piece airtight injection mold.
We designed and built 32-track recording consoles. I was head of Quality Assurance back then. Later on, I earned my Electrical Engineering degree and was promoted to Design Engineer (and to think - I couldn't even spel inginear). Jerry Puckett was Chief Engineer. We were a tight little group back then.
I earned a Computer Science degree back when the paint had barely had time to dry. It was the mid-Eighties and I didn't have time to even catch my breath. to read the exciting conclusion - read Part 2
"We designed and built 32-track recording consoles." - LOL! .... back in the day (late 60's early 80's) my uncle used to work at a recording studio owned/started by "Leon Russell" Shelter Records. I remember hanging out in the studio as a kid with my uncle during some of the recording sessions next to those 32-track recording consoles. Man those were the days!!
As a process reference point, I see this news from Cypress : They have new Async SRAMs, "fabricated using Cypress's 90-nanometer R95 CMOS technology", at 32/64/128MBit, but what really caught my eye, was this : a wide voltage range of 1.7V to 5.5V.
Seems wide supply is gaining - now even on commodity parts like SRAM.
Nobody knows what nobody wants without a market survey. A current prop chip is $8.00. If a dual chip Prop II design pushed the cost up to $30/chip, I would still buy it. I buy chips based on FUNCTIONALITY. If cost were everything, we'd still be using Z-80s. Functionality boils down to 1. What will the chip let me do? 2. What tool support do I have to make the whole project run?
If desisions were left to the bean-counters, we'd still be using an abacus. Investments in the future of technology demand side-stepping the "Cost is King" Smile and putting money in to support great products that are demonstratingly pushing the technology curve upward.
So aside from the yet to be determined cost, would the dual chip get you more features, or relieve cramped spaces, or allow faster development?
Dual-die makes the most sense, when it allows you to mix technoloigies, and use high-volume proven die for one.
So Flash (& even SRAM too) stacked on leading edge CMOS ASIC is common.
Prop 2 does not really 'fit' there, and I think the SRAM needed is not quite your generic ram either ?
If a dual chip Prop II design pushed the cost up to $30/chip, I would still buy it. I buy chips based on FUNCTIONALITY. If cost were everything, we'd still be using Z-80s. Functionality boils down to 1. What will the chip let me do? 2. What tool support do I have to make the whole project run?
Perhaps you are price agnostic, but most engineering & product decisions factor Functionality PER Price, not either alone.
History has examples of chips that ventured too far from an industry Functionality/Price metric.
For the Prop, some of the volume-user design alternative competition comes from CPLDs, (+ more generic uC) and those are getting cheaper and more powerful.
A recent example I noticed was a 256 macrocell Actel A3PNxx part, for $3.30@100+ at Mouser, and 512 macrocells for $5.20, likewise the Lattice MachXO2 at 640 MC is on a (very) similar price-curve at $5.87 (no price yet on the 2 smaller siblings) - those levels of logic, add some serious 'co-processor' capability to a more mainstream controller.
Well, I used 'CPLD' because that's what the vendors call them, and they measure them in MacroCells, even if those are mow rather virtual MacroCells (vMC?) of indeterminate fan-in.
- but you are right, these newest largish (128-640 vMC) CPLDs are really granular like FPGA, with built in FLASH
CPLDs aren't really suitable as co-processors. FPGAs are much larger, have things like multipliers, and IP for DSP functions etc. is widely available.
You are thinking of Maths-Co-Processors ? - there are many other peripheral conditioning/processing tasks, that you might do in a COG for example, that can be done in a CPLD.
Quadrature Counting is one example, Chroma (Phase) modulation is another, or even counting over 40MHz...
.
I was wondering if the Prop 2 will be able to do RF. Will it be possible to write a driver for a FM transceiver with a few external components? This could replace 433Mhz transceiver.
"Maybe we will be enlightened in another 29 hours (the webinar or meetup at Parallax)" - That's where I'm kinda leaning at the moment. Chip and I both have our plates full with a few changes (<--good ones) . Any questions should be directed towards Chip at the webinar.
The last date I saw was nov-2010. Hmmmm, kinda slipped past that one. Can you guys give a fresh update? If you wait too long, your market might drift.........
Comments
How tuff would it be to put the design on two dies?
The dies would mate back to back to allow more real estate ( like a multi-layer board).
You could pick which side a particular item was on to facillitate heat distribution.
http://www.xilinx.com/support/documentation/white_papers/wp380_Stacked_Silicon_Interconnect_Technology.pdf
lol - perhaps I should have said 'That it was tedious' instead... :-) ... I don't mind it, there's so many other cool/fun things to layout.
@Cluso99,
Yes, the width of the buss to allow proper connection to all of the I/O's with all of the features has been known. There are 3 layers of metal used in the buss, leaving 2 layers for perpendicular escapement and connection to the buss. Metal layer 1 and Metal layer 3 'bump up' or 'bump down' to Metal layer 2 to make the connection, while Metal layer 5 bumps down to Metal layer 4. Metal layer 4 is also used to carry power across the buss from the I/O's into the core. I'm up for better ideas to make this more compact. (See attached images)
@goober-head,
I have layed out 'flip chip' designs before, and the problem is the yield isn't as high, the connections from one chip to the other are similar to BGA (Ball Grid Array), and the 'keep out' rules where you can't place active layout is really large around the area. Not to mention added cost.... as I see it has already been mentioned
Note: on Image #2, there should be Metal1 under Metal5 giving it a 'greyish-blue' or even 'lavender' look you see in Image #1... instead, it's just Metal 5... I missed grabbing it when putting together the illustration.
@All - Before someone says, well, why don't you just place all of the buss wires (Metal 1, Metal 3, and Metal 5) in one stack? ... you can still 'bump up' or 'bump down' to Metal 2 or Metal 4 as needed. ... Yes, you could do that, but it really doesn't gain you much if any real estate over the span of many wires in the buss. By staggering the center buss metal, Metal 3, it helps to reduce parallel capacitance between buss wires. You still get some fringing capacitance with it staggared, but not as much as if it were stacked. (see attachment)
I use same technique on PCB's if I need draw traces on both sides in same direction.
Will it be possible later to simply/easily expand the outer bus ring outwards to allow for more internal die space (i.e. use a larger die) to get more hub ram on a later variant of prop2 ?
BTW I wasn't being critical. Until you explained the connections required, I had no concept (I guess I just hadn't thought about it) of just how many interconnects were in there, just for the I/Os. And of course, we know there is a lot of options in those I/O pins too. I guess this is why other chips have certain pins dedicated to certain functions. I appreciate having a "regular" set of pins that can all do anything other pins can do. Everything has its price.
We designed and built 32-track recording consoles. I was head of Quality Assurance back then. Later on, I earned my Electrical Engineering degree and was promoted to Design Engineer (and to think - I couldn't even spel inginear). Jerry Puckett was Chief Engineer. We were a tight little group back then.
I earned a Computer Science degree back when the paint had barely had time to dry. It was the mid-Eighties and I didn't have time to even catch my breath.
to read the exciting conclusion - read Part 2
"We designed and built 32-track recording consoles." - LOL! .... back in the day (late 60's early 80's) my uncle used to work at a recording studio owned/started by "Leon Russell" Shelter Records. I remember hanging out in the studio as a kid with my uncle during some of the recording sessions next to those 32-track recording consoles. Man those were the days!!
http://en.wikipedia.org/wiki/Shelter_Records
Attached a picture of my Uncle Tom taken in the 70's in his recording studio
Seems wide supply is gaining - now even on commodity parts like SRAM.
Nobody knows what nobody wants without a market survey. A current prop chip is $8.00. If a dual chip Prop II design pushed the cost up to $30/chip, I would still buy it. I buy chips based on FUNCTIONALITY. If cost were everything, we'd still be using Z-80s. Functionality boils down to 1. What will the chip let me do? 2. What tool support do I have to make the whole project run?
If desisions were left to the bean-counters, we'd still be using an abacus. Investments in the future of technology demand side-stepping the "Cost is King" Smile and putting money in to support great products that are demonstratingly pushing the technology curve upward.
Dual-die makes the most sense, when it allows you to mix technoloigies, and use high-volume proven die for one.
So Flash (& even SRAM too) stacked on leading edge CMOS ASIC is common.
Prop 2 does not really 'fit' there, and I think the SRAM needed is not quite your generic ram either ?
Perhaps you are price agnostic, but most engineering & product decisions factor Functionality PER Price, not either alone.
History has examples of chips that ventured too far from an industry Functionality/Price metric.
For the Prop, some of the volume-user design alternative competition comes from CPLDs, (+ more generic uC) and those are getting cheaper and more powerful.
A recent example I noticed was a 256 macrocell Actel A3PNxx part, for $3.30@100+ at Mouser, and 512 macrocells for $5.20, likewise the Lattice MachXO2 at 640 MC is on a (very) similar price-curve at $5.87 (no price yet on the 2 smaller siblings) - those levels of logic, add some serious 'co-processor' capability to a more mainstream controller.
Well, I used 'CPLD' because that's what the vendors call them, and they measure them in MacroCells, even if those are mow rather virtual MacroCells (vMC?) of indeterminate fan-in.
- but you are right, these newest largish (128-640 vMC) CPLDs are really granular like FPGA, with built in FLASH
You are thinking of Maths-Co-Processors ? - there are many other peripheral conditioning/processing tasks, that you might do in a COG for example, that can be done in a CPLD.
Quadrature Counting is one example, Chroma (Phase) modulation is another, or even counting over 40MHz...
.
I was wondering if the Prop 2 will be able to do RF. Will it be possible to write a driver for a FM transceiver with a few external components? This could replace 433Mhz transceiver.
Fred
Can you give us an update?
Thanks!
OBC
"Maybe we will be enlightened in another 29 hours (the webinar or meetup at Parallax)" - That's where I'm kinda leaning at the moment. Chip and I both have our plates full with a few changes (<--good ones) . Any questions should be directed towards Chip at the webinar.
Ken: Get that whip out