It just seems highly unlikely to me that there are in fact applications which *only* a P2 is capable of performing.
I'm not quite following the point you were trying to make, but given
a) We have P2's running now, on FPGA's
b) Any (almost) P2 peripheral can be crafted in Programmable logic
we already have an answer to that...
The nearest Prop-Space almost-competitor, would be a NIOS core, running on the smallest FPGA that will host it.
Notice also a single Prop COG is ~ 2x the logic of that NIOS, so a FullProp represents 16x the Logic ( or 8x if you allow some peripherals to be added to the NIOS, in the spare 57% of that FPGA example)
I'm not quite following the point you were trying to make, but given
a) We have P2's running now, on FPGA's
b) Any (almost) P2 peripheral can be crafted in Programmable logic
we already have an answer to that...
The nearest Prop-Space almost-competitor, would be a NIOS core, running on the smallest FPGA that will host it.
I'd rather see a specific application example. I'm sure there are other comparisons to make besides FPGAs with NIOS cores (eg, maybe only the FPGA itself). Again, it depends on the application.
So this doesn't really address the point: there are no (or at best very very few) real-world design applications at which only a P2 can actually do the work.
I see expanding openings where a design has chosen an ARM, and loaded it with some OS. (RasPi is a classic example). If that user wants to play in the
hard-real-time world, they need something else.
Yep, they go to the zync or those new fangled TI ARM's with PRU's on them.
Potatohead,
...that long post missed the mark...
Not totally, I appreciate what you say.
Market research is all about data. Many of the pricing answers are data driven. The more you have, the more you can infer
That's what I thought, there is no magic formula to turn that data into the launch price. Some brave soul has to make the final estimate and run with it. I
think MS just noticed that with the Windows RT tablet fiasco.
So this doesn't really address the point: there are no (or at best very very few) real-world design applications at which only a P2 can actually do the work.
but it is self evident, that there are no real-world design applications at which only a P2 can actually do the work - programmable logic proves that.
The smarter question, is at what price and complexity can that work be done ?
There are plenty in the ATE arena, where P2 will easily trump alternative designs.
DACs + ADCs + Maths ? - nothing else can match those channel numbers in one package.
In industrial control, where it trends to the instrumentation/high performance end, you have Resolutions and Maths and Tasking in P2 hat can shake the others.
DSP+CAN ? - pop over to ADi, & their BlackFin DSPs, and we see DSPs start cheap, sub $2 in volumes, but if you want CAN, you bump well above $10.
Or, their new ADSP-CM40x might have appeal, when it hits final release. M4F, with price indicators of $8~$14
Can someone explain where determinism is important? I understand that it's needed for things like UARTs, USB, PWM,
Well there is the thing.
If you have a normal run of the mill MCU it has UART, USB, SPI, PWM, etc etc. It's main CPU does not need timing determinism down to nano seconds because the hardware does that. For machine control and such good old interrupts on GPIO pins will do fine.
BUT:
The Prop is designed such that there is no dedicated peripheral devices. They are intended to be created in software. Hence the need for multiple processors (COGs). And hence the need for timing determinism.
Why is the Prop like that?
No idea. Ask Chip. But it does mean you have a very flexible piece of silicon. Need more UARTS, you got them. Need more PWM, you got them. And so on. As your design evolves you don't need to switch from one device to another, if there is one, just change the code and move on with the job.
That flexibility is the Props greatest asset.
XMOS started out with a similar concept. Seems that recently they have backed down on that and introduced chips with ARM cores and UART, SPI, USB etc peripherals as well as their original hard real-time cores on board.
but it is self evident, that there are no real-world design applications at which only a P2 can actually do the work - programmable logic proves that.
Thank you. That was the point being made (some doubted it).
The smarter question, is at what price and complexity can that work be done ?
That's the second point (or the first, depending on how you view it). We're getting there now...
There are plenty in the ATE arena, where P2 will easily trump alternative designs.
DACs + ADCs + Maths ? - nothing else can match those channel numbers in one package.
Are you sure? Moreover, having it in one package may not trump price. Anyway, we need specific examples to make comparisons - and as acknowledged above - there *are* comparisons (options) to be considered.
In industrial control, where it trends to the instrumentation/high performance end, you have Resolutions and Maths and Tasking in P2 hat can shake the others.
That's right up my ally. And as you go on to show, there are options at the high end - many in the $10 range. Moreover, this kind of performance is still seldom required. Most of the work I do, for example, can be done with C8051Fs, dsPICs, PIC32s, ARMs, or even plain-jane ATmega AVRs, and of course the P1.
Are you guys arguing there is no point in building the PII because the is nothing it can do that can't be done cheaper and easier already?
Nope. But this does point to the potential folly of trying to chase better, more, and higher specs/features over and again. It also shows that added complexity doesn't always help. If P2's user manual begins even to rival, in terms of size and/or incomprehensibility, say, a Cotex-M4s a crucial advantage will have been forfeited. I'm *not* saying that has already happened or is about to, I'm just saying.
In my view, it would have been much better to have made P2 an incremental improvement over P1. More speed (4x if possible), more memory, and a few other improvements would have made a huge difference in the number of applications in which it could fit. That chip would likely be here now - with the proper focus. Engineering costs would have been lower. Parallax would have a second chip under their belt and greatly improved their standing as a semiconductor company.
That didn't happen. So here we are. Can't go back, must go forward (I suppose). That doesn't mean, however, that the lesson should simply be forgotten.
The Prop is designed such that there is no dedicated peripheral devices. They are intended to be created in software. Hence the need for multiple processors (COGs). And hence the need for timing determinism.
Why is the Prop like that?
No idea. Ask Chip. But it does mean you have a very flexible piece of silicon. Need more UARTS, you got them. Need more PWM, you got them. And so on. As your design evolves you don't need to switch from one device to another, if there is one, just change the code and move on with the job.
Okay, that suggests to me that we should stop claiming that determinism is what distinguishes the Propeller from other MCUs because determinism is mostly needed on the Propeller to implement peripherals that other MCUs have in custom hardware. Instead we should emphasize the flexiblity of the Propeller to have different combinations of periperals as needed. No need to mention determinism because that is just a feature needed to implement soft peripherals and can't really be compared with what is available on MCUs that have hard peripherals.
Thing about ATE is that you often need to drive a lot of signals onto the unit under test and read a lot of signals back.
I used to work in a test department for radar and missile systems, there was an endless number of "test jigs" designed to exercise all manner of circuit boards with odd signals. All customized to test one particular circuit.
Thing about ATE is that you often need to drive a lot of signals onto the unit under test and read a lot of signals back.
I used to work in a test department for radar and missile systems, there was an endless number of "test jigs" designed to exercise all manner of circuit boards with odd signals. All customized to test one particular circuit.
There is that real time determinism again...
Thanks! That certainly sounds like an application where dedicated hardware peripherals like UART, SPI, I2C, PWM, etc wouldn't do the job and the Propeller would.
In my view, it would have been much better to have made P2 an incremental improvement over P1. More speed (4x if possible), more memory, and a few other improvements would have a made a huge difference in the number of applications in which it could fit. That chip would likely be here now - with the proper focus. Engineering costs would have been lower. Parallax would have a second chip under their belt and greatly improved their standing as a semiconductor company.
That didn't happen. So here we are. Can't go back, must go forward (I suppose). That doesn't mean, however, that the lesson should simply be forgotten.
I do not see much of a lesson here, just a musing on an alternative pathway.
There are thousands of alternative pathways, but little is to be gained by musing on last years problems, better to focus on the live problems.
The P2 will never displace your generic $2 micros purely on chip cost, it comes into play when you outgrow that sandpit, and look for the next step.
or when you have a product where chip cost is not actually as mission-critical as some imagine.
It's not imagination. If one expects to ship 10,000 units per year and someone else proposes that you add $5 to the BOM, that someone else had better be able to provide a sound reason for doing so. Once significant volume is a reality, price will not be an issue to cavalierly dismiss.
That's *not* to say there aren't other tradeoffs.
And yes, we are looking at the next step. The discussion has centered around $10-$20+ solutions.
I do not see much of a lesson here, just a musing on an alternative pathway.
Then you need to re-read what I wrote. Because there is, and it's explicitly spelled out.
There are thousands of alternative pathways, but little is to be gained by musing on last years problems, better to focus on the live problems.
Okay, this is a childish way to view much of anything. Don't learn/remember the past and you're doomed to repeat it. That doesn't mean stay in the past - only remember it and its lessons.
It's not imagination. If one expects to ship 10,000 units per year and someone else proposes that you add $5 to the BOM, that someone else had better be able to provide a sound reason for doing so. Once significant volume is a reality, price will not be an issue to cavalierly dismiss.
That's *not* to say there aren't other tradeoffs.
And yes, we are looking at the next step. The discussion has centered around $10-$20+ solutions.
I don't think you read what I wrote, but since you moved to the 10k+ area, if you look at companies like ADI and Maxim, I'm always amazed by how many niche parts those .companies have.
Some of their order line volumes must be very low, in consumer-run terms, but they still manage to offer the parts, and be very large companies.
Part of how they achieve this, is to find enough moderate volume customers.
The Medical instrumentation sub group, is one that springs to mind.
The Prop is designed such that there is no dedicated peripheral devices. They are intended to be created in software. Hence the need for multiple processors (COGs). And hence the need for timing determinism.
Why is the Prop like that?
No idea. Ask Chip. But it does mean you have a very flexible piece of silicon. Need more UARTS, you got them. Need more PWM, you got them. And so on. As your design evolves you don't need to switch from one device to another, if there is one, just change the code and move on with the job.
That flexibility is the Props greatest asset.
Yes, that and ease of use (for the amount of processing power it does provide).
Then you need to re-read what I wrote. Because there is, and it's explicitly spelled out.
.
Did that, still only see a musing, no concrete lesson. Reflecting on what might have been, does not seem too practical to me.
Better to focus on the now. Past decisions are always made on the constraints of the time.
I don't think you read what I wrote, but since you moved to the 10k+ area, if you look at companies like ADI and Maxim, I'm always amazed by how many niche parts those .companies have.
Some of their order line volumes must be very low, in consumer-run terms, but they still manage to offer the parts, and be very large companies.
Part of how they achieve this, is to find enough moderate volume customers.
And these are in fact the types of volumes we're talking about. (Well, the sane among us anyway.)
And yes, I read what you wrote. I used a 10,000 piece example. But one can see where even at 1,000 pieces price as a factor doesn't simply go away.
Did that, still only see a musing, no concrete lesson. Reflecting on what might have been, does not seem too practical to me.
Better to focus on the now. Past decisions are always made on the constraints of the time.
But I didn't write a mere reflection on might-have-beens:
But this does point to the potential folly of trying to chase better, more, and higher specs/features over and again. It also shows that added complexity doesn't always help. If P2's user manual begins even to rival, in terms of size and/or incomprehensibility, say, a Cotex-M4s a crucial advantage will have been forfeited. I'm *not* saying that has already happened or is about to, I'm just saying.
So are you saying that this is somehow not a potential pitfall? Regardless, it's more than ruminating on the past.
Comments
I'm not quite following the point you were trying to make, but given
a) We have P2's running now, on FPGA's
b) Any (almost) P2 peripheral can be crafted in Programmable logic
we already have an answer to that...
The nearest Prop-Space almost-competitor, would be a NIOS core, running on the smallest FPGA that will host it.
Some interesting numbers were given here
http://forums.parallax.com/showthread.php/150849-BeMicro-CV-FPGA-Board-for-P2?p=1222355&viewfull=1#post1222355
Notice also a single Prop COG is ~ 2x the logic of that NIOS, so a FullProp represents 16x the Logic ( or 8x if you allow some peripherals to be added to the NIOS, in the spare 57% of that FPGA example)
So this doesn't really address the point: there are no (or at best very very few) real-world design applications at which only a P2 can actually do the work.
Potatohead, Not totally, I appreciate what you say. That's what I thought, there is no magic formula to turn that data into the launch price. Some brave soul has to make the final estimate and run with it. I
think MS just noticed that with the Windows RT tablet fiasco.
but it is self evident, that there are no real-world design applications at which only a P2 can actually do the work - programmable logic proves that.
The smarter question, is at what price and complexity can that work be done ?
There are plenty in the ATE arena, where P2 will easily trump alternative designs.
DACs + ADCs + Maths ? - nothing else can match those channel numbers in one package.
In industrial control, where it trends to the instrumentation/high performance end, you have Resolutions and Maths and Tasking in P2 hat can shake the others.
DSP+CAN ? - pop over to ADi, & their BlackFin DSPs, and we see DSPs start cheap, sub $2 in volumes, but if you want CAN, you bump well above $10.
Or, their new ADSP-CM40x might have appeal, when it hits final release. M4F, with price indicators of $8~$14
If you have a normal run of the mill MCU it has UART, USB, SPI, PWM, etc etc. It's main CPU does not need timing determinism down to nano seconds because the hardware does that. For machine control and such good old interrupts on GPIO pins will do fine.
BUT:
The Prop is designed such that there is no dedicated peripheral devices. They are intended to be created in software. Hence the need for multiple processors (COGs). And hence the need for timing determinism.
Why is the Prop like that?
No idea. Ask Chip. But it does mean you have a very flexible piece of silicon. Need more UARTS, you got them. Need more PWM, you got them. And so on. As your design evolves you don't need to switch from one device to another, if there is one, just change the code and move on with the job.
That flexibility is the Props greatest asset.
XMOS started out with a similar concept. Seems that recently they have backed down on that and introduced chips with ARM cores and UART, SPI, USB etc peripherals as well as their original hard real-time cores on board.
Err, are you sure they do ? : at $69 for the entry level XC7Z0 parts, in BGA packages...
Well that good news then. The potential competition is not priced so low.
That's the second point (or the first, depending on how you view it). We're getting there now...
Are you sure? Moreover, having it in one package may not trump price. Anyway, we need specific examples to make comparisons - and as acknowledged above - there *are* comparisons (options) to be considered.
That's right up my ally. And as you go on to show, there are options at the high end - many in the $10 range. Moreover, this kind of performance is still seldom required. Most of the work I do, for example, can be done with C8051Fs, dsPICs, PIC32s, ARMs, or even plain-jane ATmega AVRs, and of course the P1.
Are you guys arguing there is no point in building the PII because the is nothing it can do that can't be done cheaper and easier already?
Err no, more the opposite, my examples are what I'd call relatively expensive, and show there is room for a P2.
The P2 will never displace your generic $2 micros purely on chip cost, it comes into play when you outgrow that sandpit, and look for the next step.
or when you have a product where chip cost is not actually as mission-critical as some imagine.
Automatic/Automated Test Equipment ( and Test and measuring apps too )
In my view, it would have been much better to have made P2 an incremental improvement over P1. More speed (4x if possible), more memory, and a few other improvements would have made a huge difference in the number of applications in which it could fit. That chip would likely be here now - with the proper focus. Engineering costs would have been lower. Parallax would have a second chip under their belt and greatly improved their standing as a semiconductor company.
That didn't happen. So here we are. Can't go back, must go forward (I suppose). That doesn't mean, however, that the lesson should simply be forgotten.
Thing about ATE is that you often need to drive a lot of signals onto the unit under test and read a lot of signals back.
I used to work in a test department for radar and missile systems, there was an endless number of "test jigs" designed to exercise all manner of circuit boards with odd signals. All customized to test one particular circuit.
There is that real time determinism again...
I do not see much of a lesson here, just a musing on an alternative pathway.
There are thousands of alternative pathways, but little is to be gained by musing on last years problems, better to focus on the live problems.
That's *not* to say there aren't other tradeoffs.
And yes, we are looking at the next step. The discussion has centered around $10-$20+ solutions.
Okay, this is a childish way to view much of anything. Don't learn/remember the past and you're doomed to repeat it. That doesn't mean stay in the past - only remember it and its lessons.
I don't think you read what I wrote, but since you moved to the 10k+ area, if you look at companies like ADI and Maxim, I'm always amazed by how many niche parts those .companies have.
Some of their order line volumes must be very low, in consumer-run terms, but they still manage to offer the parts, and be very large companies.
Part of how they achieve this, is to find enough moderate volume customers.
The Medical instrumentation sub group, is one that springs to mind.
Did that, still only see a musing, no concrete lesson. Reflecting on what might have been, does not seem too practical to me.
Better to focus on the now. Past decisions are always made on the constraints of the time.
And yes, I read what you wrote. I used a 10,000 piece example. But one can see where even at 1,000 pieces price as a factor doesn't simply go away.
So are you saying that this is somehow not a potential pitfall? Regardless, it's more than ruminating on the past.
This is way OT. Can we move this elsewhere please???
Yup, all covered by my last paragraph.
also on the 'quicker' angle, notice the Build time of that (appx) FPGA alternative here
http://forums.parallax.com/showthrea...=1#post1222355
- 10 minutes.