What is not to like about specifically sharing bandwith between co-operating cogs ???
Using this should allow lower total system powers, as SW will finish faster, and spend longer in the lower power wait modes.
Energy saving is always good.
I agree with all you naysayers... <tongue-in-cheek>
The last mask was believed workable, just not with OnSemi. So, just send it out "as is" to TSMC.
Then you'll be happy - 128KB hub, QUAD hub access, no new instruction set, no UARTs, no SERDES, no slot changes, possibly no USB FS, no CRC bit mode, no HUBEXEC, no AUGD/S, etc, etc, etc.
Gee, we may even see this shuttle run back sooner
Now, forget the hobbyists for a bit and think about Parallax's real customers of the P2, the commercial users. Do you think they will wrap their heads around a issues if they can squeeze a design in by utilising some additional options??? Better they be given those possibilities than not!
Now, forget the hobbyists for a bit and think about Parallax's real customers of the P2, the commercial users. Do you think they will wrap their heads around a issues if they can squeeze a design in by utilising some additional options??? Better they be given those possibilities than not!
Correct, that is why Parallax Semiconductor exists.
Not all applications will require 8 cogs, just because they are there doesn't mean they have to be used.
It think it has already been demonstrated that the P2 will do LOTS more in less cogs.
If P2 can do in 5 or 6 cogs what took P1 all 8 then why not utilize the extra slots to BOOST the others.
Power to the people.
I'm sure the commercial users of P2 are not going to care about OBEX as their IP will never be posted anyway.
Parallax will benefit from less frequent shuttle runs - more time to run simulators, and it is also preferrable to pay $50,000 per shuttle run instead of $30,000 - after all, Parallax would get a bigger tax write off!
Besides, $50,000 for one shuttle run is cheaper than 2x$30,000 for two shuttle runs, after all, we know for certain that no further shuttle runs will be needed!
I agree with all you naysayers... <tongue-in-cheek>
The last mask was believed workable, just not with OnSemi. So, just send it out "as is" to TSMC.
Then you'll be happy - 128KB hub, QUAD hub access, no new instruction set, no UARTs, no SERDES, no slot changes, possibly no USB FS, no CRC bit mode, no HUBEXEC, no AUGD/S, etc, etc, etc.
Gee, we may even see this shuttle run back sooner
Now, forget the hobbyists for a bit and think about Parallax's real customers of the P2, the commercial users. Do you think they will wrap their heads around a issues if they can squeeze a design in by utilising some additional options??? Better they be given those possibilities than not!
Not all applications will require 8 cogs, just because they are there doesn't mean they have to be used.
It think it has already been demonstrated that the P2 will do LOTS more in less cogs.
If P2 can do in 5 or 6 cogs what took P1 all 8 then why not utilize the extra slots to BOOST the others.
Power to the people.
I'm sure the commercial users of P2 are not going to care about OBEX as their IP will never be posted anyway.
With Ray working on USB, soon we can say "Bye Bye" to FTDI chips.
There is no reason the boot loader in the prop can't load a fancier boot loader from the SPI flash, which can check for autoload.bin on the SD card (or flash file system)
If it does not find an autoload.bin, it enumerates as a CDC USB device, and waits
Saves ~$2-$3 on BOM costs, which translates to $8-$15 savings on retail price.
Yes, that extreme example of a two COG object or library unit that can do what it likes with its share of HUB slots with out any possible conflict with other objects. It is extreme to totally waste a COG though!
Well, I guess the COG wouldn't actually *have* to be wasted. It could be used by the same object since presumably that object would understand the limitations of the COG that had donated its slot. So you could have a two-COG object that had one high-speed hub access COG and another that didn't use the hub at all. Practically speaking though, how many COGs don't need hub access at all? Don't most at least have a mailbox in hub memory?
Given that they want it to sell, and sell a lot, and given Cortex M4 pricing (which has an FPU), LPC4370 pricing (204MHz M4, FPU, 2x 204MHz M0) I would be surprised if it was more expensive than the LPC4370 - but I don't know Parallax's plans, so take that guess with a sack of salt.
Given that they want it to sell, and sell a lot, and given Cortex M4 pricing (which has an FPU), LPC4370 pricing (204MHz M4, FPU, 2x 204MHz M0) I would be surprised if it was more expensive than the LPC4370 - but I don't know Parallax's plans, so take that guess with a sack of salt.
I suspect it will be well more than that, and if I recall there was a thread some time back that more or less said as much. In any case, in order to plan and target specific markets/applications (or even talk about them much) it's important to have a good general idea; otherwise, it quickly becomes rather meaningless.
I remember a higher number for a module with SDRAM, breaking out to .1" headers
IMHO, pricing it higher than LPC4370 would seriously limit market penetration, and be a mistake. Fortunately, I don't have to decide pricing that's Parallax's headache.
I suspect it will be well more than that, and if I recall there was a thread some time back that more or less said as much. In any case, in order to plan and target specific markets/applications (or even talk about them much) it's important to have a good general idea; otherwise, it quickly becomes rather meaningless.
I remember a higher number for a module with SDRAM, breaking out to .1" headers
IMHO, pricing it higher than LPC4370 would seriously limit market penetration, and be a mistake. Fortunately, I don't have to decide pricing that's Parallax's headache.
I agree with you there. I don't think the chip would be commercially viable priced much higher. The LPC4370 is apprx. $10 now low quantity, and will probably drop more by the time P2 is out. It'll be tough to match that, especially if they want to get engineering costs ($4 million+ and counting?) back in a reasonable time frame. We'll see. Anyway, something that has to be factored in when making plans.
Prop Spin/pasm/hpasm development system ... running on the Prop!
Yep. Been thinking it since the meetup in Rocklin. Chip and I, and a few others were musing about various things possible. Along with that dev system, one could have some nice programs and tools sitting in storage. A nice board with some connectors, external circuits of various kinds, and suddenly one has a pretty powerful workbench computer to do a variety of things...
I'm sure many of us have used our P1 in similar ways. Logic analyzer, signal generator, etc...
I have a 500Msps much more expensive one, but I end up using the logic sniffers more; so much so that I have three of them - one semi-permanently attached to one of my DE0-Nano's.
P2 should sample more channels at the same 200Msps rate
Yep. Been thinking it since the meetup in Rocklin. Chip and I, and a few others were musing about various things possible. Along with that dev system, one could have some nice programs and tools sitting in storage. A nice board with some connectors, external circuits of various kinds, and suddenly one has a pretty powerful workbench computer to do a variety of things...
I'm sure many of us have used our P1 in similar ways. Logic analyzer, signal generator, etc...
Cheap at how much? What's the price? In fact, since we're on the subject, how much will a P2 chip cost in low to medium quantities?
How much vill u pay uh? $50? $40? goin cheap at $30, but to u a spezal price $25!
Seriously, Chip gave us numbers, but Parallax have to recoup their investment, so Ken will have the input here. It will be what the market can stand to recoup as quickly as possible.
The price I am willing to pay just soared over the past week or is it
I don't think cheap would be the primary value in a self-hosted system. The thing can't cost too much, but there is no real reason it has to match something like the Pi, for example.
The value of it would be in how it operates, features offered, etc...
The price I am willing to pay just soared over the past week or is it
Word!
someone said:
I don't think the chip would be commercially viable priced much higher.
It seems simplistic to say that the P2 won't be commercially viable if it doesn't match the price of the LPC4370. The two are substantially different, philosophically and practically. Also, who can know of all commercial applications in existence? I'm surprised at the varied uses to which the P1 is put. It has done well in an environment of dirt cheap ARMs.
IMHO, pricing it higher than LPC4370 would seriously limit market penetration, and be a mistake. Fortunately, I don't have to decide pricing that's Parallax's headache.
The LPC4370 shows 1,000: $5.34 vs Prop 1 @ 500: $5.68
So I'd say it there is not even a remote chance of P2 being priced lower than LPC4370.
The LPC4370 shows 1,000: $5.34 vs Prop 1 @ 500: $5.68
So I'd say it there is not even a remote chance of P2 being priced lower than LPC4370.
IIRC Chip said the P2 may in fact be a tiny bit cheaper raw cost but there is a large R&D to recover first. I am sure someone wanting 1M pcs could negotiate a great deal with Ken. And we would all be so happy for Parallax too
Comments
Using this should allow lower total system powers, as SW will finish faster, and spend longer in the lower power wait modes.
Energy saving is always good.
Let us acknowledge the term "slot stealing" as false and intentionally perjorative.
The last mask was believed workable, just not with OnSemi. So, just send it out "as is" to TSMC.
Then you'll be happy - 128KB hub, QUAD hub access, no new instruction set, no UARTs, no SERDES, no slot changes, possibly no USB FS, no CRC bit mode, no HUBEXEC, no AUGD/S, etc, etc, etc.
Gee, we may even see this shuttle run back sooner
Now, forget the hobbyists for a bit and think about Parallax's real customers of the P2, the commercial users. Do you think they will wrap their heads around a issues if they can squeeze a design in by utilising some additional options??? Better they be given those possibilities than not!
Correct, that is why Parallax Semiconductor exists.
Not all applications will require 8 cogs, just because they are there doesn't mean they have to be used.
It think it has already been demonstrated that the P2 will do LOTS more in less cogs.
If P2 can do in 5 or 6 cogs what took P1 all 8 then why not utilize the extra slots to BOOST the others.
Power to the people.
I'm sure the commercial users of P2 are not going to care about OBEX as their IP will never be posted anyway.
Yes!
Parallax will benefit from less frequent shuttle runs - more time to run simulators, and it is also preferrable to pay $50,000 per shuttle run instead of $30,000 - after all, Parallax would get a bigger tax write off!
Besides, $50,000 for one shuttle run is cheaper than 2x$30,000 for two shuttle runs, after all, we know for certain that no further shuttle runs will be needed!
P2_Task 50MIPS/task, 200MB/sec hub access assuming averaging over four tasks
Therefore
A P1 compares poorly to TWO P2 cogs (assuming all four tasks code fits in teh cog) as:
8x P1 cog: 160MIPS max, 160MB/sec max
2x P2 cog: 400MIPS max, 1600MB/sec max
So potentially two P2 cogs are 2.5 times as fast with 10x the bandwidth as a whole P1.
A P1 vs P2 is even more uneven.
160MIPS vs 1600MIPS (10x compute power, even without considering MUL,DIV,CORDIC etc)
160MB/s vs 6400MB/s (40x hub memory bandwidth)
Dem numbers look good Bill!
With 256KB hub, and hubexec, there is no reason why PNut could not be translated from x86asm to hpasm. It would fit.
Second holy grail possible - Prop Spin/pasm/hpasm development system ... running on the Prop!
Wait, if you order now...
even a dinky 1MB SPI flash has more than enough storage for PNut/editor
8MB SPI flash would have room for a 7MB file system.
TALK ABOUT A CHEAP DEV BOX!
Prop + SPI flash + PS2 kb/mouse (soon USB KB/mouse) + TV or VGA monitor
For data storage, add uSD or USB flash stick!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!
There is no reason the boot loader in the prop can't load a fancier boot loader from the SPI flash, which can check for autoload.bin on the SD card (or flash file system)
If it does not find an autoload.bin, it enumerates as a CDC USB device, and waits
Saves ~$2-$3 on BOM costs, which translates to $8-$15 savings on retail price.
"Not much more than P1"
Given that they want it to sell, and sell a lot, and given Cortex M4 pricing (which has an FPU), LPC4370 pricing (204MHz M4, FPU, 2x 204MHz M0) I would be surprised if it was more expensive than the LPC4370 - but I don't know Parallax's plans, so take that guess with a sack of salt.
IMHO, pricing it higher than LPC4370 would seriously limit market penetration, and be a mistake. Fortunately, I don't have to decide pricing
Yep. Been thinking it since the meetup in Rocklin. Chip and I, and a few others were musing about various things possible. Along with that dev system, one could have some nice programs and tools sitting in storage. A nice board with some connectors, external circuits of various kinds, and suddenly one has a pretty powerful workbench computer to do a variety of things...
I'm sure many of us have used our P1 in similar ways. Logic analyzer, signal generator, etc...
I've had visions of full bus rate sampling... and signal generation... forever. (6.25MHz/10ns sounds familiar I think)
I used Hanno's ViewPort to debug the first Morpheus prototype, including the first drivers.
Dev box, test instrument, workbenck... SONIC SCREWDRIVER!!!!!!!
Talking about test instruments... Have you tried
http://www.seeedstudio.com/depot/preorder-open-workbench-logic-sniffer-p-612.html?cPath=75
I have a 500Msps much more expensive one, but I end up using the logic sniffers more; so much so that I have three of them - one semi-permanently attached to one of my DE0-Nano's.
P2 should sample more channels at the same 200Msps rate
Anyway, that might explain my SPIN + PASM comments earlier. There could be some nice markets made, if somebody has the right vision. Needs to exist.
Seriously, Chip gave us numbers, but Parallax have to recoup their investment, so Ken will have the input here. It will be what the market can stand to recoup as quickly as possible.
The price I am willing to pay just soared over the past week
The value of it would be in how it operates, features offered, etc...
Word!
someone said:
It seems simplistic to say that the P2 won't be commercially viable if it doesn't match the price of the LPC4370. The two are substantially different, philosophically and practically. Also, who can know of all commercial applications in existence? I'm surprised at the varied uses to which the P1 is put. It has done well in an environment of dirt cheap ARMs.
I don't think GCC would be a good compiler to run on the P2, something like Catalina is probably a lot more compact.
The LPC4370 shows 1,000: $5.34 vs Prop 1 @ 500: $5.68
So I'd say it there is not even a remote chance of P2 being priced lower than LPC4370.
Yeah, it was said in jest. That being said it would make quite a great challenge. Bit out of my league though.
Now, what was that killer app again?