How to coordinate with Smartpin in NCO mode? IN not working?

RaymanRayman Posts: 9,909
edited 2019-01-14 - 15:40:56 in Propeller 2
I have pin#1 toggling using Smartpin in NCO mode like this:
'Turn on pixel clock
            mov     x,##SmartMode
            wrpin   x,#PClkPin
            mov     x,##$0D  '1.2 MHz with $0D, 9.62 MHz with wypin=$8000_0000
            wxpin   x,#PClkPin
            mov     x,##$1000_0000'8000_0000  'Toggle every n base period
            wypin   x,#PClkPin
            dirh    #PClkPin

Then, I'm trying to make pin#0 follow the output using testp on the smartpin like this:
TestLoop
            nop
            nop
            testp   #PClkPin wc 
    if_nc   drvh    #DePin
    if_c    drvl    #DePin                                                        
            nop
            nop
            jmp     #TestLoop

Doesn't work though, seems in on smartpin is always high...
What am I doing wrong?
Prop Info and Apps: http://www.rayslogic.com/

Comments

  • ElectrodudeElectrodude Posts: 1,291
    edited 2019-01-14 - 18:43:14
    The IN, OUT, and DIR lines of a pin don't mean what they normally mean when the smartpin is in a non-zero mode. See the smartpin documentation for what they do mean in each mode. It would seem from the documentation that IN is raised on every accumulator overflow and drops again when you AKPIN or WRPIN the pin.

    Also, unrelated to your problem, you can replace this:
        if_nc   drvh    #DePin
        if_c    drvl    #DePin
    
    with this:
                drvnc    #DePin
    

    EDIT: ACKPIN -> AKPIN
  • Thanks! Akpin (new name, right?) is what I needed to do. That wasn't so clear...
    This now produces a pulse on DePin every time PClkPin goes low:
    TestLoop            
                nop
                nop
                testp   #PClkPin wc 
                akpin   #PClkPin
                drvc    #DePin                                                      
                nop
                nop
                jmp     #TestLoop
    
    Prop Info and Apps: http://www.rayslogic.com/
  • I may need to try bit-banging the pixel clock too...

    This works fine at 1 MHz, but at 10 MHz only catches every 5th pulse:
    TestLoop            
                testp   #PClkPin wc 
                drvc    #DePin   
                akpin   #PClkPin                                                   
                jmp     #TestLoop
    
    Prop Info and Apps: http://www.rayslogic.com/
  • @rayman

    You can use the smart pin input selector to read the output state of neighbor pins.
    From the smart pin docs:

    D/# = %AAAA_BBBB_FFF_PPPPPPPPPPPPP_TT_MMMMM_0

    %AAAA: ‘A’ input selector

    0xxx = true (default)
    1xxx = inverted
    x000 = this pin’s read state (default)
    x001 = relative +1 pin’s read state
    x010 = relative +2 pin’s read state
    x011 = relative +3 pin’s read state
    x100 = this pin’s OUT bit from cogs
    x101 = relative -3 pin’s read state
    x110 = relative -2 pin’s read state
    x111 = relative -1 pin’s read state
    Here's an example of reading a smart pins output state.
    dat	org
    
    	hubset	#1		'rcslow
    
    	wrpin	#%1_00110_0,#56	'nco frequency mode
    	wxpin	##10000,#56	'base period
    	wypin	##$80000000,#56
    	dirh	#56
    
    	wrpin	##%1111 << 28,#57	'input selector = inverted, pin - 1
    
    	rep	#2,#0			'repeat forever
    	testp	#57 wc			'get pin 56 state
    	drvc	#59			'send inverted state to pin 59
    
    
    Melbourne, Australia
  • @ozpropdev

    I am looking at the smart pin codes. I noted that you wrote:

    wrpin #%1_00110_0,#56 'nco frequency mode
    wxpin ##10000,#56 'base period
    wypin ##$80000000,#56

    This is in the docs:

    D/# = %AAAA_BBBB_FFF_PPPPPPPPPPPPP_TT_MMMMM_0

    I have seen in the forums what you wrote as well as something like this:

    prng = %0000_0000_000_10100_00000000_01_00001_0
    dither = %0000_0000_000_10100_00000000_01_00010_0 ' remember to wypin
    dither_pwm = %0000_0000_000_10100_00000000_01_00011_0 ' remember to wypin
    dac = %0000_0000_000_10100_00000000_00_00000_0

    What is the easiest way or what of the aaaa,bbbb,fff,pppp etc can I leave out?

    Thanks
    “Light thinks it travels faster than anything but it is wrong. No matter how fast light travels, it finds the darkness has always got there first, and is waiting for it.”
    “You only live twice:
    Once when you are born
    And once when you look death in the face”
  • evanhevanh Posts: 8,274
    edited 2019-07-14 - 01:37:14
    The M field, plus the end zero, (the right most six bits) is the smartpin mode select. Everything else is non-smartpin.

    The T field is often needed to force the pin's DIR high when using a smartpin. This is because the cog's DIR is now controlling the smartpin instead of the pin directly.

    The P field is the most complex, it defines the pin config of the custom pins. All the interface attributes like pull-up resistors and switching on the ADC.

    Fields A, B and F work together in selecting digital input sources. Input selector A works for cogs as well but only smartpins can see B. F applies to both A and B.
    We have the vastness of the internet and yet billions of people decided to spend most of their time within a horribly designed, fake-news emporium of a website that sucks every possible piece of personal information out of you so it can sell it to others. And they see nothing wrong with that.
  • pilot0315 wrote: »
    What is the easiest way or what of the aaaa,bbbb,fff,pppp etc can I leave out?

    For clarity all the bit fields were shown.
    You can remove all the leading zeros.
    prng = %10100_00000000_01_00001_0
      dither = %10100_00000000_01_00010_0    ' remember to wypin
      dither_pwm = %10100_00000000_01_00011_0    ' remember to wypin
      dac  = %10100_00000000_00_00000_0
    
    



    Melbourne, Australia
  • @evanh
    @ozpropdev
    Thank you. I will experiment with the information.
    I will let you know.
    “Light thinks it travels faster than anything but it is wrong. No matter how fast light travels, it finds the darkness has always got there first, and is waiting for it.”
    “You only live twice:
    Once when you are born
    And once when you look death in the face”
  • evanhevanh Posts: 8,274
    edited 2019-07-26 - 13:10:53
    Here's my latest "ASCII art" block diagram:
    *****************************************************
    ***   Guide of where WRPIN config bits are used   ***
    *****************************************************
    All cogs share the one-per-pin mode config registers.
    WRPIN   {#}D,{#}S	D/# = %AAAA_BBBB_FFF_PPPPPPPPPPPPP_TT_MMMMM_0
                                             :
                                             :
                                     ----------------------------------------------------------------- RND
                                    |        :
                                    |        :                            COG_DAC (Streamers/Cogs)
                                    |        :          [=============]<----------------------------- cog0
                               Other|        :          [             ]<----------------------------- cog1
                                    |        :          [   DAC bus   ]<----------------------------- cog2
                                    |        :          [   select    ]<----------------------------- cog3
                                    v        :          [             ]<----------------------------- cog4
                           [=============]   : DAC_MODE [             ]<----------------------------- cog5
                           [  Flash DAC  ]<-------------[   (%P...P)  ]<----------------------------- cog6
                           [   Network   ]   :          [    (%TT)    ]<----------------------------- cog7
    [========]             [             ]   :          [  (%MMMMM_0) ]
    [        ]<------------[   (%P...P)  ]   :          [             ]<------------------------------ OUT
    [Physical]             [             ]   :  driveH  [             ]<---------------------------+-- DIR
    [  Even  ]             [             ]<-------------[ Logic Output]                            |
    [  Pin   ]             [  Pin Output ]   :  driveL  [             ] SMART_DAC[============]    |
    [        ]------       [             ]<-------------[             ]<---------[            ]    |
    [========]      |      [=============]   :          [             ] SMART_OUT[            ]<---
                    |            |  ^        :      ----[             ]<---------[            ]
                    |            |  |        :     |    [=============]          [            ]
                    |    COMP_DAC|  |Feed    :     |                             [            ]
                    |            |  |back    :     |                             [   Odd #    ]
                    |            v  |        :  OUT|      -1  -2  -3             [  Smartpin  ]
                    |      [=============]   :     |       |   |   |             [ (%MMMMM_0) ]
                    | PinB [  Comparator ]   :     |       v   v   v             [            ]
                  -------->[             ]   :     |    [=============]      A   [            ]
                 |  | PinA [   (%P...P)  ]   :      --->[ Logic Input ]--------->[---o----o---]-------> IN
                 |  +----->[             ]   :          [  (%A_B_F)   ]      B   [  (M == 0)  ]
                 |  |      [  Pin Input  ]------------->[             ]--------->[            ]
                 |  |      [             ]   :          [=============]          [            ]
                 |  |      [ Sigma-Delta ]   :             ^   ^   ^             [============]
                 |  |      [     ADC     ]   :             |   |   |
                 |  |      [=============]   :            +1  +2  +3
                 |  |                        :
                 |  |                        :
                 |  |                        :                            COG_DAC (Streamers/Cogs)
                 |  |                        :          [=============]<----------------------------- cog0
                 |  |        |\              :          [             ]<----------------------------- cog1
                 |  +--------| |O--- Other   :          [   DAC bus   ]<----------------------------- cog2
                 |  |        |/     |        :          [   select    ]<----------------------------- cog3
                 |  |               v        :          [             ]<----------------------------- cog4
                 |  |      [=============]   : DAC_MODE [             ]<----------------------------- cog5
                 |  |      [  Flash DAC  ]<-------------[   (%P...P)  ]<----------------------------- cog6
                 |  |      [   Network   ]   :          [    (%TT)    ]<----------------------------- cog7
                 |  |      [             ]   :          [  (%MMMMM_0) ]
                 |  |      [   (%P...P)  ]   :          [             ]<------------------------------ OUT
    [========]   |  |      [             ]   :  driveH  [             ]<---------------------------+-- DIR
    [        ]<------------[             ]<-------------[ Logic Output]                            |
    [Physical]   |  |      [  Pin Output ]   :  driveL  [             ] SMART_DAC[============]    |
    [  Odd   ]   |  |      [             ]<-------------[             ]<---------[            ]    |
    [  Pin   ]   |  |      [=============]   :          [             ] SMART_OUT[            ]<---
    [        ]---+  |            |  ^        :      ----[             ]<---------[            ]
    [========]   |  |            |  |        :     |    [=============]          [            ]
                 |  |    COMP_DAC|  |Feed    :     |                             [            ]
                 |  |            |  |back    :     |                             [   Odd #    ]
                 |  |            v  |        :  OUT|      -1  -2  -3             [  Smartpin  ]
                 |  |      [=============]   :     |       |   |   |             [ (%MMMMM_0) ]
                 |  |      [  Comparator ]   :     |       v   v   v             [            ]
                 |  |      [             ]   :     |    [=============]      A   [            ]
                 |  | PinB [   (%P...P)  ]   :      --->[ Logic Input ]--------->[---o----o---]-------> IN
                 |   ----->[             ]   :          [  (%A_B_F)   ]      B   [  (M == 0)  ]
                 |    PinA [  Pin Input  ]------------->[             ]--------->[            ]
                  -------->[             ]   :          [=============]          [            ]
                           [ Sigma-Delta ]   :             ^   ^   ^             [============]
                           [     ADC     ]   :             |   |   |
                           [=============]   :            +1  +2  +3
                                             :
                .......................      :               ..........................
                : Custom I/O Pad Ring :      :               : Synthesised Core Logic :
                '''''''''''''''''''''''      :               ''''''''''''''''''''''''''
    
    


    And to go with it, the P field write up:
    WRPIN   {#}D,{#}S	Write D to mode register of smart pin S[5:0], acknowledge smart pin.
    
       bit 30    25     20   15   10      5     0
            |     |      |    |    |      |     |
    D/# = %AAAA_BBBB_FFF_PPPPPPPPPPPPP_TT_MMMMM_0
    
     2    1    1
     0    5    0
    %PPPPPPPPPPPPP: low-level custom pin control (for engineering sample die)
    
    	common labelling of pin config bits
    		%C = clocked I/O (extra clock for IN and OUT)
    		%I = invert IN output
    		%O = invert OUT input
    		%HHH/LLL = digital out drive strength
    			000: Fast
    			001: 1k5R
    			010: 15kR
    			011: 150kR
    			100: 1mA
    			101: 100uA
    			110: 10uA
    			111: Float
    		PinA is specified pin number
    		PinB is PinA's odd/even pair
    
             0      5    0
    	%0_VVV_CIOHHHLLL = Digital mode (default = %0000000000000)
    		DIR enables PinA digital output
    		%VVV = Digital config
    			000: IN = PinA logic, PinA output from OUT
    			001: IN = PinA logic, PinA output from IN
    			010: IN = PinB logic, PinA output from IN
    			011: IN = PinA schmitt, PinA output from OUT
    			100: IN = PinA schmitt, PinA output from IN
    			101: IN = PinB schmitt, PinA output from IN
    			110: IN = PinA > PinB comparator, PinA output from OUT
    			111: IN = PinA > PinB comparator, PinA output from IN
    
             0     5     0
    	%100_VVV_OHHHLLL = ADC_MODE, first order sigma-delta
    		IN has bitstream, sysclock bitrate, for smartpin mode %01111 (Y=0)
    		OUT is PinA digital output, clocked
    		DIR enables PinA digital output
    		%VVV = ADC config instruction
    			000: GIO, 1x (~5 volt range, centred on VIO/2)
    			001: VIO, 1x       "
    			010: PinB, 1x      "
    			011: PinA, 1x      "
    			100: PinA, 3.16x (~1.58 volt range, centred on VIO/2)
    			101: PinA, 10x   (~0.5 volt range, centred on VIO/2)
    			110: PinA, 31.6x (~0.158 volt range, centred on VIO/2)
    			111: PinA, 100x  (~0.05 volt range, centred on VIO/2)
    
             0      5    0
    	%101_VV_DDDDDDDD = DAC_MODE (%TT = 00 and %MMMMM = 00000), 8-bit flash
    		OUT enables PinA ADC (ADC config %011), sysclocked bitstream on IN
    		DIR enables PinA DAC output
    		%VV = PinA DAC config
    			00: 990 ohm, 3.3 volt range
    			01: 600 ohm, 2.0 volt range
    			10: 123.75 ohm, 3.3 volt range
    			11: 75 ohm, 2.0 volt range
    		%DDDDDDDD = DAC level
    
    		for %TT = %01 and %MMMMM = %00000, %101_VV_xxxxSSSS = COG_DAC mode
    			%SSSS = Cog/streamer select: sets DAC level (registered?)
    
    		for %00000 < %MMMMM < %00100 = SMART_DAC mode
    			DIR/IN are usual smartpin ctrl
    			%DDDDDDDD ignored, smartpin sets DAC level (registered?)
    
    		for %MMMMM >= %00100 or (%TT = %1x and %MMMMM = %00000) = BIT_DAC mode
    			OUT sets DAC level (clocked?, ADC disabled?, IN = ?)
    				0: 0 = GIO level
    				1: %DDDDDDDD
    
             0      5    0
    	%11_VV_CDDDDDDDD = COMP_DAC comparator mode
    		DIR enables PinA digital output
    		%VV = Comparator config
    			00: IN = PinA > D, PinA driven by 1k5R from OUT
    			01: IN = PinA > D, PinA driven by 1k5R from !IN
    			10: IN = PinB > D, PinA driven by 1k5R from IN
    			11: IN = PinB > D, PinA driven by 1k5R from !IN
    		%DDDDDDDD = DAC level for internal analogue compare
    
    

    EDIT: Added DAC paths to block diagram.
    EDIT2: Now shows DAC and ADC and comparator locations.
    EDIT3: Named a separate SMART_OUT after finding that OUT can be looped back as an input while the smartpin is the output without being circular.
    We have the vastness of the internet and yet billions of people decided to spend most of their time within a horribly designed, fake-news emporium of a website that sucks every possible piece of personal information out of you so it can sell it to others. And they see nothing wrong with that.
  • Hey guys I think I am getting it. Let you know.
    Thanks
    “Light thinks it travels faster than anything but it is wrong. No matter how fast light travels, it finds the darkness has always got there first, and is waiting for it.”
    “You only live twice:
    Once when you are born
    And once when you look death in the face”
  • evanh wrote: »
    Here's my latest "ASCII art" block diagram:
    *****************************************************
    ***   Guide of where WRPIN config bits are used   ***
    *****************************************************
    All cogs share the one-per-pin mode config registers.
    WRPIN   {#}D,{#}S	D/# = %AAAA_BBBB_FFF_PPPPPPPPPPPPP_TT_MMMMM_0
                                             :
                                             :
                                     ----------------------------------------------------------------- RND
                                    |        :
                                    |        :                            COG_DAC (Streamers/Cogs)
                                    |        :          [=============]<----------------------------- cog0
                               Other|        :          [             ]<----------------------------- cog1
                                    |        :          [   DAC bus   ]<----------------------------- cog2
                                    |        :          [   select    ]<----------------------------- cog3
                                    v        :          [             ]<----------------------------- cog4
                           [=============]   : DAC_MODE [             ]<----------------------------- cog5
                           [  Flash DAC  ]<-------------[   (%P...P)  ]<----------------------------- cog6
                           [   Network   ]   :          [    (%TT)    ]<----------------------------- cog7
    [========]             [             ]   :          [  (%MMMMM_0) ]
    [        ]<------------[   (%P...P)  ]   :          [             ]<------------------------------ OUT
    [Physical]             [             ]   :  driveH  [             ]<---------------------------+-- DIR
    [  Even  ]             [             ]<-------------[ Logic Output]                            |
    [  Pin   ]             [  Pin Output ]   :  driveL  [             ] SMART_DAC[============]    |
    [        ]------       [             ]<-------------[             ]<---------[            ]    |
    [========]      |      [=============]   :          [             ] SMART_OUT[            ]<---
                    |            |  ^        :      ----[             ]<---------[            ]
                    |            |  |        :     |    [=============]          [            ]
                    |    COMP_DAC|  |Feed    :     |                             [            ]
                    |            |  |back    :     |                             [   Odd #    ]
                    |            v  |        :  OUT|      -1  -2  -3             [  Smartpin  ]
                    |      [=============]   :     |       |   |   |             [ (%MMMMM_0) ]
                    | PinB [  Comparator ]   :     |       v   v   v             [            ]
                  -------->[             ]   :     |    [=============]      A   [            ]
                 |  | PinA [   (%P...P)  ]   :      --->[ Logic Input ]--------->[---o----o---]-------> IN
                 |  +----->[             ]   :          [  (%A_B_F)   ]      B   [  (M == 0)  ]
                 |  |      [  Pin Input  ]------------->[             ]--------->[            ]
                 |  |      [             ]   :          [=============]          [            ]
                 |  |      [ Sigma-Delta ]   :             ^   ^   ^             [============]
                 |  |      [     ADC     ]   :             |   |   |
                 |  |      [=============]   :            +1  +2  +3
                 |  |                        :
                 |  |                        :
                 |  |                        :                            COG_DAC (Streamers/Cogs)
                 |  |                        :          [=============]<----------------------------- cog0
                 |  |        |\              :          [             ]<----------------------------- cog1
                 |  +--------| |O--- Other   :          [   DAC bus   ]<----------------------------- cog2
                 |  |        |/     |        :          [   select    ]<----------------------------- cog3
                 |  |               v        :          [             ]<----------------------------- cog4
                 |  |      [=============]   : DAC_MODE [             ]<----------------------------- cog5
                 |  |      [  Flash DAC  ]<-------------[   (%P...P)  ]<----------------------------- cog6
                 |  |      [   Network   ]   :          [    (%TT)    ]<----------------------------- cog7
                 |  |      [             ]   :          [  (%MMMMM_0) ]
                 |  |      [   (%P...P)  ]   :          [             ]<------------------------------ OUT
    [========]   |  |      [             ]   :  driveH  [             ]<---------------------------+-- DIR
    [        ]<------------[             ]<-------------[ Logic Output]                            |
    [Physical]   |  |      [  Pin Output ]   :  driveL  [             ] SMART_DAC[============]    |
    [  Odd   ]   |  |      [             ]<-------------[             ]<---------[            ]    |
    [  Pin   ]   |  |      [=============]   :          [             ] SMART_OUT[            ]<---
    [        ]---+  |            |  ^        :      ----[             ]<---------[            ]
    [========]   |  |            |  |        :     |    [=============]          [            ]
                 |  |    COMP_DAC|  |Feed    :     |                             [            ]
                 |  |            |  |back    :     |                             [   Odd #    ]
                 |  |            v  |        :  OUT|      -1  -2  -3             [  Smartpin  ]
                 |  |      [=============]   :     |       |   |   |             [ (%MMMMM_0) ]
                 |  |      [  Comparator ]   :     |       v   v   v             [            ]
                 |  |      [             ]   :     |    [=============]      A   [            ]
                 |  | PinB [   (%P...P)  ]   :      --->[ Logic Input ]--------->[---o----o---]-------> IN
                 |   ----->[             ]   :          [  (%A_B_F)   ]      B   [  (M == 0)  ]
                 |    PinA [  Pin Input  ]------------->[             ]--------->[            ]
                  -------->[             ]   :          [=============]          [            ]
                           [ Sigma-Delta ]   :             ^   ^   ^             [============]
                           [     ADC     ]   :             |   |   |
                           [=============]   :            +1  +2  +3
                                             :
                .......................      :               ..........................
                : Custom I/O Pad Ring :      :               : Synthesised Core Logic :
                '''''''''''''''''''''''      :               ''''''''''''''''''''''''''
    
    


    And to go with it, the P field write up:
    WRPIN   {#}D,{#}S	Write D to mode register of smart pin S[5:0], acknowledge smart pin.
    
       bit 30    25     20   15   10      5     0
            |     |      |    |    |      |     |
    D/# = %AAAA_BBBB_FFF_PPPPPPPPPPPPP_TT_MMMMM_0
    
     2    1    1
     0    5    0
    %PPPPPPPPPPPPP: low-level custom pin control (for engineering sample die)
    
    	common labelling of pin config bits
    		%C = clocked I/O (extra clock for IN and OUT)
    		%I = invert IN output
    		%O = invert OUT input
    		%HHH/LLL = digital out drive strength
    			000: Fast
    			001: 1k5R
    			010: 15kR
    			011: 150kR
    			100: 1mA
    			101: 100uA
    			110: 10uA
    			111: Float
    		PinA is specified pin number
    		PinB is PinA's odd/even pair
    
             0      5    0
    	%0_VVV_CIOHHHLLL = Digital mode (default = %0000000000000)
    		DIR enables PinA digital output
    		%VVV = Digital config
    			000: IN = PinA logic, PinA output from OUT
    			001: IN = PinA logic, PinA output from IN
    			010: IN = PinB logic, PinA output from IN
    			011: IN = PinA schmitt, PinA output from OUT
    			100: IN = PinA schmitt, PinA output from IN
    			101: IN = PinB schmitt, PinA output from IN
    			110: IN = PinA > PinB comparator, PinA output from OUT
    			111: IN = PinA > PinB comparator, PinA output from IN
    
             0     5     0
    	%100_VVV_OHHHLLL = ADC_MODE, first order sigma-delta
    		IN has bitstream, sysclock bitrate, for smartpin mode %01111 (Y=0)
    		OUT is PinA digital output, clocked
    		DIR enables PinA digital output
    		%VVV = ADC config instruction
    			000: GIO, 1x (~5 volt range, centred on VIO/2)
    			001: VIO, 1x       "
    			010: PinB, 1x      "
    			011: PinA, 1x      "
    			100: PinA, 3.16x (~1.58 volt range, centred on VIO/2)
    			101: PinA, 10x   (~0.5 volt range, centred on VIO/2)
    			110: PinA, 31.6x (~0.158 volt range, centred on VIO/2)
    			111: PinA, 100x  (~0.05 volt range, centred on VIO/2)
    
             0      5    0
    	%101_VV_DDDDDDDD = DAC_MODE (%TT = 00 and %MMMMM = 00000), 8-bit flash
    		OUT enables PinA ADC (ADC config %011), sysclocked bitstream on IN
    		DIR enables PinA DAC output
    		%VV = PinA DAC config
    			00: 990 ohm, 3.3 volt range
    			01: 600 ohm, 2.0 volt range
    			10: 123.75 ohm, 3.3 volt range
    			11: 75 ohm, 2.0 volt range
    		%DDDDDDDD = DAC level
    
    		for %TT = %01 and %MMMMM = %00000, %101_VV_xxxxSSSS = COG_DAC mode
    			%SSSS = Cog/streamer select: sets DAC level (registered?)
    
    		for %00000 < %MMMMM < %00100 = SMART_DAC mode
    			DIR/IN are usual smartpin ctrl
    			%DDDDDDDD ignored, smartpin sets DAC level (registered?)
    
    		for %MMMMM >= %00100 or (%TT = %1x and %MMMMM = %00000) = BIT_DAC mode
    			OUT sets DAC level (clocked?, ADC disabled?, IN = ?)
    				0: 0 = GIO level
    				1: %DDDDDDDD
    
             0      5    0
    	%11_VV_CDDDDDDDD = COMP_DAC comparator mode
    		DIR enables PinA digital output
    		%VV = Comparator config
    			00: IN = PinA > D, PinA driven by 1k5R from OUT
    			01: IN = PinA > D, PinA driven by 1k5R from !IN
    			10: IN = PinB > D, PinA driven by 1k5R from IN
    			11: IN = PinB > D, PinA driven by 1k5R from !IN
    		%DDDDDDDD = DAC level for internal analogue compare
    
    

    EDIT: Added DAC paths to block diagram.
    EDIT2: Now shows DAC and ADC and comparator locations.
    EDIT3: Named a separate SMART_OUT after finding that OUT can be looped back as an input while the smartpin is the output without being circular.
    Nice! That clears some of my doubts. One DAC and one ADC per pin! That's brutal (in a very good way).

    That made my day! You helped me a lot.

    Kind regards, Samuel Lourenço
  • Nice to hear, thanks.

    True, the prop2 can't be called minimalistic quite like the prop1 was. And the hardware config bits has grown numerous. But the symmetries that the prop1 had are still there, even in the new hardware, leading to plenty of mix and match possibilities.

    We have the vastness of the internet and yet billions of people decided to spend most of their time within a horribly designed, fake-news emporium of a website that sucks every possible piece of personal information out of you so it can sell it to others. And they see nothing wrong with that.
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