How to coordinate with Smartpin in NCO mode? IN not working?
Rayman
Posts: 14,557
I have pin#1 toggling using Smartpin in NCO mode like this:
Then, I'm trying to make pin#0 follow the output using testp on the smartpin like this:
Doesn't work though, seems in on smartpin is always high...
What am I doing wrong?
'Turn on pixel clock
mov x,##SmartMode
wrpin x,#PClkPin
mov x,##$0D '1.2 MHz with $0D, 9.62 MHz with wypin=$8000_0000
wxpin x,#PClkPin
mov x,##$1000_0000'8000_0000 'Toggle every n base period
wypin x,#PClkPin
dirh #PClkPin
Then, I'm trying to make pin#0 follow the output using testp on the smartpin like this:
TestLoop
nop
nop
testp #PClkPin wc
if_nc drvh #DePin
if_c drvl #DePin
nop
nop
jmp #TestLoop
Doesn't work though, seems in on smartpin is always high...
What am I doing wrong?
Comments
Also, unrelated to your problem, you can replace this:
if_nc drvh #DePin if_c drvl #DePinwith this:EDIT: ACKPIN -> AKPIN
This now produces a pulse on DePin every time PClkPin goes low:
TestLoop nop nop testp #PClkPin wc akpin #PClkPin drvc #DePin nop nop jmp #TestLoopThis works fine at 1 MHz, but at 10 MHz only catches every 5th pulse:
TestLoop testp #PClkPin wc drvc #DePin akpin #PClkPin jmp #TestLoopYou can use the smart pin input selector to read the output state of neighbor pins.
From the smart pin docs: Here's an example of reading a smart pins output state.
I am looking at the smart pin codes. I noted that you wrote:
wrpin #%1_00110_0,#56 'nco frequency mode
wxpin ##10000,#56 'base period
wypin ##$80000000,#56
This is in the docs:
D/# = %AAAA_BBBB_FFF_PPPPPPPPPPPPP_TT_MMMMM_0
I have seen in the forums what you wrote as well as something like this:
prng = %0000_0000_000_10100_00000000_01_00001_0
dither = %0000_0000_000_10100_00000000_01_00010_0 ' remember to wypin
dither_pwm = %0000_0000_000_10100_00000000_01_00011_0 ' remember to wypin
dac = %0000_0000_000_10100_00000000_00_00000_0
What is the easiest way or what of the aaaa,bbbb,fff,pppp etc can I leave out?
Thanks
The T field is often needed to force the pin's DIR high when using a smartpin. This is because the cog's DIR is now controlling the smartpin instead of the pin directly.
The P field is the most complex, it defines the pin config of the custom pins. All the interface attributes like pull-up resistors and switching on the ADC.
Fields A, B and F work together in selecting digital input sources. Input selector A works for cogs as well but only smartpins can see B. F applies to both A and B.
For clarity all the bit fields were shown.
You can remove all the leading zeros.
@ozpropdev
Thank you. I will experiment with the information.
I will let you know.
***************************************************** *** Guide of where WRPIN config bits are used *** ***************************************************** All cogs share the one-per-pin mode config registers. WRPIN {#}D,{#}S D/# = %AAAA_BBBB_FFF_PPPPPPPPPPPPP_TT_MMMMM_0 : ....................... : .......................... : Custom I/O Pad Ring : : : Synthesised Core Logic : ''''''''''''''''''''''' : '''''''''''''''''''''''''' : : CogDAC (Streamers/Cogs) : [%%%%%%%%%%%%%]<============================= cog0 : [ ]<============================= cog1 [%%%%%%%%%%%%%] : [ DAC bus ]<============================= cog2 | [ Flash DAC ]<=============================[ select ]<============================= cog3 |<-----[ Network ] : [ ]<============================= cog4 | [ (%P...P) ] : [ (%P...P) ]<============================= cog5 | [ ]<- : [ ]<============================= cog6 | [%%%%%%%%%%%%%] | : [ ]<============================= cog7 | | : [%%%%%%%%%%%%%]<===\\ | | : ^ || | [%%%%%%%%%%%%%] | : | ------------------------------------- RND | [ Logic Drive ]<-+------------- : BitDAC | | Other || [%%%%%%%%] |<-----[ (%P...P) ] | : | v ||SmartDAC [ ] | [ ]<------------- | : [%%%%%%%%%%%%%] || [Physical] | [%%%%%%%%%%%%%] | | : Enable [ ]<------------------------------ OUT [ Even # ]------+ ^ | -------------[ Logic ] || [ Pin Pad] | | | : Output [ Output ]<---------------------------+-- DIR [ ] | ----------- --------+------[ ] || | [%%%%%%%%] | | : | [ (%TT) ] || [%%%%%%%%%%%%] | | | : | [ (%MMMMM_0) ] \\====[ ] | | | : | OUTin[ ] [ Even # ]<--- | [%%%%%%%%%%%%%] | : | ---[ ]<---------[ Smartpin ] (Self) | PinA [ Comparator ] | : | | [%%%%%%%%%%%%%] SmartOUT [ (%MMMMM_0) ] +----->[ & Logic ] | : | | [ ] (Pair) | PinB [ & Schmitt ] | : | | [ (X reg)===]<==== WXPIN -------->[ (%P...P) ]---+ Input : | | -1 -2 -3 [ (Y reg)===]<==== WYPIN | | [ ] | : | | | | | [ (Z reg)===]====> RDPIN | | [%%%%%%%%%%%%%] | : | | v v v [ ] | | | : | | [%%%%%%%%%%%%%] SmartA [ ] | | | [%%%%%%%%] : | -->[ Mux & ]--------->[---o----o---]-------> IN | | [%%%%%%%%%%%%%] -->[ Mux ] : | [ De-glitch ] SmartB [ (M == 0) ] | | [ Sigma-Delta ] [(%P...P)]------------>[ (A_B_F) ]--------->[ ] | +----->[ ADC ]------>[ ] : | [%%%%%%%%%%%%%] [ ]<------ ACK | | [ (%P...P) ] [%%%%%%%%] : | ^ ^ ^ [ USB brain ] | | [%%%%%%%%%%%%%] : | | | | [%%%%%%%%%%%%] | | : | +1 +2 +3 | | : | | | : | | | : | CogDAC (Streamers/Cogs) | | : | [%%%%%%%%%%%%%]<============================= cog0 | | : | [ ]<============================= cog1 | | [%%%%%%%%%%%%%] : | [ DAC bus ]<============================= cog2 | | [ Flash DAC ]<=============================[ select ]<============================= cog3 |<--------[ Network ] : | [ ]<============================= cog4 | | [ (%P...P) ] : __|__ [ (%P...P) ]<============================= cog5 | | [ ]<- : \ / [ ]<============================= cog6 | | [%%%%%%%%%%%%%] | : \ / [ ]<============================= cog7 | | | : O [%%%%%%%%%%%%%]<===\\ | | | : | ^ || | | [%%%%%%%%%%%%%] | : ----------- | || | | [ Logic Drive ]<-+------------- : Other | |BitDAC || SmartDAC [%%%%%%%%] |<--------[ (%P...P) ] | : v | || [ ] | | [ ]<------------- | : [%%%%%%%%%%%%%] || [Physical] | | [%%%%%%%%%%%%%] | | : Enable [ ]<------------------------------ OUT [ Odd # ]---+ | ^ | -------------[ Logic ] || [ Pin Pad] | | | | : Output [ Output ]<---------------------------+-- DIR [ ] | | ----------- ---------------[ ] || | [%%%%%%%%] | | | : [ (%TT) ] || [%%%%%%%%%%%%] | | | | : [ (%MMMMM_0) ] \\====[ ] | | | | : OUTin [ ] [ Odd # ]<--- | | [%%%%%%%%%%%%%] | : ---[ ]<---------[ Smartpin ] (Pair)| | PinB [ Comparator ] | : | [%%%%%%%%%%%%%] SmartOUT [ (%MMMMM_0) ] | ----->[ & Logic ] | : | [ ] (Self)| PinA [ & Schmitt ] | : | [ (X reg)===]<==== WXPIN +-------->[ (%P...P) ]---+ Input : | -1 -2 -3 [ (Y reg)===]<==== WYPIN | [ ] | : | | | | [ (Z reg)===]====> RDPIN | [%%%%%%%%%%%%%] | : | v v v [ ] | | : | [%%%%%%%%%%%%%] SmartA [ ] | | [%%%%%%%%] : -->[ Mux & ]--------->[---o----o---]-------> IN | [%%%%%%%%%%%%%] -->[ Mux ] : [ De-glitch ] SmartB [ (M == 0) ] | [ Sigma-Delta ] [(%P...P)]------------>[ (A_B_F) ]--------->[ ] -------->[ ADC ]------>[ ] : [%%%%%%%%%%%%%] [ ]<------ ACK [ (%P...P) ] [%%%%%%%%] : ^ ^ ^ [ USB passive] [%%%%%%%%%%%%%] : | | | [%%%%%%%%%%%%] : +1 +2 +3 : ....................... : .......................... : Custom I/O Pad Ring : : : Synthesised Core Logic : ''''''''''''''''''''''' : ''''''''''''''''''''''''''And to go with it, the P field write up is here - https://forums.parallax.com/discussion/comment/1452036/#Comment_1452036
EDIT: Added DAC paths to block diagram
EDIT2: Now shows DAC and ADC and comparator locations
EDIT3: Named a separate SMART_OUT after finding that OUT can be looped back as an input while the smartpin is the output without being circular
EDIT4: Typo correction: Was two "odds"
EDIT5: Rearrange "Other"
EDIT6: Updated with corrections after Chip provided more details - https://forums.parallax.com/discussion/comment/1494131/#Comment_1494131
EDIT7: Added X, Y and Z registers to smartpin
EDIT8: Added DAC Enable and smartpin ACK
EDIT9: Updated to latest - https://forums.parallax.com/discussion/comment/1495133/#Comment_1495133
Thanks
That made my day! You helped me a lot.
Kind regards, Samuel Lourenço
True, the prop2 can't be called minimalistic quite like the prop1 was. And the hardware config bits has grown numerous. But the symmetries that the prop1 had are still there, even in the new hardware, leading to plenty of mix and match possibilities.
It would be great if the two blocks could be published as PDF's, they are hard to follow with having to scroll.
To be serious, I have no skills at page layout so anyone is likely better than me at it. The reason I used text was because I was getting frustrated with other drawing software.
Sometimes it's nice to have a printer that can do 11x17 prints. Here are both sections as jpeg's in case that helps.
I love 11x17. I sometimes print Chips assembly instructions on 24x30. Thanks for that.
It is quick and dirty code, but may still be useful.
If errors are found, please report. I only tested it with a few examples.
I built it on Linux, but the cpp should also compile on other platforms.
./confSP %AAAA: ‘A’ input selector 0xxx = true (default) 1xxx = invertedx000 = this pin’s read state (default) x001 = relative +1 pin’s read state x010 = relative +2 pin’s read state x011 = relative +3 pin’s read state x100 = this pin’s OUT bit from cogs x101 = relative -3 pin’s read state x110 = relative -2 pin’s read state x111 = relative -1 pin’s read state input 4bit A - Field (ex. 0101) 0000 %BBBB: ‘B’ input selector 0xxx = true (default) 1xxx = invertedx000 = this pin’s read state (default) x001 = relative +1 pin’s read state x010 = relative +2 pin’s read state x011 = relative +3 pin’s read state x100 = this pin’s OUT bit from cogs x101 = relative -3 pin’s read state x110 = relative -2 pin’s read state x111 = relative -1 pin’s read state input 4bit B - Field (ex. 0101) 0000 %FFF: 'A' and 'B' input logic/filtering (after 'A' and 'B' input selectors) 000 = A, B (default) 001 = A AND B, B 010 = A OR B, B 011 = A XOR B, B 100 = A, B, both filtered using global filt0 settings 101 = A, B, both filtered using global filt1 settings 110 = A, B, both filtered using global filt2 settings 111 = A, B, both filtered using global filt3 settings The resultant 'A' will drive the IN signal in non-smart-pin modes. input 3 bit F -Field 000 %PPPPPPPPPPPPP: low-level custom pin control (for engineering sample die) common labelling of pin config bits %C = clocked I/O (extra clock for IN and OUT) %I = invert IN output %O = invert OUT input %HHH/LLL = digital out drive strength 000: Fast 001: 1k5R 010: 15kR 011: 150kR 100: 1mA 101: 100uA 110: 10uA 111: Float PinA is specified pin number PinB is PinA's odd/even pair %0_VVV_CIOHHHLLL = Digital mode (default = %0000000000000) DIR enables PinA digital output %VVV = Digital config 000: IN = PinA logic, PinA output from OUT 001: IN = PinA logic, PinA output from IN 010: IN = PinB logic, PinA output from IN 011: IN = PinA schmitt, PinA output from OUT 100: IN = PinA schmitt, PinA output from IN 101: IN = PinB schmitt, PinA output from IN 110: IN = PinA > PinB comparator, PinA output from OUT 111: IN = PinA > PinB comparator, PinA output from IN %100_VVV_OHHHLLL = ADC_MODE, first order sigma-delta IN has bitstream, sysclock bitrate, for smartpin mode %01111 (Y=0) OUT is PinA digital output, clocked DIR enables PinA digital output %VVV = ADC config instruction 000: GIO, 1x (~5 volt range, centred on VIO/2) 001: VIO, 1x 010: PinB, 1x 011: PinA, 1x 100: PinA, 3.16x (~1.58 volt range, centred on VIO/2) 101: PinA, 10x (~0.5 volt range, centred on VIO/2) 110: PinA, 31.6x (~0.158 volt range, centred on VIO/2) 111: PinA, 100x (~0.05 volt range, centred on VIO/2) %101_VV_DDDDDDDD = DAC_MODE (%TT = 00 and %MMMMM = 00000), 8-bit flash OUT enables PinA ADC (ADC config %011), sysclocked bitstream on IN DIR enables PinA DAC output %VV = PinA DAC config 00: 990 ohm, 3.3 volt range 01: 600 ohm, 2.0 volt range 10: 123.75 ohm, 3.3 volt range 11: 75 ohm, 2.0 volt range %DDDDDDDD = DAC level for %TT = %01 and %MMMMM = %00000, %101_VV_xxxxSSSS = COG_DAC mode %SSSS = Cog/streamer select: sets DAC level (registered?) for %00000 < %MMMMM < %00100 = SMART_DAC mode DIR/IN are usual smartpin ctrl %DDDDDDDD ignored, smartpin sets DAC level (registered?) for %MMMMM >= %00100 or (%TT = %1x and %MMMMM = %00000) = BIT_DAC mode OUT sets DAC level (clocked?, ADC disabled?, IN = ?) 0: 0 = GIO level 1: %DDDDDDDD %11_VV_CDDDDDDDD = COMP_DAC comparator mode DIR enables PinA digital output %VV = Comparator config 00: IN = PinA > D, PinA driven by 1k5R from OUT 01: IN = PinA > D, PinA driven by 1k5R from !IN 10: IN = PinB > D, PinA driven by 1k5R from IN 11: IN = PinB > D, PinA driven by 1k5R from !IN %DDDDDDDD = DAC level for internal analogue compare input 13 bit P - Field 1011110000000 %TT: pin DIR/OUT control (default = %00) for odd pins, 'OTHER' = NOT lower pin's output state (diff source) for even pins, 'OTHER' = unique pseudo-random bit (noise source) for all pins, 'SMART' = smart pin output which overrides OUT/OTHER 'DAC_MODE' is enabled when P[12:10] = %101 'BIT_DAC' outputs {2{P[7:4]}} for 'high' or {2{P[3:0]}} for 'low' in DAC_MODE for smart pin mode off (%MMMMM = %00000): DIR enables output for non-DAC_MODE: 0x = OUT drives output 1x = OTHER drives output for DAC_MODE: 00 = OUT enables ADC, P[7:0] sets DAC level 01 = OUT enables ADC, P[3:0] selects cog DAC channel 10 = OUT drives BIT_DAC 11 = OTHER drives BIT_DAC for all smart pin modes (%MMMMM > %00000): x0 = output disabled, regardless of DIR x1 = output enabled, regardless of DIR for DAC smart pin modes (%MMMMM = %00001..%00011): 0x = OUT enables ADC in DAC_MODE, P[7:0] overridden 1x = OTHER enables ADC in DAC_MODE, P[7:0] overridden for non-DAC smart pin modes (%MMMMM = %00100..%11111): 0x = SMART/OUT drives output or BIT_DAC if DAC_MODE 1x = SMART/OTHER drives output or BIT_DAC if DAC_MODE input 2 bit T - Field 01 %MMMMM: 00000 = smart pin off (default) 00001 = long repository (P[12:10] != %101) 00010 = long repository (P[12:10] != %101) 00011 = long repository (P[12:10] != %101) 00001 = DAC noise (P[12:10] = %101) 00010 = DAC 16-bit dither, noise (P[12:10] = %101) 00011 = DAC 16-bit dither, PWM (P[12:10] = %101) 00100* = pulse/cycle output 00101* = transition output 00110* = NCO frequency 00111* = NCO duty 01000* = PWM triangle 01001* = PWM sawtooth 01010* = PWM switch-mode power supply, V and I feedback 01011 = periodic/continuous: A-B quadrature encoder 01100 = periodic/continuous: inc on A-rise & B-high 01101 = periodic/continuous: inc on A-rise & B-high / dec on A-rise & B-low 01110 = periodic/continuous: inc on A-rise {/ dec on B-rise} 01111 = periodic/continuous: inc on A-high {/ dec on B-high} 10000 = time A-states 10001 = time A-highs 10010 = time X A-highs/rises/edges -or- timeout a-/high/rise/edge 10011 = for X periods, count time 10100 = for X periods, count states 10101 = for periods in X+ clocks, count time 10110 = for periods in X+ clocks, count states 10111 = for periods in X+ clocks, count periods 11000 = ADC sample/filter/capture, internally clocked 11001 = ADC sample/filter/capture, externally clocked 11010 = ADC scope with trigger 11011* = USB host/device (even/odd pin pair = DM/DP) 11100* = sync serial transmit (A-data, B-clock) 11101 = sync serial receive (A-data, B-clock) 11110* = async serial transmit (baudrate) 11111 = async serial receive (baudrate) * OUT signal overridden input 5 bit M - Field 00011 your input A-FIELD 0000 B-FIELD 0000 F-FIELD 000 P-FIELD 1011110000000 T-FIELD 01 M-FIELD 00011 RESULT (32bit) : %00000000000101111000000001000110 RESULT decimal : 1540166I like to read an analog voltage into P0. I tried a Configuration, but there are many questions what I have is: %AAAA BBBB FFF PPPPPPPPPPPPP TT MMMMM 0 | | |__________ 11000 ADC SAMPLE INTERNAL CLOCKED | |______________ 01 output enabled, regardless of DIR |______________________ 100 001 OHHHLLL | | |__________ what is this ? | |_______________ VIO 1x |__________________ ADC MODE if I have the Configuration wrpin ##CONFIG,#PIN0 '? wxpin ##SAMPLERATE,PIN0'? do I need dirh or dirl do I need setsel ' and how can I do rdpin adc,#PIN0 do I need waitsel must I do any external connection, as I understand SigmaDelta as in and out ? I just don't get it. Reinhard(1): Those bits are for optional digital output drive. Maybe you want to apply a current bias to the ADC frontend.
(2): No for pin config to take effect. Yes, a high DIR is needed for smartpin to run (A low on DIR holds the smartpin in reset). If you just wanted the raw ADC bitstream appearing on IN, then leave the smartpin mode off (M=0) and DIR should stay low unless you want the output driven. Mostly you'll be wanting the smartpin to consume the bitstream though.
Additionally, a DIRL/DIRH pair are usually placed around any smartpin initialising code to neuter potential strange behaviour on initial mode change. Although, I have used a non-typical order to ensure the output stays driven when engaging a smartpin, but still providing the smartpin resetting function.
(3) and (5): No, SETSE1/2/3 are only if you want to make use of the hardware event system.
(4): Yep, RDPIN is how to read data for all smartpins. That's where the ADC's smartpin samples appear.
(6): Nothing extra for ADC function. With the Prop2, all the sigma-delta hardware is built in. The input voltage range is limited to -0.3 to 3.6 Volts though.
Thanks for the link and the information it contains.
I've tried a lot, but the result is always similar:
It doesn't matter whether I leave the pin open, connect it to GND or to VIO.
my current attempt:
#include <stdio.h> #include <propeller2.h> #include <math.h> #include <stdlib.h> #include <unistd.h> #define P2_TARGET_MHZ 160 #include "sys/p2es_clock.h" #define BAUD 230400 #define PIN0 0 #define PIN1 1 #define PIN2 2 #define SYSTEM_CLOCK (_CLOCKFREQ) #define SAMPLE_RATE 8000 #define SAMPLE_PERIOD SYSTEM_CLOCK / SAMPLE_RATE // CPU cycles between sample updates /* A-FIELD 0000 B-FIELD 0000 F-FIELD 000 P-FIELD 1001000000000 T-FIELD 01 M-FIELD 11000 RESULT (32bit) : %00000000000100100000000001110000 RESULT decimal : 1179760 */ #define CONFIG 1179760 void main () { int x1=0; int diff1=0; int diff1a=0; clkset(_SETFREQ, _CLOCKFREQ); _setbaud(BAUD); sleep(1); __asm { wrpin ##CONFIG, #PIN0 wxpin ##SAMPLE_PERIOD, #PIN0 dirh #PIN0 }; while(1) { __asm{ rdpin x1,#PIN0 //sub x1, diff1 //add diff1, x1 //sub x1, diff1a //add diff1a, x1 //shr x1, #7 }; printf("%d \n",x1); sleep(1); }//while }//mainI use about 20cm long laboratory cables to connect the pin to VIO / GND. Can it be that the converter is so sensitive and that the line induces something?
Another problem is %TT should be %00, %01 means the output is driven low to GIO voltage. This is reflected in the ADC readings when pin input is selected. Also, I'm guessing you didn't want x3.16 gain setting in the P bits. I'm thinking you were aiming for VIO selected instead. ie:
Please be patient with me. I used the above settings and set the sample period to 8 / 10 / 6.
I switched a potentiometer between VIO and GND. The middle tap goes to P0. With a voltmeter at P0, I set a voltage of almost 0 to 1500 mV.
Nothing changes in the result, a value (432) is constantly output via printf.
What else can I do wrong?
// C Tests - ADC #include <stdio.h> #include <propeller2.h> #define P2_TARGET_MHZ 160 #include "sys/p2es_clock.h" #define BAUD 230400 #define ADC 11 // --\ Pins #define DAC 13 // --/ connected together void pinconfig(int pin, int mode, int x, int y) { _dirl(pin); _wrpin(pin,mode); _wxpin(pin,x); _wypin(pin,y); _pinl(pin); } void main() { int v, v0, v3, da; clkset(_SETFREQ, _CLOCKFREQ); _setbaud(BAUD); pinconfig(ADC, 0b100000_0000000_00_11000_0, 9, 0); // ADC10bit GND ref _waitx(_CLOCKFREQ/100); v0 = _rdpin(ADC); pinconfig(ADC, 0b100001_0000000_00_11000_0, 9, 0); // ADC10bit VCC ref _waitx(_CLOCKFREQ/100); v3 = _rdpin(ADC); pinconfig(ADC, 0b100011_0000000_00_11000_0, 9, 0); // ADC10bit Ainp da = 0x4000; pinconfig(DAC, 0b10100_00000000_01_00010_0, 1, da); // DAC16bit dither while(1) { _waitx(_CLOCKFREQ/10); v = _rdpin(ADC); //read ADC _wypin(DAC,da); //write DAC da = (da + 128) & 0xFFFF; //ramp up DAC value printf("ADval = %d mV\n",(v-v0)*3300/(v3-v0)); } }Andy
It works great!
I tried it out right now, then I look into the sources to learn how to do it.
Thanks for this example, Andy!
Reinhard
I have the config function
_dirl / _wypin / _pinl
not used.
And probably the biggest mistake:
I have not specified GND-ref and VCC-ref.
I have learned more from your example than from blind testing in the last 2 days.
Reinhard