P2 Tricks, Traps & Differences between P1 (Reference Material Only)

Cluso99 · 2018-10-06 - 06:16:33

Please keep this thread as a reference

Any corrections, additions and discussions can be done in the thread linked here...
forums.parallax.com/discussion/167812/p2-tricks-traps-differences-between-p1-discussion/p1?new=1

Cluso99 · 2018-10-06 - 06:18:11

Here is a table of P1 vs P2 PASM Instructions

        P1:                         Z    C            P2:                          Z    C
'------------------------------------------------------------------------------------------------------------------------------------------                             
        xxx     d,PAR                                 xxx     d,PTRA                               *****  needs to be set by SETQ before COGINIT
                    {wc,wz/wz,wc}                                 {wcz}                            *****
                    {nr}                                                                           *****  no equivalent
        NOP     d,s {wc,wz}         ---  ---                                                       *****  no real equivalent
                                    
        AND     d,s {wc,wz}         R=0  P            AND      d,s {wc,wz}         R=0  P
        ANDN    d,s {wc,wz}         R=0  P            ANDN     d,s {wc,wz}         R=0  P
        OR      d,s {wc,wz}         R=0  P            OR       d,s {wc,wz}         R=0  P
        XOR     d,s {wc,wz}         R=0  P            XOR      d,s {wc,wz}         R=0  P
        MUXC    d,s {wc,wz}         R=0  P            MUXC     d,s {wc,wz}         R=0  P
        MUXNC   d,s {wc,wz}         R=0  P            MUXNC    d,s {wc,wz}         R=0  P
        MUXNZ   d,s {wc,wz}         R=0  P            MUXNZ    d,s {wc,wz}         R=0  P
        MUXZ    d,s {wc,wz}         R=0  P            MUXZ     d,s {wc,wz}         R=0  P
        TEST    d,s {wc,wz}         R=0  P            TEST     d,s {wc,wz}         R=0  P 
        TESTN   d,s {wc,wz}         R=0  P            TESTN    d,s {wc,wz}         R=0  P 
        ABS     d,s {wc,wz}         R=0  S31          ABS      d,s {wc,wz}         R=0  S31
        NEG     d,s {wc,wz}         R=0  S31          NEG      d,s {wc,wz}         R=0  R31*
        ABSNEG  d,s {wc,wz}         R=0  S31       // ABS      d,s {wc}                 S31
                                                   \\ NEG      s      {wz}         R=0
        NEGC    d,s {wc,wz}         R=0  S31          NEGC     d,s {wc,wz}         R=0  R31*       *****
        NEGNC   d,s {wc,wz}         R=0  S31          NEGNC    d,s {wc,wz}         R=0  R31*       *****
        NEGNZ   d,s {wc,wz}         R=0  S31          NEGNZ    d,s {wc,wz}         R=0  R31*       *****
        NEGZ    d,s {wc,wz}         R=0  S31          NEGZ     d,s {wc,wz}         R=0  R31*       *****
                                                      NOT      d,s {wc,wz}         R=0  R31*   
        MOV     d,s {wc,wz}         R=0  S31          MOV      d,s {wc,wz}         R=0  S31
        ROL     d,s {wc,wz}         R=0  D31          ROL      d,s {wc,wz}         R=0  C = last bit shifted out if S[4:0] > 0, else D[31]
        RCL     d,s {wc,wz}         R=0  D31          RCL      d,s {wc,wz}         R=0  C = last bit shifted out if S[4:0] > 0, else D[31]
        SHL     d,s {wc,wz}         R=0  D31          SHL      d,s {wc,wz}         R=0  C = last bit shifted out if S[4:0] > 0, else D[31]
                d,s {wc,wz}                           SAL      d,s {wc,wz}         R=0  C = last bit shifted out if S[4:0] > 0, else D[31]
        ROR     d,s {wc,wz}         R=0  D0           ROR      d,s {wc,wz}         R=0  C = last bit shifted out if S[4:0] > 0, else D[0]
        RCR     d,s {wc,wz}         R=0  D0           RCR      d,s {wc,wz}         R=0  C = last bit shifted out if S[4:0] > 0, else D[0]
        SHR     d,s {wc,wz}         R=0  D0           SHR      d,s {wc,wz}         R=0  C = last bit shifted out if S[4:0] > 0, else D[0]
        SAR     d,s {wc,wz}         R=0  D0           SAR      d,s {wc,wz}         R=0  C = last bit shifted out if S[4:0] > 0, else D[0]
        REV     d,s {wc,wz}         R=0  D0        // REV      d,s {wc,wz}         R=0  C = last bit shifted out if S[4:0] > 0, else D[0]  ?????
                                                   \\ ZEROX                                                                                ?????
                                                                                        
        ADD     d,s {wc,wz}         R=0  C             ADD     d,s {wc,wz}         R=0  C        
        SUB     d,s {wc,wz}         R=0  D<S           SUB     d,s {wc,wz}         R=0  D<S            
        CMP     d,s {wc,wz}         D=S  D<S           CMP     d,s {wc,wz}         D=S  D<S    
                                                       SUBR    d,s {wc,wz}         R=0  D>S
                                                       CMPR    d,s {wc,wz}         D=S  D>S
        CMPSUB  d,s {wc,wz}         D=S  D=>S          CMPSUB  d,s {wc,wz}         D=S  D=>S   
*** ADDABS: if S -ve: C=!UB(D-S) SUBABS: if S -ve: C=!UC(D+S)
        ADDABS  d,s {wc,wz}         R=0  UC***                                                     *****
        SUBABS  d,s {wc,wz}         R=0  UB***                                                     *****
        ADDS    d,s {wc,wz}         R=0  SO            ADDS    d,s {wc,wz}         R=0  SO         ?????
        SUBS    d,s {wc,wz}         R=0  SO            SUBS    d,s {wc,wz}         R=0  SO         ?????
        CMPS    d,s {wc,wz}         D=S  D<S           CMPS    d,s {wc,wz}         D=S  D<S        ?????
        ADDX    d,s {wc,wz} Z&(D+S+C=0)  UC            ADDX    d,s {wc,wz} Z&(D+S+C=0)  UC         ?????
        SUBX    d,s {wc,wz}         R=0  UB            SUBX    d,s {wc,wz}         R=0  UB         ?????
        CMPX    d,s {wc,wz}   Z&(D=S+C)  U(D<S+C)      CMPX    d,s {wc,wz}   Z&(D=S+C)  U(D<S+C)   ?????
        ADDSX   d,s {wc,wz} Z&(D+S+C=0)  SO            ADDSX   d,s {wc,wz} Z&(D+S+C=0)  R31*       ?????
        SUBSX   d,s {wc,wz}         R=0  SO            SUBSX   d,s {wc,wz}         R=0  R31*       ?????
        CMPSX   d,s {wc,wz}   Z&(D=S+C)  S(D<S+C)      CMPSX   d,s {wc,wz}   Z&(D=S+C)  S(D<S+C)   ?????
        SUMC    d,s {wc,wz}         R=0  SO            SUMC    d,s {wc,wz}         R=0  R31*       ?????
        SUMNC   d,s {wc,wz}         R=0  SO            SUMNC   d,s {wc,wz}         R=0  R31*       ?????
        SUMNZ   d,s {wc,wz}         R=0  SO            SUMNZ   d,s {wc,wz}         R=0  R31*       ?????
        SUMZ    d,s {wc,wz}         R=0  SO            SUMZ    d,s {wc,wz}         R=0  R31*       ?????
        MAX     d,s {wc,wz}         S=0  D<S           FLE     d,s {wc,wz}         S=0  D<S    
        MAXS    d,s {wc,wz}         S=0  D<S           FLES    d,s {wc,wz}         S=0  D<S    
        MIN     d,s {wc,wz}         S=0  D<S           FGE     d,s {wc,wz}         S=0  D<S    
        MINS    d,s {wc,wz}         S=0  D<S           FGES    d,s {wc,wz}         S=0  D<S    
                
        MOVS    d,s {wc,wz}         R=0  ---          SETS     d,s                 ---  ---        *****                    \ 2 instruction pipeline
        MOVD    d,s {wc,wz}         R=0  ---          SETD     d,s                 ---  ---        *****                    |
        MOVI    d,s {wc,wz}         R=0  ---          SETR     d,s                 ---  ---        *****  sets iiiiiii-cz   /

        JMPRET  d,s {wc,wz}         R=0  ---                                                       ?????
        CALL    s   {wc,wz}         R=0  ---                                                       ?????
        JMP     s   {wc,wz}         R=0  ---                                                       ?????
        RET     s   {wc,wz}         R=0  ---                                                       ?????
        DJNZ    d,s {wc,wz}         R=0  UB            DJNZ    d,s                                 *****
        TJNZ    d,s {wc,wz}         R=0  0             TJNZ    d,s                                 *****
        TJZ     d,s {wc,wz}         R=0  0             TJZ     d,s                                 *****

        HUBOP   s   {wc,wz}        ???  ???            HUBOP   d                                   ?????
        CLKSET  s   {wc,wz}        ---  ---                                                        ?????
                                                    // SETQ    d                                   ***** D-->PTRA
        COGINIT s   {wc,wz}        ID=0  no-free    \\ COGINIT d,s {wc}           ---   no-free    ***** S-->PC
        COGSTOP s   {wc,wz}        ID=0  no-free       COGSTOP d                  ---   ---        *****
        COGID   s   {wc,wz}        ID=0  0             COGID   d                  ---   ---        *****  this cog
                                                       COGID   d   {wc}           ---   running    *****  running?
        LOCKNEW s   {wc,wz}        ID=0  no-free       LOCKNEW d   {wc}           ---   no-free    *****
        LOCKRET s   {wc,wz}        ID=0  no-free       LOCKRET d                  ---   ---        *****
        LOCKSET s   {wc,wz}        ID=0  prev          LOCKTRY d   {wc}           ---   obtained   *****  C is reversed to P1
        LOCKCLR s   {wc,wz}        ID=0  prev          LOCKREL d   {wc}           ---   prev       *****

        WAITCNT d,s {wc,wz}        R=0  UC             WAITX   d                                   ***** {wc,wz}=d+rnd?

        WAITPEQ d,s {wc,wz}        ---  ---         // SETPAT  d,s                                 *****  D=mask,S=value   Z=!D ???
        WAITPNE d,s {wc,wz}        ---  ---         \\ WAITPAT       {wc,wz}                       ***** {wc,wz}???
        WAITVID d,s {wc,wz}      D+S=0  UO                                                         *****

        RDBYTE  d,s {wc,wz}        R=0  ---            RDBYTE  d,s/p {wc,wz}      R=0  R7*         *****
        RDWORD  d,s {wc,wz}        R=0  ---            RDWORD  d,s/p {wc,wz}      R=0  R15*        *****
        RDLONG  d,s {wc,wz}        R=0  ---            RDLONG  d,s/p {wc,wz}      R=0  R31*        *****  SETQ for block xfer
        WRBYTE  d,s {wc,wz}        ---  ---            WRBYTE  d,s/p              ---  ---         *****
        WRWORD  d,s {wc,wz}        ---  ---            WRWORD  d,s/p              ---  ---         *****
        WRLONG  d,s {wc,wz}        ---  ---            WRLONG  d,s/p              ---  ---         *****  SETQ for block xfer
'------------------------------------------------------------------------------------------------------------------------------------------                             
COG Register Layout:
$000..$1EF                                             RAM           general-use code/data registers
$1F0    PAR                                            RAM / IJMP3   interrupt call   address for INT3
$1F1    CNT                                            RAM / IRET3   interrupt return address for INT3
$1F2    INA                                            RAM / IJMP2   interrupt call   address for INT2
$1F3    INB                                            RAM / IRET2   interrupt return address for INT2
$1F4    OUTA                                           RAM / IJMP1   interrupt call   address for INT1
$1F5    OUTB                                           RAM / IRET1   interrupt return address for INT1
$1F6    DIRA                                           RAM / PA      CALLD-imm return, CALLPA parameter, or LOC address
$1F7    DIRB                                           RAM / PB      CALLD-imm return, CALLPB parameter, or LOC address
$1F8    CTRA                                           PTRA          pointer A to hub RAM
$1F9    CTRB                                           PTRB          pointer B to hub RAM
$1FA    FRQA                                           DIRA          output enables for P31..P0
$1FB    FRQB                                           DIRB          output enables for P63..P32
$1FC    PHSA                                           OUTA          output states for P31..P0
$1FD    PHSB                                           OUTB          output states for P63..P32
$1FE    VCFG                                           INA *         input states for P31..P0     * also debug interrupt call address
$1FF    VSCL                                           INB **        input states for P63..P32   ** also debug interrupt return address
'------------------------------------------------------------------------------------------------------------------------------------------

Cluso99 · 2018-10-06 - 08:04:23

LOCKTRY

In P1...
LOCKSET D WC returns C=previous lock setting ie C=1=previously set

In P2
LOCKTRY D WC returns C=1=obtained lock Note the reversed result

This is opposite to P1, and also differs from
LOCKNEW D WC returns C=1=no lock available

Cluso99 · 2018-10-06 - 08:06:28

JMP & CALL Relative & Direct COG/LUT/HUB Addressing

Here is the definitive example from Chip

https://forums.parallax.com/discussion/comment/1438380/#Comment_1438380

Cluso99 · 2018-10-06 - 08:08:04

SKIP

Here is a solution to skipping instructions without using condition codes...

case1           mov     cmdtype,          #1            ' returns w /CS=0(enabled)
                jmp     #cmdxx
case2           mov 	cmdtype,          #0            ' returns w /CS=1(disabled)
cmdxx           outl    #sd_cs                          '/ /CS=0(enabled) 
.....
                skip    cmdtype                         '| skips next instr if #1
                outh    #sd_cs                          '/ /CS=1(disable) if reqd

Acknowledgement to PeterJ

Cluso99 · 2018-10-06 - 08:09:28

Checking for valid characters in a table

I noticed this very smart coding trick Chip used in checking for a hex character (0..9, A..F, a..f).
Code and table must be in cog.
I also found a shorter way to convert it to a binary nibble.

hexchrs		long	%00000000_00000000_00000000_00000000
		long	%00000011_11111111_00000000_00000000		'"0".."9"
		long	%00000000_00000000_00000000_01111110		'"A".."F"
		long	%00000000_00000000_00000000_01111110		'"a".."f"
		long	%00000000_00000000_00000000_00000000
		long	%00000000_00000000_00000000_00000000
		long	%00000000_00000000_00000000_00000000
		long	%00000000_00000000_00000000_00000000

.check		altb	x,#hexchrs		'check for hex
		testb	0,x		wc
	if_nc	ret				'if not hex, c=0
                testbn  x,#6            wz      'hex, "0".."9"?
        if_nz   add     x,#9                    '..make low nibble $A..$F
        _ret_   and     x,#$F                   'extract low nibble, return c=1

The add x,#9 converts "A..F" to "J..O" and "a..f" to "j..o". "J" is ascii $4A and "j" is ascii $6A.
Then we strip off the upper nibble from both the "0..9" and "J..O"/"j..o" leaving $00..$0F"

While it's shorter code to first check for ASCII $80 and above, rather than using the 8 long table we could use a 4 long table. This would save 2 longs.
However, Chip is looking for the fastest code.

Cluso99 · 2018-10-06 - 08:09:56

RDWORD, RDLONG, WRWORD, WRLONG Hub non-aligned

The P1 ignores lowest hub address bit(s) for non-aligned hub reads and writes.
The P2 correctly accesses non-aligned word and long reads and writes.

In the P1, there were tricks associated with the lower hub address bit(s) being ignored. This code will fail on P2.

Cluso99 · 2018-10-06 - 08:12:57

WAITCTn

In P1 we did this...

                mov     count,            #(96*2)
                mov     delay,            cnt           
                add     delay,            delay5us      
:loop           waitcnt delay,            delay5us      
                'do something
                djnz    count,            #:loop

In P2 we do this...

                mov     count,            #(96*2)
                getct   delay                             
.loop           addct1  delay,            delay5us                
                waitct1                                          
                'do something
                djnz    count,            #.loop

And here is the trap: Our P1 code incorrectly converted to P2

                mov     count,            #(96*2)
                getct   delay                             
                addct1  delay,            delay5us                
.loop           waitct1                                          
                'do something
                djnz    count,            #.loop

Note we need to include the addct1 instruction into the loop because waitcnt no longer adds to the count

WAITX D/#
An alternative to just wait n+2 clocks is the WAITX instruction.

Cluso99 · 2018-10-07 - 07:19:10

Here is the Instruction Set Summary v32i used in the current prototype chips...

Propeller P2X8C4M46P Instructions v32i Sep2018
Cond Opcode  CZ I Dest       Source     Instr00 01      10      11        Operand(s)                                                   Flags
--------------------------------------------------------------------------------------------------------------------------------------------------
EEEE 00000ff CZ I DDDDDDDDD  SSSSSSSSS  ROR     ROL     SHR     SHL       D,{#}S {WC/WZ/WCZ}                                           CZ CZ CZ CZ 
EEEE 00001ff CZ I DDDDDDDDD  SSSSSSSSS  RCR     RCL     SAR     SAL       D,{#}S {WC/WZ/WCZ}                                           CZ CZ CZ CZ 
EEEE 00010ff CZ I DDDDDDDDD  SSSSSSSSS  ADD     ADDX    ADDS    ADDSX     D,{#}S {WC/WZ/WCZ}                                           CZ CZ CZ CZ 
EEEE 00011ff CZ I DDDDDDDDD  SSSSSSSSS  SUB     SUBX    SUBS    SUBSX     D,{#}S {WC/WZ/WCZ}                                           CZ CZ CZ CZ 
EEEE 00100ff CZ I DDDDDDDDD  SSSSSSSSS  CMP     CMPX    CMPS    CMPSX     D,{#}S {WC/WZ/WCZ}                                           CZ CZ CZ CZ 
EEEE 00101ff CZ I DDDDDDDDD  SSSSSSSSS  CMPR    CMPM    SUBR    CMPSUB    D,{#}S {WC/WZ/WCZ}                                           CZ CZ CZ CZ 
EEEE 00110ff CZ I DDDDDDDDD  SSSSSSSSS  FGE     FLE     FGES    FLES      D,{#}S {WC/WZ/WCZ}                                           CZ CZ CZ CZ 
EEEE 00111ff CZ I DDDDDDDDD  SSSSSSSSS  SUMC    SUMNC   SUMZ    SUMNZ     D,{#}S {WC/WZ/WCZ}                                           CZ CZ CZ CZ 
EEEE 01000ff CZ I DDDDDDDDD  SSSSSSSSS  TESTB   TESTBN  TESTB   TESTBN    D,{#}S WC/WZ;D,{#}S WC/WZ;D,{#}S ANDC/ANDZ;D,{#}S ANDC/ANDZ  CZ CZ CZ CZ 
EEEE 01001ff CZ I DDDDDDDDD  SSSSSSSSS  TESTB   TESTBN  TESTB   TESTBN    D,{#}S ORC/ORZ;D,{#}S ORC/ORZ;D,{#}S XORC/XORZ;D,{#}S XORC/X CZ CZ CZ CZ 
EEEE 01000ff CZ I DDDDDDDDD  SSSSSSSSS  BITL    BITH    BITC    BITNC     D,{#}S {WCZ}                                                 CZ CZ CZ CZ 
EEEE 01001ff CZ I DDDDDDDDD  SSSSSSSSS  BITZ    BITNZ   BITRND  BITNOT    D,{#}S {WCZ}                                                 CZ CZ CZ CZ 
EEEE 01010ff CZ I DDDDDDDDD  SSSSSSSSS  AND     ANDN    OR      XOR       D,{#}S {WC/WZ/WCZ}                                           CZ CZ CZ CZ 
EEEE 01011ff CZ I DDDDDDDDD  SSSSSSSSS  MUXC    MUXNC   MUXZ    MUXNZ     D,{#}S {WC/WZ/WCZ}                                           CZ CZ CZ CZ 
EEEE 01100ff CZ I DDDDDDDDD  SSSSSSSSS  MOV     NOT     ABS     NEG       D,{#}S {WC/WZ/WCZ}                                           CZ CZ CZ CZ 
EEEE 01101ff CZ I DDDDDDDDD  SSSSSSSSS  NEGC    NEGNC   NEGZ    NEGNZ     D,{#}S {WC/WZ/WCZ}                                           CZ CZ CZ CZ 
EEEE 01110ff CZ I DDDDDDDDD  SSSSSSSSS  INCMOD  DECMOD  ZEROX   SIGNX     D,{#}S {WC/WZ/WCZ}                                           CZ CZ CZ CZ 
EEEE 01111ff CZ I DDDDDDDDD  SSSSSSSSS  ENCOD   ONES    TEST    TESTN     D,{#}S {WC/WZ/WCZ}                                           CZ CZ CZ CZ 
EEEE 1000ffN NN I DDDDDDDDD  SSSSSSSSS  SETNIB  GETNIB  ROLNIB            D,{#}S,#N                                                    -- -- --    
EEEE 100011f NN I DDDDDDDDD  SSSSSSSSS  SETBYTE GETBYTE ROLBYTE           D,{#}S,#N                                                    -- -- --    
EEEE 1001001 fn I DDDDDDDDD  SSSSSSSSS  SETWORD GETWORD ROLWORD           D,{#}S,#N                                                    -- -- --    
EEEE 1001010 10 I DDDDDDDDD  SSSSSSSSS  ALTSN   ALTGN                     D,{#}S                                                       -- --       
EEEE 1001011 ff I DDDDDDDDD  SSSSSSSSS  ALTSB   ALTGB   ALTSW   ALTGW     D,{#}S                                                       -- -- -- -- 
EEEE 1001100 ff I DDDDDDDDD  SSSSSSSSS  ALTR    ALTD    ALTS    ALTB      D,{#}S                                                       -- -- -- -- 
EEEE 1001101 ff I DDDDDDDDD  SSSSSSSSS  ALTI    SETR    SETD    SETS      D,{#}S                                                       -- -- -- -- 
EEEE 1001110 ff I DDDDDDDDD  SSSSSSSSS  DECOD   BMASK   CRCBIT  CRCNIB    D,{#}S                                                       -- -- -- -- 
EEEE 1001111 ff I DDDDDDDDD  SSSSSSSSS  MUXNITS MUXNIBS MUXQ    MOVBYTS   D,{#}S                                                       -- -- -- -- 
EEEE 101000f fZ I DDDDDDDDD  SSSSSSSSS  MUL     MULS    SCA     SCAS      D,{#}S {WZ}                                                  -Z -Z -Z -Z 
EEEE 1010010 ff I DDDDDDDDD  SSSSSSSSS  ADDPIX  MULPIX  BLNPIX  MIXPIX    D,{#}S                                                       -- -- -- -- 
EEEE 1010011 ff I DDDDDDDDD  SSSSSSSSS  ADDCT1  ADDCT2  ADDCT3  WMLONG    D,{#}S;D,{#}S;D,{#}S;D,{#}S/P                                -- -- -- -- 
EEEE 1010100 Cf I DDDDDDDDD  SSSSSSSSS  RQPIN   RDPIN                     D,{#}S {WC}                                                  C- C-       
EEEE 1010fff CZ I DDDDDDDDD  SSSSSSSSS  RDLUT   RDBYTE  RDWORD  RDLONG    D,{#}S {WC/WZ/WCZ};D,{#}S/P {WC/WZ/WCZ};D,{#}S/P {WC/WZ/WCZ} CZ CZ CZ CZ 
EEEE 1011010 fL I DDDDDDDDD  SSSSSSSSS  CALLPA  CALLPB                    {#}D,{#}S                                                    -- --       
EEEE 1011011 ff I DDDDDDDDD  SSSSSSSSS  DJZ     DJNZ    DJF     DJNF      D,{#}S                                                       -- -- -- -- 
EEEE 1011100 ff I DDDDDDDDD  SSSSSSSSS  IJZ     IJNZ    TJZ     TJNZ      D,{#}S                                                       -- -- -- -- 
EEEE 1011101 ff I DDDDDDDDD  SSSSSSSSS  TJF     TJNF    TJS     TJNS      D,{#}S                                                       -- -- -- -- 
EEEE 1011110 ff I DDDDDDDDD  SSSSSSSSS  TJV                               D,{#}S                                                       --          
EEEE 1011110 01 I 0000000ff  SSSSSSSSS  JINT    JCT1    JCT2    JCT3      {#}S                                                         -- -- -- -- 
EEEE 1011110 01 I 0000001ff  SSSSSSSSS  JSE1    JSE2    JSE3    JSE4      {#}S                                                         -- -- -- -- 
EEEE 1011110 01 I 0000010ff  SSSSSSSSS  JPAT    JFBW    JXMT    JXFI      {#}S                                                         -- -- -- -- 
EEEE 1011110 01 I 0000011ff  SSSSSSSSS  JXRO    JXRL    JATN    JQMT      {#}S                                                         -- -- -- -- 
EEEE 1011110 01 I 0000100ff  SSSSSSSSS  JNINT   JNCT1   JNCT2   JNCT3     {#}S                                                         -- -- -- -- 
EEEE 1011110 01 I 0000101ff  SSSSSSSSS  JNSE1   JNSE2   JNSE3   JNSE4     {#}S                                                         -- -- -- -- 
EEEE 1011110 01 I 0000110ff  SSSSSSSSS  JNPAT   JNFBW   JNXMT   JNXFI     {#}S                                                         -- -- -- -- 
EEEE 1011110 01 I 0000111ff  SSSSSSSSS  JNXRO   JNXRL   JNATN   JNQMT     {#}S                                                         -- -- -- -- 
EEEE 101111f fL I DDDDDDDDD  SSSSSSSSS  <empty> <empty> SETPAT            {#}D,{#}S                                                    -- -- --    
EEEE 110000f fL I DDDDDDDDD  SSSSSSSSS  WRPIN   WXPIN   WYPIN   WRLUT     {#}D,{#}S                                                    -- -- -- -- 
EEEE 110001f fL I DDDDDDDDD  SSSSSSSSS  WRBYTE  WRWORD  WRLONG  RDFAST    {#}D,{#}S/P;{#}D,{#}S/P;{#}D,{#}S/P;{#}D,{#}S                -- -- -- -- 
EEEE 110010f fL I DDDDDDDDD  SSSSSSSSS  WRFAST  FBLOCK  XINIT   XZERO     {#}D,{#}S                                                    -- -- -- -- 
EEEE 1100110 fL I DDDDDDDDD  SSSSSSSSS  XCONT   REP                       {#}D,{#}S                                                    -- --       
EEEE 1100111 CL I DDDDDDDDD  SSSSSSSSS  COGINIT                           {#}D,{#}S {WC}                                               C-          
EEEE 110100f fL I DDDDDDDDD  SSSSSSSSS  QMUL    QDIV    QFRAC   QSQRT     {#}D,{#}S                                                    -- -- -- -- 
EEEE 1101010 fL I DDDDDDDDD  SSSSSSSSS  QROTATE QVECTOR                   {#}D,{#}S                                                    -- --       
EEEE 1101011 00 L DDDDDDDDD  0000000ff  HUBSET  COGID   COGSTOP LOCKNEW   {#}D;{#}D {WC};{#}D;D {WC}                                   -- C- -- C- 
EEEE 1101011 C0 0 DDDDDDDDD  0000001ff  LOCKNEW LOCKRET LOCKTRY LOCKREL   D {WC};{#}D;{#}D {WC};{#}D {WC}                              C- -- C- C- 
EEEE 1101011 CZ 0 DDDDDDDDD  0000100ff  RFBYTE  RFWORD  RFLONG  RFVAR     D {WC/WZ/WCZ}                                                CZ CZ CZ CZ 
EEEE 1101011 CZ 0 DDDDDDDDD  0000101ff  RFVARS  WFBYTE  WFWORD  WFLONG    D {WC/WZ/WCZ};{#}D;{#}D;{#}D                                 CZ -- -- -- 
EEEE 1101011 CZ 0 DDDDDDDDD  0000110ff  GETQX   GETQY   GETCT   GETRND    D {WC/WZ/WCZ};D {WC/WZ/WCZ};D;D        {WC/WZ/WCZ}           CZ CZ -- CZ 
EEEE 1101011 00 L DDDDDDDDD  0000111ff  SETDACS SETXFRQ GETXACC WAITX     {#}D;{#}D;D;{#}D {WC/WZ/WCZ}                                 -- -- -- -- 
EEEE 1101011 00 L DDDDDDDDD  0001000ff  SETSE1  SETSE2  SETSE3  SETSE4    {#}D                                                         -- -- -- -- 
EEEE 1101011 CZ 0 0000000ff  000100100  POLLINT POLLCT1 POLLCT2 POLLCT3   {WC/WZ/WCZ}                                                  CZ CZ CZ CZ 
EEEE 1101011 CZ 0 0000001ff  000100100  POLLSE1 POLLSE2 POLLSE3 POLLSE4   {WC/WZ/WCZ}                                                  CZ CZ CZ CZ 
EEEE 1101011 CZ 0 0000010ff  000100100  POLLPAT POLLFBW POLLXMT POLLXFI   {WC/WZ/WCZ}                                                  CZ CZ CZ CZ 
EEEE 1101011 CZ 0 0000011ff  000100100  POLLXRO POLLXRL POLLATN POLLQMT   {WC/WZ/WCZ}                                                  CZ CZ CZ CZ 
EEEE 1101011 CZ 0 0000100ff  000100100  WAITINT WAITCT1 WAITCT2 WAITCT3   {WC/WZ/WCZ}                                                  CZ CZ CZ CZ 
EEEE 1101011 CZ 0 0000101ff  000100100  WAITSE1 WAITSE2 WAITSE3 WAITSE4   {WC/WZ/WCZ}                                                  CZ CZ CZ CZ 
EEEE 1101011 CZ 0 0000110ff  000100100  WAITPAT WAITFBW WAITXMT WAITXFI   {WC/WZ/WCZ}                                                  CZ CZ CZ CZ 
EEEE 1101011 CZ 0 0000111ff  000100100  WAITXRO WAITXRL WAITATN ALLOWI    {WC/WZ/WCZ};{WC/WZ/WCZ};{WC/WZ/WCZ};                         CZ CZ CZ -- 
EEEE 1101011 00 0 0001000ff  000100100  ALLOWI  STALLI  TRGINT1 TRGINT2                                                                -- -- -- -- 
EEEE 1101011 00 0 0001001ff  000100100  TRGINT3 NIXINT1 NIXINT2 NIXINT3                                                                -- -- -- -- 
EEEE 1101011 00 L DDDDDDDDD  0001001ff  SETINT1 SETINT2 SETINT3           {#}D                                                         -- -- --    
EEEE 1101011 00 L DDDDDDDDD  0001010ff  SETQ    SETQ2   PUSH    POP       {#}D;{#}D;{#}D;D {WC/WZ/WCZ}                                 -- -- -- CZ 
EEEE 1101011 CZ 0 DDDDDDDDD  0001011ff  JMP                               D {WC/WZ/WCZ}                                                CZ          
EEEE 1101011 CZ 0 DDDDDDDDD  000101101  CALL    RET                       D {WC/WZ/WCZ};{WC/WZ/WCZ}                                    CZ CZ       
EEEE 1101011 CZ f DDDDDDDDD  00010111f  CALLA   RETA    CALLB   RETB      D {WC/WZ/WCZ};{WC/WZ/WCZ};D {WC/WZ/WCZ};{WC/WZ/WCZ}          CZ CZ CZ CZ 
EEEE 1101011 00 L DDDDDDDDD  0001100ff  JMPREL  SKIP    SKIPF   EXECF     {#}D                                                         -- -- -- -- 
EEEE 1101011 00 0 DDDDDDDDD  0001101ff  GETPTR                            D                                                            --          
EEEE 1101011 CZ 0 DDDDDDDDD  000110101  GETBRK  COGBRK                    D WC/WZ/WCZ;{#}D                                             CZ --       
EEEE 1101011 00 L DDDDDDDDD  000110110  BRK     SETLUTS                   {#}D                                                         -- --       
EEEE 1101011 00 L DDDDDDDDD  0001110ff  SETCY   SETCI   SETCQ   SETCFRQ   {#}D                                                         -- -- -- -- 
EEEE 1101011 00 L DDDDDDDDD  0001111ff  SETCMOD SETPIV  SETPIX  COGATN    {#}D                                                         -- -- -- -- 
EEEE 1101011 CZ L DDDDDDDDD  0010000ff  TESTP   TESTPN  TESTP   TESTPN    {#}D WC/WZ;{#}D WC/WZ;{#}D ANDC/ANDZ;{#}D ANDC/ANDZ          CZ CZ CZ CZ 
EEEE 1101011 CZ L DDDDDDDDD  0010001ff  TESTP   TESTPN  TESTP   TESTPN    {#}D ORC/ORZ;{#}D ORC/ORZ;{#}D XORC/XORZ;{#}D XORC/XORZ      CZ CZ CZ CZ 
EEEE 1101011 CZ L DDDDDDDDD  0010000ff  DIRL    DIRH    DIRC    DIRNC     {#}D {WCZ}                                                   CZ CZ CZ CZ 
EEEE 1101011 CZ L DDDDDDDDD  0010001ff  DIRZ    DIRNZ   DIRRND  DIRNOT    {#}D {WCZ}                                                   CZ CZ CZ CZ 
EEEE 1101011 CZ L DDDDDDDDD  0010010ff  OUTL    OUTH    OUTC    OUTNC     {#}D {WCZ}                                                   CZ CZ CZ CZ 
EEEE 1101011 CZ L DDDDDDDDD  0010011ff  OUTZ    OUTNZ   OUTRND  OUTNOT    {#}D {WCZ}                                                   CZ CZ CZ CZ 
EEEE 1101011 CZ L DDDDDDDDD  0010100ff  FLTL    FLTH    FLTC    FLTNC     {#}D {WCZ}                                                   CZ CZ CZ CZ 
EEEE 1101011 CZ L DDDDDDDDD  0010101ff  FLTZ    FLTNZ   FLTRND  FLTNOT    {#}D {WCZ}                                                   CZ CZ CZ CZ 
EEEE 1101011 CZ L DDDDDDDDD  0010110ff  DRVL    DRVH    DRVC    DRVNC     {#}D {WCZ}                                                   CZ CZ CZ CZ 
EEEE 1101011 CZ L DDDDDDDDD  0010111ff  DRVZ    DRVNZ   DRVRND  DRVNOT    {#}D {WCZ}                                                   CZ CZ CZ CZ 
EEEE 1101011 00 0 DDDDDDDDD  0011000ff  SPLITB  MERGEB  SPLITW  MERGEW    D                                                            -- -- -- -- 
EEEE 1101011 00 0 DDDDDDDDD  0011001ff  SEUSSF  SEUSSR  RGBSQZ  RGBEXP    D                                                            -- -- -- -- 
EEEE 1101011 00 0 DDDDDDDDD  0011010ff  XORO32  REV     RCZR    RCZL      D;D;D {WC/WZ/WCZ};D {WC/WZ/WCZ}                              -- -- CZ CZ 
EEEE 1101011 00 0 DDDDDDDDD  0011011ff  WRC     WRNC    WRZ     WRNZ      D                                                            -- -- -- -- 
EEEE 1101100 RA A AAAAAAAAA  AAAAAAAAA  JMP     CALL    CALLA   CALLB     #A                                                           -- -- -- -- 
EEEE 11100WW RA A AAAAAAAAA  AAAAAAAAA  CALLD   LOC     AUGS    AUGD      PA/PB/PTRA/PTRB,#A;PA/PB/PTRA/PTRB,#A;#N;#N                  -- -- -- --

Cluso99 · 2018-11-04 - 04:20:56

Crystal Parameters for HUBSET

This should work. Just fill in the values and the values will be calculated for you...
(samples shown for P2-EVAL & P2D2 boards with 150MHz & 148.5MHz selected respectively)

CON
'+-------[ Select for P2-EVAL ]------------------------------------------------+ 
  _XTALFREQ     = 20_000_000                                    ' crystal frequency
  _XDIV         = 2             '\                              '\ crystal divider                      to give 10.0MHz
  _XMUL         = 15            '| 150 MHz                      '| crystal / div * mul                  to give 150MHz
  _XDIVP        = 1             '/                              '/ crystal / div * mul /divp            to give 150MHz
  _XOSC         = %10                                   '15pF   ' %00=OFF, %01=OSC, %10=15pF, %11=30pF
'+-------[ Select for P2D2 ]---------------------------------------------------+ 
  _XTALFREQ     = 12_000_000                                    ' crystal frequency
  _XDIV         = 4             '\                              '\ crystal divider                      to give   3.0MHz
  _XMUL         = 99            '| 148.5MHz                     '| crystal / div * mul                  to give 297.0MHz
  _XDIVP        = 2             '/                              '/ crystal / div * mul /divp            to give 148.5MHz
  _XOSC         = %01                                   'OSC    ' %00=OFF, %01=OSC, %10=15pF, %11=30pF
'+-----------------------------------------------------------------------------+
  _XSEL         = %11                                   'XI+PLL ' %00=rcfast(20+MHz), %01=rcslow(~20KHz), %10=XI(5ms), %11=XI+PLL(10ms)
  _XPPPP        = ((_XDIVP>>1) + 15) & $F                       ' 1->15, 2->0, 4->1, 6->2...30->14
  _CLOCKFREQ    = _XTALFREQ / _XDIV * _XMUL / _XDIVP            ' internal clock frequency                
  _SETFREQ      = 1<<24 + (_XDIV-1)<<18 + (_XMUL-1)<<8 + _XPPPP<<4 + _XOSC<<2  ' %0000_000e_dddddd_mmmmmmmmmm_pppp_cc_00  ' setup  oscillator
  _ENAFREQ      = _SETFREQ + _XSEL                                             ' %0000_000e_dddddd_mmmmmmmmmm_pppp_cc_ss  ' enable oscillator

  _1us          = _clockfreq/1_000_000                          ' 1us

DAT             org     0
'+-------[ Set Xtal ]----------------------------------------------------------+ 
entry           hubset  #0                              ' set 20MHz+ mode
                hubset  ##_SETFREQ                      ' setup oscillator
                waitx   ##20_000_000/100                ' ~10ms
                hubset  ##_ENAFREQ                      ' enable oscillator
'+-----------------------------------------------------------------------------+

Oops. Fixed this _SETFREQ = 1<<24 +.. was 1<<25
Updated: 22 Feb 2019

evanh · 2018-11-04 - 05:12:39

Custom pin config bits when issuing smartpin mode setting:
(Source - https://forums.parallax.com/discussion/comment/1392310/#Comment_1392310)

Cogs share the configuring of each per-pin mode register.
A pin will stay configured even if all cogs are restarted.

WRPIN   {#}D,{#}S	Write D to mode register of pin S[5:0], acknowledge smartpin if operating.

   bit 30    25     20   15   10      5     0
        |     |      |    |    |      |     |
D/# = %AAAA_BBBB_FFF_PPPPPPPPPPPPP_TT_MMMMM_0

 2    1    1
 0    5    0
%PPPPPPPPPPPPP: low-level custom pin control

	common labelling of pin config bits
		%C = clocked/registered I/O (extra clock for IN and OUT)
		%I = invert IN output
		%O = invert OUT input
		%HHH/LLL = digital out drive strength
			000: Fast, 20R
			001: 1k5R
			010: 15kR
			011: 150kR
			100: 1mA
			101: 100uA
			110: 10uA
			111: Float
		PinA is specified pin number
		PinB is PinA's odd/even pair

	 0      5    0
	%0_VVV_CIOHHHLLL = Digital mode, 3.3 volt
		DIR enables PinA digital output
		%VVV = Digital config
			000: IN = PinA logic, PinA output from OUT
			001: IN = PinA logic, PinA output inverted from IN
			010: IN = PinB logic, PinA output inverted from IN
			011: IN = PinA schmitt, PinA output from OUT
			100: IN = PinA schmitt, PinA output inverted from IN
			101: IN = PinB schmitt, PinA output inverted from IN
			110: IN = PinA > PinB comparator, PinA output from OUT
			111: IN = PinA > PinB comparator, PinA output inverted from IN

	 0     5     0
	%100_VVV_OHHHLLL = ADC_MODE, first order sigma-delta
		IN has bitstream, sysclock bitrate
		OUT is PinA digital output, registered
		DIR enables PinA digital output
		%VVV = ADC config
			000: GIO, 1x (~5 volt range, centred on VIO/2)
			001: VIO, 1x       "
			010: PinB, 1x      "     (In revC silicon this measures the zero-bias point of the ADC)
			011: PinA, 1x      "
			100: PinA, 3.16x (~1.58 volt range, centred on VIO/2)
			101: PinA, 10x   (~0.5 volt range, centred on VIO/2)
			110: PinA, 31.6x (~0.158 volt range, centred on VIO/2)
			111: PinA, 100x  (~0.05 volt range, centred on VIO/2)

	 0      5    0
	%101_VV_DDDDDDDD = DAC_MODE (%TT = 00 and %MMMMM = 00000), 8-bit flash, registered
		OUT enables PinA ADC (ADC config %011), sysclocked bitstream on IN
		DIR enables PinA DAC output
		%VV = PinA DAC config
			00: 990 ohm, 3.3 volt range
			01: 600 ohm, 2.0 volt range
			10: 123.75 ohm, 3.3 volt range
			11: 75 ohm, 2.0 volt range
		%DDDDDDDD = DAC level

		for %TT = %01 and %MMMMM = %00000, %101_VV_xxxxSSSS = COG_DAC mode
			%SSSS = Cog/streamer select: sets DAC level

		for %00000 < %MMMMM < %00100 = SMART_DAC mode
			DIR/IN are usual smartpin ctrl
			%DDDDDDDD ignored, smartpin sets DAC level

		for %MMMMM >= %00100 or (%TT = %1x and %MMMMM = %00000) = BIT_DAC mode
			OUT sets DAC level, (ADC disabled?, IN = ?)
				0: 0 = GIO level (revA)		0: %xxxxDDDD (revB) One of sixteen levels
				1: %DDDDDDDD     (revA)		1: %DDDDxxxx (revB) One of sixteen levels

	 0      5    0
	%11_VV_CDDDDDDDD = COMP_DAC comparator mode, DAC always clocked (registered)
		DIR enables PinA digital output
		%VV = Comparator config
			00: IN = PinA > D.  PinA driven by 1k5R from OUT
			01: IN = PinA > D.  PinA driven by 1k5R from !IN
			10: IN = PinB > D.  PinA driven by 1k5R from IN
			11: IN = PinB > D.  PinA driven by 1k5R from !IN
		%DDDDDDDD = DAC level for internal analogue compare

Mode list:
Digital I/O (default)
- inversion
- clocking (registered)
- out strength
- feedback select
- logic in / schmitt in / comparator in

COMP_DAC
- preset level
- pinA/B in select
- feedback select (1500 Ohm out strength)

ADC_MODE
- in/gain select (pinB is disabled in revC silicon)

DAC_MODE
- strength
- preset level
- COG_DAC
- - specify cog
- - cog/streamer provides level
- SMART_DAC
- - associated smartpin provides level
- BIT_DAC
- - preset split level

Updated 20-11-2018 to correct smartpin mode number for capturing ADC bitstream.
25-11-2018: Reverse the update. Doh!
26-12-2018: Typo, R -> % in BIT_DAC mode line. And stated for engineering sample.
26-3-2019: Add link to source "pin_modes.png" sheet.
3-7-2019: Add "0" and "5" bit position indicators for faster constant crafting.
17-11-2019: Add changed revB silicon BIT_DAC mode. Mark DAC_MODE and its sub-modes as registered I/O.
1-12-2019: Add short mode list.
4-4-2020: RevC update.

Cluso99 · 2018-11-04 - 08:25:08

Saw this trick in Chip's ROM boot code to load a large value using a small constant...

		decod	y,#10			'ready to input $400 bytes from SPI

' good for..

                DECOD   D,#n            ' 1 << n                          
   n                                       n
   0 ->    $1 =                   %1       16 ->    $1_0000 =                   %1_0000_0000_0000_0000
   1 ->    $2 =                  %10       17 ->    $2_0000 =                  %10_0000_0000_0000_0000
   2 ->    $4 =                 %100       18 ->    $4_0000 =                 %100_0000_0000_0000_0000
   3 ->    $8 =                %1000       19 ->    $8_0000 =                %1000_0000_0000_0000_0000
   4 ->   $10 =              %1_0000       20 ->   $10_0000 =              %1_0000_0000_0000_0000_0000
   5 ->   $20 =             %10_0000       21 ->   $20_0000 =             %10_0000_0000_0000_0000_0000
   6 ->   $40 =            %100_0000       22 ->   $40_0000 =            %100_0000_0000_0000_0000_0000
   7 ->   $80 =           %1000_0000       23 ->   $80_0000 =           %1000_0000_0000_0000_0000_0000
   8 ->  $100 =         %1_0000_0000       24 ->  $100_0000 =         %1_0000_0000_0000_0000_0000_0000
   9 ->  $200 =        %10_0000_0000       25 ->  $200_0000 =        %10_0000_0000_0000_0000_0000_0000
  10 ->  $400 =       %100_0000_0000       26 ->  $400_0000 =       %100_0000_0000_0000_0000_0000_0000
  11 ->  $800 =      %1000_0000_0000       27 ->  $800_0000 =      %1000_0000_0000_0000_0000_0000_0000
  12 -> $1000 =    %1_0000_0000_0000       28 -> $1000_0000 =    %1_0000_0000_0000_0000_0000_0000_0000
  13 -> $2000 =   %10_0000_0000_0000       29 -> $2000_0000 =   %10_0000_0000_0000_0000_0000_0000_0000
  14 -> $4000 =  %100_0000_0000_0000       30 -> $4000_0000 =  %100_0000_0000_0000_0000_0000_0000_0000
  15 -> $8000 = %1000_0000_0000_0000       31 -> $8000_0000 = %1000_0000_0000_0000_0000_0000_0000_0000

Also this to load $FFFF_FFFF

		neg	pb,#1			'set command bits to all 1's

Updated with more info 22 Feb 2019

cgracey · 2018-11-04 - 08:30:03

There's also BMASK for making LSB-justified runs of 1's.

BMASK D,#11 'D = $FFF
BMASK D,#15 'D = $FFFF
BMASK D,#30 'D = $7FFF_FFFF

Cluso99 · 2018-11-04 - 08:53:22

Nice thanks Chip.
So here is another way of expressing this...

                BMASK   D,#n            ' where 'n+1' is the number of LSB 1's
   n                                       n
   0 ->    $1 =                   %1       16 ->    $1_FFFF =                   %1_1111_1111_1111_1111
   1 ->    $3 =                  %11       17 ->    $3_FFFF =                  %11_1111_1111_1111_1111
   2 ->    $7 =                 %111       18 ->    $7_FFFF =                 %111_1111_1111_1111_1111
   3 ->    $F =                %1111       19 ->    $F_FFFF =                %1111_1111_1111_1111_1111
   4 ->   $1F =              %1_1111       20 ->   $1F_FFFF =              %1_1111_1111_1111_1111_1111
   5 ->   $3F =             %11_1111       21 ->   $3F_FFFF =             %11_1111_1111_1111_1111_1111
   6 ->   $7F =            %111_1111       22 ->   $7F_FFFF =            %111_1111_1111_1111_1111_1111
   7 ->   $FF =           %1111_1111       23 ->   $FF_FFFF =           %1111_1111_1111_1111_1111_1111
   8 ->  $1FF =         %1_1111_1111       24 ->  $1FF_FFFF =         %1_1111_1111_1111_1111_1111_1111
   9 ->  $3FF =        %11_1111_1111       25 ->  $3FF_FFFF =        %11_1111_1111_1111_1111_1111_1111
  10 ->  $7FF =       %111_1111_1111       26 ->  $7FF_FFFF =       %111_1111_1111_1111_1111_1111_1111
  11 ->  $FFF =      %1111_1111_1111       27 ->  $FFF_FFFF =      %1111_1111_1111_1111_1111_1111_1111
  12 -> $1FFF =    %1_1111_1111_1111       28 -> $1FFF_FFFF =    %1_1111_1111_1111_1111_1111_1111_1111
  13 -> $3FFF =   %11_1111_1111_1111       29 -> $3FFF_FFFF =   %11_1111_1111_1111_1111_1111_1111_1111
  14 -> $7FFF =  %111_1111_1111_1111       30 -> $7FFF_FFFF =  %111_1111_1111_1111_1111_1111_1111_1111
  15 -> $FFFF = %1111_1111_1111_1111       31 -> $FFFF_FFFF = %1111_1111_1111_1111_1111_1111_1111_1111

adjusted per Chip's following suggestion

cgracey · 2018-11-04 - 08:57:36

Cluso99, if you made that list show 0..31, instead of 1..32, it would make more immediate sense.

Cluso99 · 2018-11-06 - 04:11:53

Streamer

Here is a section of code to record 'sample_length' of P0-P31 or P32-P63 using the streamer into HUB RAM at 'samples'...

con
' Streams INA (32 bits) to hub.
                sample_length = 4000    'longs

dat             orgh
                org     0
...
                setxfrq ##$8000_0000    'sysclk sample rate
                wrfast  #0,##@samples
'                         %1111_xxxx_xppp_xxxx << 16
'                                     000                                 P31-0
'                                     001                                 P39-8
'                                     010                                 P47-16
'                                     011                                 P55-24
'                                     100                                 P63-32
'                                     101                            P7-0+P63-40
'                                     110                           P15-0+P63-48
'                                     111                           P23-0+P63-56 
                xinit   ##%1111_0000_0000_0000 << 16 | sample_length,#0  'P00-31
'               xinit   ##%1111_0000_0100_0000 << 16 | sample_length,#0  'P32-63
                waitxfi
'*******************************************************************
                orgh    $4000
samples         long    0[sample_length]
'*******************************************************************

evanh · 2018-12-06 - 10:57:13

A trap. Pnut has buggy code generation for PC-relative encoding of LOC instruction. Recommendation, for the moment anyway, is to always use #\ or #\@ .

 LOC/MOV syntax         ORG $00F           ORGH $00110         ORGH $00600
 from hubexec        op-code  PA-data    op-code  PA-data    op-code  PA-data
==============================================================================
loc  pa, #label     fe80000f 0000000f   fe800110 00000110   fe900198 00000600
loc  pa, #@label    fe80003c 0000003c   fe800110 00000110   fe900174 00000600
loc  pa, #\label    fe80000f 0000000f   fe800110 00000110   fe800600 00000600
loc  pa, #\@label   fe80003c 0000003c   fe800110 00000110   fe800600 00000600
mov  pa, ##label    f607ec0f 0000000f   f607ed10 00000110   f607ec00 00000600
mov  pa, ##@label   f607ec3c 0000003c   f607ed10 00000110   f607ec00 00000600

 LOC/MOV syntax         ORG $00F           ORGH $00110         ORGH $00600
 from cogexec        op-code  PA-data    op-code  PA-data    op-code  PA-data
==============================================================================
loc  pa, #label     fe9fffe0 000ffff7   fe9003dc 000003f5   fe800600 00000600
loc  pa, #@label    fe900070 00000090   fe9003b8 000003da   fe800600 00000600
loc  pa, #\label    fe80000f 0000000f   fe800110 00000110   fe800600 00000600
loc  pa, #\@label   fe80003c 0000003c   fe800110 00000110   fe800600 00000600
mov  pa, ##label    f607ec0f 0000000f   f607ed10 00000110   f607ec00 00000600
mov  pa, ##@label   f607ec3c 0000003c   f607ed10 00000110   f607ec00 00000600

NOTE: When specifying a numerical immediate in place of the label, it is treated as an absolute address and the same rules apply, ie: it will be encoded as PC-relative if possible, as per above. However, "@" produces an error with Pnut but not with p2asm. p2asm will perform a left shift by 2.

Test code added: 2019-4-11

UPDATES:
2019-4-12: Bug is fixed in fastspin v3.9.25 - https://github.com/totalspectrum/spin2cpp
2019-4-13: Bug is fixed in p2asm v0.015 - https://github.com/davehein/p2gcc
2020-7-05: Bug is fixed in Pnut v34 (5 Feb 2020) - http://forums.parallax.com/discussion/comment/1488890/#Comment_1488890

Cluso99 · 2018-12-06 - 12:18:29

Beware the instructions TESTB & TESTBN seems to me to give the wrong results for the Z flags on P2-ES silicon

                mov     lmm_x,#0
                testb   lmm_x,#0                wz      ' nz  <<<<<
                testbn  lmm_x,#0                wz      ' z   <<<<<
                testb   lmm_x,#0                wc      ' nc
                testbn  lmm_x,#0                wc      ' c
                and     lmm_x,#1                wz      ' z

                mov     lmm_x,#1
                testb   lmm_x,#0                wz      ' z   <<<<<
                testbn  lmm_x,#0                wz      ' nz  <<<<<
                testb   lmm_x,#0                wc      ' c
                testbn  lmm_x,#0                wc      ' nc
                and     lmm_x,#1                wz      ' nz

cgracey · 2018-12-07 - 05:01:30

Cluso99 wrote: »

Beware the instructions TESTB & TESTBN seems to me to give the wrong results for the Z flags on P2-ES silicon

                mov     lmm_x,#0
                testb   lmm_x,#0                wz      ' nz  <<<<<
                testbn  lmm_x,#0                wz      ' z   <<<<<
                testb   lmm_x,#0                wc      ' nc
                testbn  lmm_x,#0                wc      ' c
                and     lmm_x,#1                wz      ' z

                mov     lmm_x,#1
                testb   lmm_x,#0                wz      ' z   <<<<<
                testbn  lmm_x,#0                wz      ' nz  <<<<<
                testb   lmm_x,#0                wc      ' c
                testbn  lmm_x,#0                wc      ' nc
                and     lmm_x,#1                wz      ' nz

For anyone new reading, all register-level instructions affect the Z flag as you would expect, where it gets set if the result was zero.

For the bit-level instructions, on the other hand, C and Z are both read and written directly, without semantic consideration for what Z usually means.

evanh · 2018-12-26 - 08:34:43

There's a couple of undocumented traps with the REP instruction. One was known and easy to avoid, the other was unknown until recently and should be corrected in the next revision.

The known one is the last instruction within the REP block cannot be a branching instruction. If a branching instruction is used then the branch distance will have the block length subtracted from it. It won't be remedied, so just don't do it.

Any intentionally cancelling branches must be at least one instruction back from the end of the REP block.
UPDATE: This flaw only affects relative branching! Absolute immediate and register direct can work as usual with the last instruction of a REP block. Alternatively, a compensation (block length added) applied to the relative branch also works. Further reading - https://forums.parallax.com/discussion/comment/1488366/#Comment_1488366

The until recently unknown one is with the Jxxx branch-on-event instructions. Using any of these instructions anywhere within the REP block will intermittently fail to branch upon event. When the failure occurs, execution will continue out the end of the REP block and even fail to take the first following branch.

This one is expected to be fixed. Example code of accommodating, and alternative below - https://forums.parallax.com/discussion/comment/1458393/#Comment_1458393
UPDATE: This one was fixed with v33 FPGA files, rev B silicon.

Some extra detail - https://forums.parallax.com/discussion/comment/1461458/#Comment_1461458
and https://forums.parallax.com/discussion/169438/rep-blocks-and-branching-issue/p1

jmg · 2018-12-26 - 09:00:06

♪

jmg · 2018-12-26 - 09:03:08

♪

evanh · 2019-01-17 - 01:48:48

New tidbit discovered: WRPIN input %AAAABBBB config still apply to IN when smartpin is off. Which presumably means %FFF config also works with smartpin off.

Cluso99 · 2019-01-19 - 04:15:29

Code to convert a nibble to an ASCII character "0".."9" "A".."F" using just the C flag...

' convert nibble to ASCII hex char
                getnib  x,value,#7              '\ either instruction extracts only the lower nibble
                and     x,#$0F                  '/
                
                or      x,#"0"
                cmp     x,#";"            wc    ' : -> A etc
        if_nc   add     x,#7

evanh · 2019-01-27 - 03:26:57

NOTE: This was fixed in v33 FPGA builds, rev B silicon doesn't have this flaw. It now forwards a copy of the write data so that the simultaneous read will see latest value.

There's a hardware flaw with shared lutRAM. A simultaneous read and write will glitch the read data. The glitch patterns change slightly with each run but the alignment doesn't. Same for different sys clock rates.

v32i FPGA image on P123 board @ 20 MHz

lut glitch test =>  ffffffff   00000c00   00000000   00000000   alignment =     2   ticks =    14
lut glitch test =>  00000000   fbfffffb   ffffffff   ffffffff   alignment =     2   ticks =    14
lut glitch test =>  aaaaaaaa   51555d51   55555555   55555555   alignment =     2   ticks =    14
lut glitch test =>  55555555   aaaaaaaa   aaaaaaaa   aaaaaaaa   alignment =     2   ticks =    14

RevA P2ES board @ 20 MHz

lut glitch test =>  ffffffff   4a41febf   00000000   00000000   alignment =     2   ticks =    14
lut glitch test =>  00000000   00000000   ffffffff   ffffffff   alignment =     2   ticks =    14
lut glitch test =>  aaaaaaaa   0a80aaaa   55555555   55555555   alignment =     2   ticks =    14
lut glitch test =>  55555555   40415415   aaaaaaaa   aaaaaaaa   alignment =     2   ticks =    14

EDIT: Updated with extra tests. Thanks Brian.
EDIT2: Added that revB has this fixed.

jmg · 2019-01-27 - 04:06:12

♪

evanh · 2019-01-27 - 05:07:22

JMG,
You've managed to add a forth comment now!

jmg · 2019-01-27 - 05:57:27

evanh wrote: »

JMG, Please remove your comments from this topic. That goes for the earlier comments too.

Seem the forum software does not actually allow that, so I've done the next best thing..... ♪

Mark_T · 2019-02-12 - 22:45:25

This isn't strictly a P2 trap, but the presence of the stack based RET instruction and relative branches makes this
much harder to spot and can lead you (well me) running around in circles trying to track down very strange behaviours
that seem to defy logic:

    cognew (@entry, ...)

DAT
            ORG
rogue       long   0

entry       ' your code

Of course the ORG should be after the random long data, otherwise all the addressing is thrown, but
the effect is to omit the leading instructions in call'ed routines (jmps are relative and tend to work),
which can have subtle and bizarre consequences.

On the P1 all branches get affected and things tend to fall over completely rather than limp along misbehaving

It would be nice to get an assembler warning if the first entry after ORG 0 is not an instruction.

Cluso99 · 2019-02-14 - 04:33:38

There are times where the first instruction is a long that has no effect when executed.
P2 will be a little different to P1 in that you can start the cog at other than address COG $0, and also because we don't really have a NOP opcode.

Postedit
In P1 it was a common trick to use
LONG <somevalue>
where <somevalue> was <= 18-bits
This meant that the conditional bits EEEE=0000 and so the instruction would be treated as a NOP.

In P2 the EEEE=0000 is a valid instruction with the _RET_ condition. The instruction executes, and if not a taken branch it will also perform a RET instruction.
Therefore, any value other than all zeros will execute some intsruction.

Thus
LONG <any-non-zero-value>
will NOT BE TREATED AS A NOP in P2 !!!

ozpropdev · 2019-02-14 - 04:45:15

P2 does have a NOP opcode.

0000 0000000 000 000000000 000000000        NOP

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