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P2D2 - An open hardware reference design for the P2 CPU
In the course of documenting the P2 chip I wanted to include some basic schematics but in the process ended up designing a P2 board suitable for P2 development testing and also designing in as a component, hence P2D2, even if it does sound droid.
Why the new thread?
BUT P2D2 is not meant to be a hat or compatible with any other boards, it's main aim is to firstly allow access to all the P2 I/O pins and to have sufficient on-board resources to enable it to run off any USB serial cable. Secondly, it would be compact and versatile enough to mount on a matrix or pcb board as a component for prototypes and low-volume designs. So as to keep all the information and questions about P2D2 from being buried under too many uncontrolled suggestions with their own agenda, I thought I'd start a new thread. Parallax forum etiquette is stacks better than most forums, let's keep it that way.
Here are the screenshots of the schematics and pcb layers for reference. This top post will be updated with the current versions and links although the P2D2 document should always be up to date. Look in the dropbox folder for the pcb files which I will try to make available in different formats but if you have successfully imported into your pcb tool and can then export it into other formats then please post those files so that everyone can make use of them.
It is intended that prototypes will be produced before P2 is available so that the circuit can be verified and tested in conjunction with an FPGA board connected to the I/O and reset. Dummy loads will be switched in to test the 3.3 and 1.8V supplies as well. Once P2 chips are available they could be dropped onto a preassembled and tested board.