IIRC, although the three documents listed in that old post does refer to that subject, the one from NXP shows an exposed pad almost the same size the one P2 will have.
That doc also says this about a sparse stencil paste 'The stencil opening should be approximately 50% – 80% of the total PCB thermal pad area. This stencil-PCB thermal pad ratio ensures proper coverage of the thermal pad area with fewer voids and minimizes the possibility of
overflow bridging to the adjacent lead.'
Carefull reading will show the reason to copper filling (solid, no hollow) the vias, since this is the better way to transfer heat from the exposed pad to inner and outer layers (in a > than 2 layer design).
It's also the reason for using so many vias in the array. Note that heat flux will develop parallel to the seating plane of the exposed pad, in each copper plane the vias are attached to.
Consulting Amkor datasheet for the encapsulation you will use, should enable to calculate P2 temperature increase, from ambient (~25ºC), if power dissipation tops ~2W.
Amkor's table has three columns (phi theta something), the first one at Zero air flux speed, thus the more conservative one.
Here's a slightly different bottom layer that seeks to have as much copper as possible from the center pad while keeping all the decoupling cap grounds low impedance and low noise, all on normal double-sided. Obviously of course, multi-layer will let us pack things in far better and the whole bottom layer could be ground.
I have had problems with square pads. Sometimes the Herbert's get the pads rotated at the pcb house. OSHpark had this problem on one of my pcbs. AFAIK, it's not a Protel problem, but a rendition of the gerber.
I don't use square or octagonal pads any more. Once bitten, twice shy.
From the heat dissipation standpoint, it seems far better than the previous one(s).
It's truly impressive how fast you did the new design!
Sure, your graphic skills are on par with your other habilities.
Here in Brazil, we use to refer to a person with that much habilities as "homem de sete instrumentos = seven-instrument man"; in english it better translates to "one man band".
You sure has lifted the meaning to an even higher level.
P.S. Always remember: as intended package power dissipation increases, so widens the need for a better coverage (% area) of solder paste, distributed over the metal land area onto the printed circuit board.
The maximum coverage is limited, by having to carefully provide a minimum volumetric passage for degassing, at the escape channels between molten solder isles, during the reflow proccess.
This will ensure package adhesion to evenly occur at the land pattern and will avoid solder voids (sic).
Four inches really restricts via access which is important around a 64 pin part. Maybe a heat sink is an option mounted directly to the bottom of the board. Or a custom pcb/heat sink that is designed just as heat sink that can solder to the bottom of the pcb and provide lots of heat dissipation.
It might be worthwhile going to a 4-layer board to ensure a big, contiguous ground plane that can dissipate the heat. Any interruption in the plane kills the heat conductivity.
If you really needed a serious sink you could get some sheet copper and machine this part. This example is 2"x2" = 4 Sq In. The part in the middle is extruded up to fit through the PCB and make contact with the back of the P2. Have the PCB drilled or routed for a 10mm hole, then air solder this part direct to the bottom of the chip. Glue the edges of the sink to the back of the PCB for support.
AFAIK, it's not a Protel problem, but a rendition of the gerber.
If you follow the Gerber definition I pasted above, it certainly is Protel's problem.
It can be patched in the Gerber file, and then it renders OK here http://www.gerber-viewer.com/
It might be worthwhile going to a 4-layer board to ensure a big, contiguous ground plane that can dissipate the heat. Any interruption in the plane kills the heat conductivity.
2 Oz copper can help there, on 2 layer designs, and interruptions are not complete killers, even on 2 layer boards. All copper conducts heat, and once spread, it will travel across the narrow gaps via the FR4.
The whole board should be warm as a result.
If you really needed a serious sink you could get some sheet copper and machine this part. This example is 2"x2" = 4 Sq In. The part in the middle is extruded up to fit through the PCB and make contact with the back of the P2. Have the PCB drilled or routed for a 10mm hole, then air solder this part direct to the bottom of the chip. Glue the edges of the sink to the back of the PCB for support.
Hehe, you missed the mounts for a fan !!
This for the over-clocking enthusiasts
It might be worthwhile going to a 4-layer board to ensure a big, contiguous ground plane that can dissipate the heat. Any interruption in the plane kills the heat conductivity.
The board looks really good, by the way.
Ditto on both. Board is looking really good, but I see absolutely no reason for it to be restricted to 2 layer. 4 layer will allow much greater heat dissipation characteristics as well as some other options for signal integrity.
In regards to vias on the thermal pad, the current design will be difficult to manage paste volume due to the quantity and placement of the vias (although I haven't caught if they are gold/epoxy filled to eliminate paste thieving). In a recent design using a similar QFP with a thermal pad, the design had fewer vias, but much larger, placed nearer the perimeter of the ground pad. This allowed for excellent solderpaste printing and minimal voiding in the center of the part, but still excellent heat transfer to/through other layers. The production process was very clean due to the design, voiding was less than 8%, coverage around 85% of the part's pad, and the customer said that all of their thermal goals were well surpassed. (they were trying to design out a heatsink used on their previous design).
No it’s easy to add mount holes to bolt on the fan!
Looking at more practical 'additional cooling' choices...
If you search Digikey for Heatsinks.SMD Pad, you find parts like this HS412-ND
or the V-1100-SMD/B etc are copper, tin plated, for SMD mounting. Their feet look to solder fine under the PAD of P2 (designed to straddle a TO-252)
Might be possible to add solder mask for that ? The V-1100 specs 10.68mm solder mask outer edges, and the via edges are a nudge under 12mm, so I think that fits.
I am planning to try 4 layer as well but I need to be able to see how well a 2-layer design will work otherwise the P2 will be avoided by many who have looked forward to it. I mean, going from 40-pin DIP to to not only SMD but fine pitch exposed pad TQFP with all kinds of power and heat-sinking requirements? I know the P2 will require a good heatsink IF it is pushed hard but the great majority of P1s were barely nudged so I guess the same would go for P2. Commercial applications will probably just use 4-layer board for density and heat sinking as required but some other applications might only need a simple 2-layer and modest heat-sinking.
Then again, this board might be the "chip" that some use for prototyping and small volumes, just as I might too. Anyway, for testing and exercising the P2 chip this board works well as a breakout and the exposed bottom area allows me to add extra heat-sinking if needed, perhaps another thin pcb dedicated just for that since 2-layer are cheap enough. Also as pointed out, the option of 2oz copper goes a long way although that does add greatly to the cost since fine features and heavy copper aren't easy to achieve whereas another simple 2-layer is cheap.
At JLCPCB they quote $20 for 15 boards or $25 for 50 boards, so with 50 boards I can cut and chop them, make up different versions, experiment with hand soldering if need be etc. I'm not worried about a stencil at the moment as I may change some aspects of the design anyway and I'm used to assembling fine pitch and 0603 components.
Ditto on both. Board is looking really good, but I see absolutely no reason for it to be restricted to 2 layer. 4 layer will allow much greater heat dissipation characteristics as well as some other options for signal integrity.
True, but 2 layers is (much) cheaper, and should be compared with 4 layers to see just what the gains are. It's fairly easy to do a 4L version of a 2L board, especially with caps under the package.
In regards to vias on the thermal pad, the current design will be difficult to manage paste volume due to the quantity and placement of the vias (although I haven't caught if they are gold/epoxy filled to eliminate paste thieving).
gold/epoxy filled vias sounds expensive ? Maybe just push the via size toward the smallest end ?
In a recent design using a similar QFP with a thermal pad, the design had fewer vias, but much larger, placed nearer the perimeter of the ground pad. This allowed for excellent solderpaste printing and minimal voiding in the center of the part, but still excellent heat transfer to/through other layers. The production process was very clean due to the design, voiding was less than 8%, coverage around 85% of the part's pad, and the customer said that all of their thermal goals were well surpassed. (they were trying to design out a heatsink used on their previous design).
What paste coverage did they use ?
We've never worried about paste thieving, and the power parts we use seem to solder just fine, with some vias-under that paste fill (but not 36 ).
It does seem that matching the paste-array to via placement could help - a link above was quite broad with their 50~80% paste coverage - sounds somewhat empirical.
... Also as pointed out, the option of 2oz copper goes a long way although that does add greatly to the cost since fine features and heavy copper aren't easy to achieve whereas another simple 2-layer is cheap.
I see JLCPCB have a fixed $20 adder for 2 oz, which seems to be independent of Board quantity.
Thickness seems to not care, until you hit either 0.4mm or 2mm extremes.
0.8mm is getting quite flexible, which might not be so good for a TQFP package ? We've used 1.2mm as a compromise between thinner and stiff.
They also have a $16 adder for Black PCBs, and we have done Black PCBs for thermal reasons, based on Black radiating better. (but I've not made any accurate difference measurements)
I'm sure if one wants to buy PCB by the yard different pricing comes into play.
For a hobbyist that wants to get a handful of tiny boards made the difference between 2 layer and 4 is huge.
Yes, but that's more because the 2 layer price is a loss-leader, than the 4 layer price is expensive.
When Parallax makes Eval Boards, I'm sure they plan on just a tad more than 'a handful'
Economies of scale come into play for productions runs.
My only little point here is that if one is putting out a design, open source, with the expectation that fellow hobbyists can get it built easily, perhaps tweaking and customizing it for their own purposes, then perhaps it's nice to to keep it 2 layer and hence cheap.
@heater/JMG: Ok, so cost is a major factor, got it. My understanding was this was to be a reference design for best case design and use of the P2. With that understanding, I was thinking that performance with all that the P2 offers would be a preference over cost. Not debating the design, just trying to explain why my perspective of 4 layers should have no restrictions for this intent. I am still at a loss at how the discussion implies so much potential heat coming from the chip.
@JMG: The final stencil design we used was a pattern of 9 rectangles equally spaced within the perimeter vias. This gave a wealth of solder paste to fill the center for heat transfer away from the parts, but also decent flow near the vias. There are many white papers and studies done on various patterns for thermal pad coverage. Common patterns are filling inner spaces between vias with squares/rectangles. Other patterns, like angled strips in between vias, etc. have been proven to be poor in comparison)
Unfortunately, with the 49 vias in this design, you end up with 36 rounded rectangles (rounded squares really) that will equate to roughly 50% paste coverage (similar as that shown in the document that Yanomani posted earlier, page 6, figure 6, far right image).
Also, with a PCB clearance of 0.5 to 0.15mm per the preliminary P2 datasheet (dimension A1), you really need to use a 5 mil stencil. (4mil is 0.1016mm, too near the center of the PCB clearance specs) Dimension C is missing (the lead thickness), but other TQFP100 datasheets reference lead thickness as 0.09-0.2mm.
Even at the thinner lead thickness and allowing for the lead to fully settle into the paste down to the pad during placement, the contact expectation of paste to the thermal pad requires a minimum of 4 mils. Using 4 mil stencil could create opens/voids on the ground pad if the paste in the center begins to reflow before the lead pad paste (part would float on the lead pads while the center pad paste settles/liquefies).
In all honesty, the TQFP100 with thermal pad could limit the use of a 4 mil stencil which could also limit the types of packages you can use for supporting circuitry in a P2 design. This could limit the size of design by restricting usage of smaller parts in certain packages. I rarely use 5 mils stencils on complex designs anymore because aperture sizes are too small for that thick of a stencil and violate aspect ratio or area ratio. Not sure of what partnering components will be used with the P2, but with all it's capable of, hopefully this doesn't pose long term challenges with heat dissipation. One could always use solder preforms under the part as well if a design truly required it.
JMG, do you have the ability to x-ray your power parts to verify voiding/coverage?
Those of us that actually design and make and use these things know that there are "absolute maximums" and then there are typical operating conditions. P2 may indeed dissipate 2W under max conditions but most applications will never come near that figure. Besides, P2D2 is a reference design to actually see what a pcb would look like, rather than just talk about it. Since it is a reference design it is also OSH and keeps it simple enough for any pcb house to fab and for anyone to manually assemble. I have another blank matching pcb I intend to attach to the bottom of the P2D2 as a heatsink for when I do push the P2 to the max during testing. But testing extreme conditions is not expected to be the norm as I would be rather disappointed if the P2 always dissipated 2W and always required a 4 layers etc etc.
Perhaps if the board checks out and also checks out with P2 when it's ready, then maybe I can get a small run assembled.
Comments
IIRC, although the three documents listed in that old post does refer to that subject, the one from NXP shows an exposed pad almost the same size the one P2 will have.
https://forums.parallax.com/discussion/comment/1422033/#Comment_1422033
Hope it helps.
Henrique
'The stencil opening should be approximately 50% – 80% of the total PCB thermal pad area. This stencil-PCB thermal pad ratio ensures proper coverage of the thermal pad area with fewer voids and minimizes the possibility of
overflow bridging to the adjacent lead.'
Carefull reading will show the reason to copper filling (solid, no hollow) the vias, since this is the better way to transfer heat from the exposed pad to inner and outer layers (in a > than 2 layer design).
It's also the reason for using so many vias in the array. Note that heat flux will develop parallel to the seating plane of the exposed pad, in each copper plane the vias are attached to.
Consulting Amkor datasheet for the encapsulation you will use, should enable to calculate P2 temperature increase, from ambient (~25ºC), if power dissipation tops ~2W.
Amkor's table has three columns (phi theta something), the first one at Zero air flux speed, thus the more conservative one.
I don't use square or octagonal pads any more. Once bitten, twice shy.
From the heat dissipation standpoint, it seems far better than the previous one(s).
It's truly impressive how fast you did the new design!
Sure, your graphic skills are on par with your other habilities.
Here in Brazil, we use to refer to a person with that much habilities as "homem de sete instrumentos = seven-instrument man"; in english it better translates to "one man band".
You sure has lifted the meaning to an even higher level.
Outstanding work, IMHO! :thumb:
This one shows, very clearly, the whys and hows about solder pastes and stencil openings. Worth reading!
psemi.com/pdf/app_notes/an62.pdf
P.S. Always remember: as intended package power dissipation increases, so widens the need for a better coverage (% area) of solder paste, distributed over the metal land area onto the printed circuit board.
The maximum coverage is limited, by having to carefully provide a minimum volumetric passage for degassing, at the escape channels between molten solder isles, during the reflow proccess.
This will ensure package adhesion to evenly occur at the land pattern and will avoid solder voids (sic).
The board looks really good, by the way.
Not to bring this thread OT, but thank you for posting that link. Uploaded one of my boards to see how it renders. That's dope!
It can be patched in the Gerber file, and then it renders OK here http://www.gerber-viewer.com/
hmm.. Looks to drop the octagons entirely ?
You mentioned caps on the rear side - are those going to be added ?
The whole board should be warm as a result.
Hehe, you missed the mounts for a fan !!
This for the over-clocking enthusiasts
Ditto on both. Board is looking really good, but I see absolutely no reason for it to be restricted to 2 layer. 4 layer will allow much greater heat dissipation characteristics as well as some other options for signal integrity.
In regards to vias on the thermal pad, the current design will be difficult to manage paste volume due to the quantity and placement of the vias (although I haven't caught if they are gold/epoxy filled to eliminate paste thieving). In a recent design using a similar QFP with a thermal pad, the design had fewer vias, but much larger, placed nearer the perimeter of the ground pad. This allowed for excellent solderpaste printing and minimal voiding in the center of the part, but still excellent heat transfer to/through other layers. The production process was very clean due to the design, voiding was less than 8%, coverage around 85% of the part's pad, and the customer said that all of their thermal goals were well surpassed. (they were trying to design out a heatsink used on their previous design).
Just now, by way of an example, jlcpcb.com is quoting $2 for a 2 inch by 2 inch, 2 layer, board. Go to 4 layer and it jumps to $15 !
Which is more than we want to pay for the chip itself.
What am I missing here?
Looking at more practical 'additional cooling' choices...
If you search Digikey for Heatsinks.SMD Pad, you find parts like this HS412-ND
or the V-1100-SMD/B etc are copper, tin plated, for SMD mounting. Their feet look to solder fine under the PAD of P2 (designed to straddle a TO-252)
Might be possible to add solder mask for that ? The V-1100 specs 10.68mm solder mask outer edges, and the via edges are a nudge under 12mm, so I think that fits.
Then again, this board might be the "chip" that some use for prototyping and small volumes, just as I might too. Anyway, for testing and exercising the P2 chip this board works well as a breakout and the exposed bottom area allows me to add extra heat-sinking if needed, perhaps another thin pcb dedicated just for that since 2-layer are cheap enough. Also as pointed out, the option of 2oz copper goes a long way although that does add greatly to the cost since fine features and heavy copper aren't easy to achieve whereas another simple 2-layer is cheap.
At JLCPCB they quote $20 for 15 boards or $25 for 50 boards, so with 50 boards I can cut and chop them, make up different versions, experiment with hand soldering if need be etc. I'm not worried about a stencil at the moment as I may change some aspects of the design anyway and I'm used to assembling fine pitch and 0603 components.
gold/epoxy filled vias sounds expensive ? Maybe just push the via size toward the smallest end ?
What paste coverage did they use ?
We've never worried about paste thieving, and the power parts we use seem to solder just fine, with some vias-under that paste fill (but not 36 ).
It does seem that matching the paste-array to via placement could help - a link above was quite broad with their 50~80% paste coverage - sounds somewhat empirical.
I see JLCPCB have a fixed $20 adder for 2 oz, which seems to be independent of Board quantity.
Thickness seems to not care, until you hit either 0.4mm or 2mm extremes.
0.8mm is getting quite flexible, which might not be so good for a TQFP package ? We've used 1.2mm as a compromise between thinner and stiff.
They also have a $16 adder for Black PCBs, and we have done Black PCBs for thermal reasons, based on Black radiating better. (but I've not made any accurate difference measurements)
2 Layers : $58.00/㎡ Build Time:2 days
4 Layers : $110.00/㎡ Build Time:4-5 days
6 Layers : $168.00/㎡ Build Time:7-8 days
I make the incremental adders here
2L->4L .038*.052*(110-58) = $0.1027
2L ->6L .038*.052*(168-58) = $0.2173
For a hobbyist that wants to get a handful of tiny boards made the difference between 2 layer and 4 is huge.
Yes, but that's more because the 2 layer price is a loss-leader, than the 4 layer price is expensive.
When Parallax makes Eval Boards, I'm sure they plan on just a tad more than 'a handful'
Economies of scale come into play for productions runs.
My only little point here is that if one is putting out a design, open source, with the expectation that fellow hobbyists can get it built easily, perhaps tweaking and customizing it for their own purposes, then perhaps it's nice to to keep it 2 layer and hence cheap.
Of course that is not always possible.
@JMG: The final stencil design we used was a pattern of 9 rectangles equally spaced within the perimeter vias. This gave a wealth of solder paste to fill the center for heat transfer away from the parts, but also decent flow near the vias. There are many white papers and studies done on various patterns for thermal pad coverage. Common patterns are filling inner spaces between vias with squares/rectangles. Other patterns, like angled strips in between vias, etc. have been proven to be poor in comparison)
Unfortunately, with the 49 vias in this design, you end up with 36 rounded rectangles (rounded squares really) that will equate to roughly 50% paste coverage (similar as that shown in the document that Yanomani posted earlier, page 6, figure 6, far right image).
Also, with a PCB clearance of 0.5 to 0.15mm per the preliminary P2 datasheet (dimension A1), you really need to use a 5 mil stencil. (4mil is 0.1016mm, too near the center of the PCB clearance specs) Dimension C is missing (the lead thickness), but other TQFP100 datasheets reference lead thickness as 0.09-0.2mm.
Even at the thinner lead thickness and allowing for the lead to fully settle into the paste down to the pad during placement, the contact expectation of paste to the thermal pad requires a minimum of 4 mils. Using 4 mil stencil could create opens/voids on the ground pad if the paste in the center begins to reflow before the lead pad paste (part would float on the lead pads while the center pad paste settles/liquefies).
In all honesty, the TQFP100 with thermal pad could limit the use of a 4 mil stencil which could also limit the types of packages you can use for supporting circuitry in a P2 design. This could limit the size of design by restricting usage of smaller parts in certain packages. I rarely use 5 mils stencils on complex designs anymore because aperture sizes are too small for that thick of a stencil and violate aspect ratio or area ratio. Not sure of what partnering components will be used with the P2, but with all it's capable of, hopefully this doesn't pose long term challenges with heat dissipation. One could always use solder preforms under the part as well if a design truly required it.
JMG, do you have the ability to x-ray your power parts to verify voiding/coverage?
Perhaps if the board checks out and also checks out with P2 when it's ready, then maybe I can get a small run assembled.