Automated Testing of P2's

I've been working with ON Semi to get the P2 to be fully testable on their automatic tester.

They have their own test patterns for the digital side, but we need to also check the analog pad ring for manufacturing defects, which should cull about ~2.5% of devices, based on the pad ring area.

It's been a long journey with maybe 10 attempts and ONE more permitted tomorrow morning.

We were having all these problems where P2 chips were sporadically failing my analog test. I thought, initially it was some tester issue, and there were a few of those that we cleared out. Yesterday, I finally figured out what our lingering problem has been: Lack of thermal settling time when I enable the ADC on each pin.

In the SPICE simulation, I see that the circuit takes about 500ns to settle into bias and begin steady operation. What is NOT accounted for in the simulation, though, is self-heating effects. Things warm up and settle into some stasis that differs slightly from initial turn-on. This matters when 10-bit-quality measurements need to be taken, right from the start. I found that even giving 10us is enough time for things to thermally settle. I set the delay to 100us, though, to be sure.

You can run this test program, yourself, on the P2 Eval board by unloading all the pins and driving 1MHz into P62 via a 1k resistor:

' *****************************
' *  ATE test for Prop2 - v8  *
' *****************************
'
' This test gets run twice on the ATE machine at Vmin and Vmax
'
'   Vdd MIN = 1.8V - 5% - 30mV = 1.68V
'   Vio MIN = 3.3V - 5% - 30mV = 3.11V
'
'   Vdd MAX = 1.8V + 5% + 30mV = 1.92V
'   Vio MAX = 3.3V + 5% + 30mV = 3.50V
'
' This test passes on a prototype chip at the following voltage extremes:
'
'   Vdd MIN = 1.37V
'   Vio MIN = 2.17V
'
'   Vdd MAX = 2.00V
'   Vio MAX = 3.70V
'
' ATE test pattern:
'
'	ATE: for at least 30ms: GND(x16) = 0V, VDD(x16) = 1.8V, GIO(x16) = 0V, VIO(x16) = 3.3V
'	ATE: P0..P63 = Z, TEST = 0V, RESN = 0V
'	ATE: wait 10us
'	ATE: RESN = 3.3V, P59 = ~10k-ohm pull-up to 3.3V (or direct 3.3V if no resistor available), P63 = 3.3V
'	ATE: wait 6,000us
'	ATE: P59 = Z
'	ATE: P63 = data bitstream (0V/3.3V), each bit held for 500ns (18,786us total), see "DOWNLOAD_ATE_v8_????" files, last bit = Z
'	ATE: P62 = 1MHz (0V/3.3V), XI = 20MHz (0V/3.3V)
'	ATE: wait 5,000us
'	ATE: P62 = Z
'	ATE: wait 70,000us
'	ATE: if P[63:56] = 8'hC3 (0V/3.3V) and XO clocking at ~20MHz (0V/3.3V) then pass, else fail
'	ATE: all pins = Z, done
'

(more in the file below)
«134

Comments

  • Do you want us to test this, Chip? Or are you just posting for general info?
  • Hi Chip

    Only musing aloud...

    Any info about ATE environment (ambient) temperature, during the test runs?

    If there is a chilling environment, surrounding the test fixture, wouldn't be the case to provide some leeway at the timeout counts?

    Thinking about any possibility of marginal behavior; any observed cases, where 10 uS (or even 100 uS) weren't enough, but, says, if the timeout could, eventually, be extended to 1 mS, did the target test chip finally passed all the analog tests?
  • jmgjmg Posts: 13,609
    cgracey wrote: »
    ...
    In the SPICE simulation, I see that the circuit takes about 500ns to settle into bias and begin steady operation. What is NOT accounted for in the simulation, though, is self-heating effects. Things warm up and settle into some stasis that differs slightly from initial turn-on. This matters when 10-bit-quality measurements need to be taken, right from the start. I found that even giving 10us is enough time for things to thermally settle. I set the delay to 100us, though, to be sure.

    Do you need to push 10-bits / thermal settling levels, on a tester ?
    I would have expected the tester focus would be mainly testing speed, and a pass of even 8 bits would be ok ?

    Another, mounted-board-based test could be run to confirm the actual ENOB the P2 can deliver, which goes in the 'typical' column.

    For the serious noise-floor board mounted tests, I noticed these new ADC parts from Microchip
    They give 24b ADC with higher thruput speeds, which could track DAC and ADC noise levels on P2.

  • I need 10 bits of ADC resolution to confirm monotonicity of the three different 8-bit DACs.
  • I just posted this because someone might find it interesting. No need to run it. If you do run it, though, the four middle of the eight LEDs will light up to indicate "pass". Anything else means "fail".
  • Chip,
    Interesting results, so thanks for sharing. When you think about it, of course the chip temp is going to matter as it is warming up.
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • Here is the $10k load board they built to interface P2 to their tester.

    2250 x 3000 - 725K
    3000 x 2250 - 877K
  • cgraceycgracey Posts: 11,267
    edited 2019-06-28 - 01:58:49
    Cluso99 wrote: »
    Chip,
    Interesting results, so thanks for sharing. When you think about it, of course the chip temp is going to matter as it is warming up.

    Yes, and things like bias resistors and current regulating FETs climb to some stable temperature over ambient within microseconds. To perform accurate ADC conversions, for example, the circuit temperature must stabilize, first. Doesn't matter what the temperature is, just that it's stable.

    It's common for chips to have tiny hot spots due to analog circuits that run in the 7kW/cm2 range, even though they are only drawing a few mW. Those circuits get hot and quickly reach some stasis during operation. So, you'd better give them the settling time they need if you want them to work consistently.

    I should have realized earlier that something like this was going on, because I could see there were some time-related phenomena that exceeded what the nodal capacitances could have generated. Knowing that the power supply rails were not wandering all over, what else could be contributing to these longer-time-constant problems? They were due to thermal changes from enabling/disabling analog circuits. I hope we are on top of the situation now. This has taken so long to finalize that ON Semi is inclined to charge us for another man-week of time, and maybe even just abort the effort. We really need them to do this testing for us, though. We don't want to be opening vacuum sealed bags and having to do this as an additional step, in-house. It only adds 200ms to their automated testing time.
  • Mother dearing! :o

    Thick as a brick; expensive too: ~220 g of pure gold!

    For the first time, a (Yamaichi?) zif T&B connector seems too cheap to me.
  • jmgjmg Posts: 13,609
    cgracey wrote: »
    .... It only adds 200ms to their automated testing time.

    How do they handle the chips, for production run testing ?
    Surely they do not load manually into that ZIF socket ?
  • cgraceycgracey Posts: 11,267
    edited 2019-06-28 - 02:59:06
    jmg wrote: »
    cgracey wrote: »
    .... It only adds 200ms to their automated testing time.

    How do they handle the chips, for production run testing ?
    Surely they do not load manually into that ZIF socket ?

    This tester setup will be used for both wafer probing, which uses an even-more-expensive 'wafer probe card', and packaged-parts testing, which will handle two lanes of sockets with automated device handlers, using the 'load board' shown in the pictures. Right now, they have a single manual Yamaichi socket on there for test development. You can see on the back side of the 'load board' they have places around the DUT socket connectors for soldering bypass capacitors. They should have put a set of three strips between the DUT socket connectors for more-even bypassing. Their test engineer was telling me that they use time-domain-reflectometry to fine-align the tester signals with the DUT pins. He said that 'load board' is 18" across!
  • cgracey wrote: »
    Yes, and things like bias resistors and current regulating FETs climb to some stable temperature over ambient within microseconds. To perform accurate ADC conversions, for example, the circuit temperature must stabilize, first. Doesn't matter what the temperature is, just that it's stable.
    That begs the question now as to how much deviations occurred from this in those early ADC behavioural charts that were made with the first P2D2 boards.

    "... peers into the actual workings of a quantum jump for the first time. The results
    reveal a surprising finding that contradicts Danish physicist Niels Bohr's established view
    —the jumps are neither abrupt nor as random as previously thought."
  • Hi Chip,

    What is the 1MHz clock on pin 62 for? Sample clocking? Can I use a 3,3V CMOS digital clock generator for this? I have an homemade DDS signal generator that can produce the signal, but the jitter might not be ideal. It is not generated from the MSB created by the phase accumulator, but derived from the LP filtered signal via a fast comparator, so I think we are good.

    Kind regards, Samuel Lourenço
  • cgracey wrote: »
    jmg wrote: »
    cgracey wrote: »
    .... It only adds 200ms to their automated testing time.

    How do they handle the chips, for production run testing ?
    Surely they do not load manually into that ZIF socket ?

    This tester setup will be used for both wafer probing, which uses an even-more-expensive 'wafer probe card', and packaged-parts testing, which will handle two lanes of sockets with automated device handlers, using the 'load board' shown in the pictures. Right now, they have a single manual Yamaichi socket on there for test development. You can see on the back side of the 'load board' they have places around the DUT socket connectors for soldering bypass capacitors. They should have put a set of three strips between the DUT socket connectors for more-even bypassing. Their test engineer was telling me that they use time-domain-reflectometry to fine-align the tester signals with the DUT pins. He said that 'load board' is 18" across!

    Are you saying that every packaged chip gets put into that zif socket by a robot for testing???
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • cgraceycgracey Posts: 11,267
    edited 2019-06-28 - 15:29:48
    evanh wrote: »
    cgracey wrote: »
    Yes, and things like bias resistors and current regulating FETs climb to some stable temperature over ambient within microseconds. To perform accurate ADC conversions, for example, the circuit temperature must stabilize, first. Doesn't matter what the temperature is, just that it's stable.
    That begs the question now as to how much deviations occurred from this in those early ADC behavioural charts that were made with the first P2D2 boards.

    I wonder. In this case, different pins are briefly enabled into different analog modes and measurements are taken. I believe those P2D2 measurements were more steady-state.
  • samuell wrote: »
    Hi Chip,

    What is the 1MHz clock on pin 62 for? Sample clocking? Can I use a 3,3V CMOS digital clock generator for this? I have an homemade DDS signal generator that can produce the signal, but the jitter might not be ideal. It is not generated from the MSB created by the phase accumulator, but derived from the LP filtered signal via a fast comparator, so I think we are good.

    Kind regards, Samuel Lourenço

    That 1MHz signal into pin 62 is used in the first part of the test to measure PLL settings, to ensure that all PLL configuration bits are flexible and working. It doesn't need to be low-jitter.
  • cgraceycgracey Posts: 11,267
    edited 2019-06-28 - 15:34:33
    Cluso99 wrote: »
    cgracey wrote: »
    jmg wrote: »
    cgracey wrote: »
    .... It only adds 200ms to their automated testing time.

    How do they handle the chips, for production run testing ?
    Surely they do not load manually into that ZIF socket ?

    This tester setup will be used for both wafer probing, which uses an even-more-expensive 'wafer probe card', and packaged-parts testing, which will handle two lanes of sockets with automated device handlers, using the 'load board' shown in the pictures. Right now, they have a single manual Yamaichi socket on there for test development. You can see on the back side of the 'load board' they have places around the DUT socket connectors for soldering bypass capacitors. They should have put a set of three strips between the DUT socket connectors for more-even bypassing. Their test engineer was telling me that they use time-domain-reflectometry to fine-align the tester signals with the DUT pins. He said that 'load board' is 18" across!

    Are you saying that every packaged chip gets put into that zif socket by a robot for testing???

    The device handler will probably put the chip into a different type of socket that grabs the legs from the sides. That socket you see now is just for proving the test manually, before the robots take over.
  • SUCCESS!!!!

    The new test is working at ON Semi.

    Walt, their test engineer, even set up the temperature-control system and the whole test suite (ON's digital tests and Parallax's PLL/analog tests, together) was passing at 100C, at both Vmin and Vmax, at 180MHz. This demonstrates the test's production worthiness, as well.

    This is a huge relief, because had this test failed, ON was going to shelve the effort, pending further discussion and commitment.

    It's taken me maybe three solid weeks to get all this test stuff worked out. Now I can get back to Spin2.

    Walt is still running some tests and he and Wendy will be calling back shortly to discuss that outcome. I hope all goes well. It would be great to have this testing work nailed down.
  • Big Thumbs Up
  • VonSzarvas wrote: »
    Big Thumbs Up

    yup

    Re-inventing the wheel is not a waste of time if, when you are done, you understand why it is round.
  • Onward and upward!
    Infernal Machine
  • cgraceycgracey Posts: 11,267
    edited 2019-06-28 - 20:34:13
    So the test works at -55C to 105C.

    At -60C, the test program detects a >3% disparity from the expected full-scale output of a 2.0V DAC mode on some pins. In other words, the full-scale output ($FF), with the pull-down resistor turned on, measured either below 1.94V or above 2.06V. I could easily change the error-detection threshold to >6%, but it doesn't matter, as production testing will only be done at the hot temperature of 85C, where this problem doesn't show up. Mind you, the spec is for -40C to +85C ambient, so we are doing great.

    Walt is now testing the 30 chips at 85C which are going to be ESD-zapped and retested for ESD survivability.
  • cgraceycgracey Posts: 11,267
    edited 2019-06-28 - 19:53:06
    Walt just said that all 30 chips passed at 95C.

    Looks like we have a viable test program now. This is a huge problem out of the way.
  • Great news, Let the ESD zapping commence...

  • Great news, Chip! I am ever amazed by this entire process!
    Whit+

    "We keep moving forward, opening new doors, and doing new things, because we're curious and curiosity keeps leading us down new paths." - Walt Disney
  • Congratulations!

    Being able to follow the whole proccess and knowing how much commitment has been dedicated, untill that point was reached. It's amazing.
  • jmgjmg Posts: 13,609
    cgracey wrote: »
    ... but it doesn't matter, as production testing will only be done at the hot temperature of 85C, where this problem doesn't show up. ...

    Do OnSemi collect stats on the values (85C) of RCFAST and RCSLOW during this test ?
  • cgraceycgracey Posts: 11,267
    edited 2019-06-28 - 23:08:11
    jmg wrote: »
    cgracey wrote: »
    ... but it doesn't matter, as production testing will only be done at the hot temperature of 85C, where this problem doesn't show up. ...

    Do OnSemi collect stats on the values (85C) of RCFAST and RCSLOW during this test ?

    No. They don't know anything about our circuitry and don't want to know any more than is necessary to facilitate their digital checks.
  • cgracey wrote:
    Here is the $10k load board they built to interface P2 to their tester.
    Dang! I would've made one for you for $9500. :)

    -Phil
    “Perfection is achieved not when there is nothing more to add, but when there is nothing left to take away. -Antoine de Saint-Exupery
  • cgracey wrote:
    Here is the $10k load board they built to interface P2 to their tester.
    Dang! I would've made one for you for $9500. :)

    -Phil

    That Advantest T2000 machine that it connects to costs $2M:

    https://www.advantest.com/products/ic-test-systems/t2000

    It handles up to 8,192 digital signals.
Sign In or Register to comment.