I've been working with ON Semi to get the P2 to be fully testable on their automatic tester.
They have their own test patterns for the digital side, but we need to also check the analog pad ring for manufacturing defects, which should cull about ~2.5% of devices, based on the pad ring area.
It's been a long journey with maybe 10 attempts and ONE more permitted tomorrow morning.
We were having all these problems where P2 chips were sporadically failing my analog test. I thought, initially it was some tester issue, and there were a few of those that we cleared out. Yesterday, I finally figured out what our lingering problem has been: Lack of thermal settling time when I enable the ADC on each pin.
In the SPICE simulation, I see that the circuit takes about 500ns to settle into bias and begin steady operation. What is NOT accounted for in the simulation, though, is self-heating effects. Things warm up and settle into some stasis that differs slightly from initial turn-on. This matters when 10-bit-quality measurements need to be taken, right from the start. I found that even giving 10us is enough time for things to thermally settle. I set the delay to 100us, though, to be sure.
You can run this test program, yourself, on the P2 Eval board by unloading all the pins and driving 1MHz into P62 via a 1k resistor:
' * ATE test for Prop2 - v8 *
' This test gets run twice on the ATE machine at Vmin and Vmax
' Vdd MIN = 1.8V - 5% - 30mV = 1.68V
' Vio MIN = 3.3V - 5% - 30mV = 3.11V
' Vdd MAX = 1.8V + 5% + 30mV = 1.92V
' Vio MAX = 3.3V + 5% + 30mV = 3.50V
' This test passes on a prototype chip at the following voltage extremes:
' Vdd MIN = 1.37V
' Vio MIN = 2.17V
' Vdd MAX = 2.00V
' Vio MAX = 3.70V
' ATE test pattern:
' ATE: for at least 30ms: GND(x16) = 0V, VDD(x16) = 1.8V, GIO(x16) = 0V, VIO(x16) = 3.3V
' ATE: P0..P63 = Z, TEST = 0V, RESN = 0V
' ATE: wait 10us
' ATE: RESN = 3.3V, P59 = ~10k-ohm pull-up to 3.3V (or direct 3.3V if no resistor available), P63 = 3.3V
' ATE: wait 6,000us
' ATE: P59 = Z
' ATE: P63 = data bitstream (0V/3.3V), each bit held for 500ns (18,786us total), see "DOWNLOAD_ATE_v8_????" files, last bit = Z
' ATE: P62 = 1MHz (0V/3.3V), XI = 20MHz (0V/3.3V)
' ATE: wait 5,000us
' ATE: P62 = Z
' ATE: wait 70,000us
' ATE: if P[63:56] = 8'hC3 (0V/3.3V) and XO clocking at ~20MHz (0V/3.3V) then pass, else fail
' ATE: all pins = Z, done
(more in the file below)