P2 Smart Pin Diagram (Internals)?
JonnyMac
Posts: 9,506
A friend reached out asking if I knew of a good diagram detailing the internals of the P2 Smart Pins. I have seen such diagrams mixed into various threads, but can't seem to find them now. My memory -- which could be faulty as I've been working long hours -- tells me that @evanh has produced nice diagrams. If I'm correct, I hope he'll copy them here so that they're easier to find for myself and others. Forgive me if I'm wrong about the diagram creator; whoever you are, your work is appreciated, and I hope you'll post that great work in this thread.
Comments
https://p2docs.github.io/pin.html#diagram
Don't remember who originally made that.
Though @ikskuh at some point wanted to make a nicer SVG version, I recall, but IDK where that idea went.
Yeah, that was me. Based on @evanh text based drawing, as recall...
Here's the original ASCII art - https://forums.parallax.com/discussion/comment/1473762/#Comment_1473762
Copies from Ada's docs:
Copied from Evan's link.
***************************************************** *** Guide of where WRPIN config bits are used *** ***************************************************** All cogs share the one-per-pin mode config registers. WRPIN {#}D,{#}S D/# = %AAAA_BBBB_FFF_PPPPPPPPPPPPP_TT_MMMMM_0 : : ----------------------------------------------------------------- RND | : | : COG_DAC (Streamers/Cogs) | : [=============]<----------------------------- cog0 Other| : [ ]<----------------------------- cog1 | : [ DAC bus ]<----------------------------- cog2 | : [ select ]<----------------------------- cog3 v : [ ]<----------------------------- cog4 [=============] : DAC_MODE [ ]<----------------------------- cog5 [ Flash DAC ]<-------------[ (%P...P) ]<----------------------------- cog6 [ Network ] : [ (%TT) ]<----------------------------- cog7 [========] [ ] : [ (%MMMMM_0) ] [ ]<------------[ (%P...P) ] : [ ]<------------------------------ OUT [Physical] [ ] : driveH [ ]<---------------------------+-- DIR [ Even ] [ ]<-------------[ Logic Output] | [ Pin ] [ Pin Output ] : driveL [ ] SMART_DAC[============] | [ ]------ [ ]<-------------[ ]<---------[ ] | [========] | [=============] : [ ] SMART_OUT[ ]<--- | | ^ : ----[ ]<---------[ ] | | | : | [=============] [ ] | COMP_DAC| |Feed : | [ ] | | |back : | [ Odd # ] | v | : OUT| -1 -2 -3 [ Smartpin ] | [=============] : | | | | [ (%MMMMM_0) ] | PinB [ Comparator ] : | v v v [ ] -------->[ ] : | [=============] A [ ] | | PinA [ (%P...P) ] : --->[ Logic Input ]--------->[---o----o---]-------> IN | +----->[ ] : [ (%A_B_F) ] B [ (M == 0) ] | | [ Pin Input ]------------->[ ]--------->[ ] | | [ ] : [=============] [ ] | | [ Sigma-Delta ] : ^ ^ ^ [============] | | [ ADC ] : | | | | | [=============] : +1 +2 +3 | | : | | : | | : COG_DAC (Streamers/Cogs) | | : [=============]<----------------------------- cog0 | | |\ : [ ]<----------------------------- cog1 | +--------| |O--- Other : [ DAC bus ]<----------------------------- cog2 | | |/ | : [ select ]<----------------------------- cog3 | | v : [ ]<----------------------------- cog4 | | [=============] : DAC_MODE [ ]<----------------------------- cog5 | | [ Flash DAC ]<-------------[ (%P...P) ]<----------------------------- cog6 | | [ Network ] : [ (%TT) ]<----------------------------- cog7 | | [ ] : [ (%MMMMM_0) ] | | [ (%P...P) ] : [ ]<------------------------------ OUT [========] | | [ ] : driveH [ ]<---------------------------+-- DIR [ ]<------------[ ]<-------------[ Logic Output] | [Physical] | | [ Pin Output ] : driveL [ ] SMART_DAC[============] | [ Odd ] | | [ ]<-------------[ ]<---------[ ] | [ Pin ] | | [=============] : [ ] SMART_OUT[ ]<--- [ ]---+ | | ^ : ----[ ]<---------[ ] [========] | | | | : | [=============] [ ] | | COMP_DAC| |Feed : | [ ] | | | |back : | [ Odd # ] | | v | : OUT| -1 -2 -3 [ Smartpin ] | | [=============] : | | | | [ (%MMMMM_0) ] | | [ Comparator ] : | v v v [ ] | | [ ] : | [=============] A [ ] | | PinB [ (%P...P) ] : --->[ Logic Input ]--------->[---o----o---]-------> IN | ----->[ ] : [ (%A_B_F) ] B [ (M == 0) ] | PinA [ Pin Input ]------------->[ ]--------->[ ] -------->[ ] : [=============] [ ] [ Sigma-Delta ] : ^ ^ ^ [============] [ ADC ] : | | | [=============] : +1 +2 +3 : ....................... : .......................... : Custom I/O Pad Ring : : : Synthesised Core Logic : ''''''''''''''''''''''' : ''''''''''''''''''''''''''If he's interested in lots of detail then there is also the, mostly complete, schematic of the pad-ring - https://forums.parallax.com/discussion/comment/1494131/#Comment_1494131
And the sigma-delta ADC schematic is there too - https://forums.parallax.com/discussion/comment/1510744/#Comment_1510744
PS: I'm digging these up from the old links topic - https://forums.parallax.com/discussion/comment/1479568/#Comment_1479568