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P2 ADC timing

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  • evanhevanh Posts: 15,126

    What the hell are you smoking? I'm not about to go learning up the long dead horror IDE interface and subsequent late 90's ATA protocol (testable with a SATA adaptor) to then consume all the pins of a Propeller chip.

    IDE was one of the defining PC abominations that highlighted it as such a Smile computer of that era. It dragged the whole computer industry down with it.

    No more talk of such Smile, consider yourself warned now!

  • I don't understand your comment about the IDE and ATA100.
    The problem cannot be solved with SD cards, USB or Ram.
    On the other hand, I still have over 100 of them lying around (hardly used).
    Yes, I would have preferred SCSI Ultra 3, but the P2 doesn't have the pins and the clock is not feasible.
    The COGs were always over before the pin end.

  • evanhevanh Posts: 15,126
    edited 2021-10-26 01:28

    SD is fine. Default Speed is rated for 6 MB/s sustained. The sources need some work in better porting them over to the Prop2 is all. If need be, 4-bit mode can be added too. Or what might be easier, is going High Speed SPI mode.

  • evanhevanh Posts: 15,126

    Man, my prior working copy of FSRW is way broken for all current Spin2's. FlexSpin compiles it but it sure don't work. Pnut just pukes left right and centre. There is just a ton of illegal stuff in there for modern versions.

    I've started fixing things, mainly in sdspi_bashed.spin2 so far, but it seems never ending. Has anyone even vaguely recently tried making it work?

  • evanhevanh Posts: 15,126
    edited 2021-10-27 00:48

    It's clearly a Spin1 program with a .spin2 suffix. Have operator priorities changed from Spin1 to Spin2?

  • evanhevanh Posts: 15,126

    I've made progress - It now recognises a card is present. :)

  • evanhevanh Posts: 15,126

    Huh, got past the block-reading issue just by lowering sysclock to 80 MHz. It was at 250 MHz I don't know why. That's a fabulous result! It means two things:

    • I now have a working reference to fall back on each time I mess up the rework.
    • There is clearly plenty of scope for improvement when something like the sysclock can throw it off so badly.
  • evanhevanh Posts: 15,126

    That figures, the fix for the clockrate issue was as simple as tidy up the timing in the inner most bit-bashing.

  • I tried a bit with the code for an IDE.
    At 256Mhz I could transfer 37 Mbyts/s.
    The largest block would be 128k.
    Connection pin consumption 24.
    LBA24 or LBA48 could still be selected. I think 24 is enough for me.

  • pic18f2550pic18f2550 Posts: 392
    edited 2021-11-05 13:59

    Back to the topic of ADC.

    What is "bitstream capturing"?
    As I understand it so far, it is not a conversion of analog signals into a digital value.
    I guess it's something similar to a serial interface. (RX)

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