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## Comments

10,2226,480If you have a DAC's at your disposal and a comparator (an ADC in a 1=bit mode) then you have all you need.

It becomes a simple game of guess the number in as few steps as possible (A binary Search)... The only feedback you have is if your "guess" is higher or lower than the input. Each iteration defines your resolution.

For a simplistic example lets start with an arbitrary input voltage of 2.4V

Initial State:

RefLOW = 0V

RefHIGH = 3.3V

RefMID = (RefHIGH+RefLOW)>>1

*RefMID is what the DAC is loaded with, so the initial state is 1.65V

The simple rule for each itteration is:

After 8 iterations you get:

... the binary equivalent of the 8 bits is 186 .... 186/255 * 3.3V = 2.4V

23,186-Phil

13,69013,690I don't know enough to answer any of that, yet. EvanH is doing a lot of experiments and may come up with something useful.

13,690Jmg, I agree that the 6-bit weighting factor needs to be registered, ready to add at the start of the clock into the 32-bit accumulator.

I was talking about whether we should use a counter with variable increments, like TonyB_ had originally proposed, or a static logic implementation to generate the weighting factor from a counter. If we are going to have to have six flops for the waiting factor, we might as well just do a variable-increment counter, since it's smaller.

1,809Here is a new, shorter Tukey window (Tukey24/64) and unlike the earlier ones it has perfect symmetry: first+last=64, second+last but one=64, etc. The number of product terms is less than before so logic is smaller. Largest increment is bigger at +/- 4.

13,690Beautiful, TonyB_!

2,567For a SAR ADC you will need a Sample & Hold circuit so that the input voltage does not change during conversion. Otherwise you get quite wrong results.

Andy

13,690Ah, yes. We would need some kind of switch.

I guess we could always make a tracking ADC.

1,809And here is how the new Tukey24/64 looks, compared to the original. There are four zeroes and four 64s added merely as padding and only 24 samples are needed for each ramp (4-27 in this chart).

1,80913,690What a fantastic fit!

1,80913,690Super. Maybe it could top-out at 32.

1,809Now I've got the hang of this we could have max value of 32 or 64. I've called the new one tonight Tukey24/64 (samples/max) and we could have the following set:

Tukey16/32

Tukey16/64

Tukey24/32

Tukey24/64

374What if we could use a counter for the bulk of samples and just apply software windowing to the ends?

Doesn't solve the code resident problem, so that is one reason to have it in hardware. Another would be that it just makes the ADC easier to use.

1,809Increments:

Product terms (PTs):

1,809There is better resolution with max of 64.

12,23413,690I think that TonyB_ found that to get accuracy at these practical maximums of 32 and 64, the best fit was going into less than 16 or 32 positions, hence the zero fillers. I would imagine this is a net benefit to have a few zeros and get a much better fit.

To start with a '1', you must start the cosine from less than 180°, where the '1' would actually be.

12,234374I'm not sure yet whether the Tukey or the trapezoid is better. We really need to get an FFT of the bitstream to know how to tune the window function.

Note how Tukey24/64 has excellent rejection for a length-7 sequence. If the window function is adjustable that could be useful if some applications have high noise at particular frequencies.

14,884Don't those numbers assume the filter is always in line ?

In this ADC implementation, the filter is only present on ~1% of the samples - the first and last ones.

374I calculated with 4096 total samples, the window applies to 14-31 samples at each end. It's about 1% of samples with differing weights. So, the windowing could be done in software with little overhead if the hardware could handle the middle part that is all the same value.

14,884There are various ways to pack this, and it's not so easy to detail the least-logic in the final ASIC.

I did find that a D-FF is appx 6.5 NAND gate equivalents, so registers themselves are not a high cost.

Coding the last couple of cosine 64Y tables come in at 79PT & at 60 PT, of width 8 and for the minimum of 7 registers, - which is quite few gates, in those tables.

Another approach is to code what the tools should handle well, which could be

* A 7b+4B Sync Adder, with reset (as the output) - a small adder like this, should be compact

* A 4 register U/D/enable counter, with reset, for the eg +4..-4 step sizes (MSB sign extends as needed). In T-FF's this is 2PT per counter bit, widths up to 4, so is quite compact.

* A change decoder, IncEn/DecEn that extracts just the time to change up 1 or down 1 - this packs to appx 7PT/5PT widths of 8, for the lowest wide-PT count.

13,690SaucySoliton, thanks a lot for running those analyses. Within the bitstream, there are 7..2-bt repeating patterns.

Is there much extra benefit to going beyond 32 samples? Does an 8-sample window work much worse?

It would be good to know what would be optimal.

1,672We just now are solving problems we don't have. The propeller will never be used to sample a GHz signal like this is the case in communication networks. What we have to understand is: a value NEVER exists at a certain moment in time. That means: you can not measure a signal at a given "point" in time. That is what sampling wants to do, but never reaches. To have the best ADC you have to pay the highest price. It's just integration, that brought the price down. The type of ADC we have here is simple to understand: A signal is compared to another signal over and over. The input signal is what you want to know and the second signal is what you know already. This knowledge is the HISTORY of the unknown signal.

If you start the adc, the cap is not charged and both inputs: the signal and the compensation will charge the cap until the threshold of the comparator is reached. That moment we know: Now the input and feedback is balanced. And we just continue to keep this state by selecting a feedback according to the comparator output.

So every moment you just know: the input signal is higher or lower as the cap voltage. Only if you have knowledde of the history, how the cap was balanced, you know more exactly, what level the input voltage is. This knowledge of the history you gain from reading the feedback counter at different times.

And we are completely free to determine the time stamps. This should be according to the problem we solve.

In history, SA-ADCs were fast and cheap. Then DeltaSigma became better and cheaper. As they had to replace SA's. they were optimized to mimicry the "well understood" SA's.

There is something wrong with the streamer, there is no other reason to have the signal, the scope shows to us in start and tail. So just don't start or stop and we are fine. This ADC NEVER gives you a value, it only gives you the count of the compensation pulses you needed to balance the cap. Noise (shot noise) will always happen, but here we see a clear "signature" of the error.

There will be a next silicon it P2 is a success and if not, there will be a P2 as long as the fab makes chips. So let us focus on making the preexisting P2 a success to have the next generations!

12,234Chip was cheating posting those photos. All that has happened there is unclipped roll-over on the 8-bit DACs when outputting to the scope. I thought about saying something at the time but was tired.

PS: If you look at the voltage scale of 0.5 V/div you can see the trace is swinging more than 3.0 volts. That's rail-to-rail for the DACs.

1,672That is very close to my guessing.