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HDMI added to Prop2 - Page 7 — Parallax Forums

HDMI added to Prop2

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Comments

  • evanhevanh Posts: 10,914
    The documentation for HDMI says anything below 25MHz pixel rate must be double scanned. One of those annoying minimums that seemed to be rigidly maintain from very early on. Based on the VGA 31 kHz scan rate.

  • evanhevanh Posts: 10,914
    Here's the 1.3 spec I grab from the official site (I guessing posting this will be subject to take-down notices)
  • jmgjmg Posts: 14,662
    Wuerfel_21 wrote: »
    jmg wrote: »
    Another approach would be to increase the CLK in the HDMI section only
    how much silicon-space/money does a high-frequency PLL even cost? That could even end up in silicon. Either run the hdmi at slower main clocks or get higher resolutions.

    It costs quite a bit, as it is not standard verilog Flow.
    My suggestion was purely for testing in the FPGA, as the FPGA PLL is already there divided to get 80MHz.
    P2 has only one PLL, and that's in the custom PAD ring.
  • evanhevanh Posts: 10,914
    TonyB_ wrote: »
    Why all this 24 MHz talk? Spec says 25 MHz is the minimum pixel clock, therefore need 250 MHz to shift out the 10-bit codes.

    It's out of spec but not by much, so will probably work with most monitors/TVs. Expecting to go even further down would be inviting certain failure for sure.

  • jmgjmg Posts: 14,662
    Roy Eltham wrote: »
    Chip,
    Could you configure a 2 cog setup on the A9 FPGA and raise the fmax to something much higher for testing HDMI?

    Even 80MHz is 'overclocked', so 240/250MHz chip-wide is never going to make it.
    It might be possible to have a small area running at 250MHz, and co-operating with the streamer.
    Of course, that's then not quite the final verilog, so this FPGA variant custom testing path. is more proof of valid concept.

    P2 silicon should still be used to check Pin driver and skew/slew effects, which are outside of any verilog.
  • Is this not why Chip is going to use an FPGA build to make a bitstream, capture it, and then send it with P2A?

  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 22,980
    edited 2018-10-18 03:36
    So February/March comes around, the new silicon rev is delivered, then Lt. Columbo shows up:

    lt_columbo.jpg
    Sorry. Cain't he'p m'se'f. :)

    -Phil
    600 x 288 - 24K
  • cgraceycgracey Posts: 13,574
    Roy Eltham wrote: »
    Chip,
    Could you configure a 2 cog setup on the A9 FPGA and raise the fmax to something much higher for testing HDMI?

    Maybe. I'm thinking it would be best to just generate the data on the FPGA, serially send it to the P2, then have the P2 stream it out at full speed.
  • Cluso99Cluso99 Posts: 17,710
    edited 2018-10-18 07:23
    Skimming the pdf posted by Evan i note the following...

    The P2 I/O pins should be fine as the spec defines AVcc = 3V3 +-5%. The receiver (sink) terminates with a pullup to 3V3 of 50 ohm (but required to assume 100 ohm). The maximum differential voltage is 1.56V and minimum 0.15V. So for a low voltage out into a transmission line terminated with 100 ohm pullup, if the output resistance is 100 ohms total, the low voltage at the receiver (assuming zero cable resistance) would be 1/2 * 3V3 = 1.65V. So the output resistance would need to be a little over 100 ohm (actual value ~112 ohms). So we can easily meet this with P2. Probably a 100R series resistor will do fine for each output pin.

    Next issue is we have to supply +5V @ 55mA min (0.5A max) with over-current protection.

    Hot Plug Detect pin seems to be supplied from the receiver and is normally 2.4-5.3V via 1K +-20%.

    DDC is I2C and requires SCL and SDA have pullups on the source (P2) of 1K5-2K0. Interestingly high! The receiver requires a 47K pullup on SCL.

    The data being transmitted is 8 bits/channel but is transmitted as 10 bits via a lookup table to balance the 0 & 1 transmissions. THIS NEEDS FURTHER INVESTIGATION.

    Lastly there is mention of checksums and error checking and correction. Another possible problem.

    In summary, while I see it is quite possible to do HDMI, there are some issues with getting the transmission data into a form suitable for the streamer (or bit-banging) to output.

    BTW I am going to try and output an HDMI stream using bit-banging and multiple cogs. Peter is going to check the streams on a scope.
  • roglohrogloh Posts: 3,223
    edited 2018-10-18 09:18
    By the way, I've seen that simply capacitively coupling all HDMI TMDS signals (using 100nF caps) also seems to work for VGA resolution, at least with an FPGA. It most probably violates the spec though and who knows what type of spikes you can get on cable insert/removal. Doing something closer electrically to what CML does if at all possible with the P2 IO capabilities might be more preferable.
  • Roy Eltham wrote: »
    Rayman,
    Each P2 pin can do high speed serial. So you can just connect to P2's together with one or more pins and use that serial feature.
    You just write a byte/word/long to the smartpin and it spits it out serially.

    I see the P2 as the second coming of the transputer.
  • Heater.Heater. Posts: 21,233
    __red__
    I see the P2 as the second coming of the transputer.
    That is an awesome thought!

    Of course the XMOS devices were the second coming, what with having been architected by the same guy and having multiple cores and channel communications. https://www.xmos.com/developer/silicon/xcore200-general. XMOS does not seem to be into supporting hobbyists and tinkerers though, judging by their web site.









  • Roy Eltham wrote: »
    Rayman,
    Each P2 pin can do high speed serial. So you can just connect to P2's together with one or more pins and use that serial feature.
    You just write a byte/word/long to the smartpin and it spits it out serially.

    I see the P2 as the second coming of the transputer.
    Heater. wrote: »
    __red__
    I see the P2 as the second coming of the transputer.
    That is an awesome thought!

    The smart pins are a game-changer for fault tolerant systems in my view.

    Have you ever heard of erlang's OTP?

    I swear to the erlang's God's, I don't think the P2 could be a closer match for a hardware port architecturally (except more memory please (and that's an eternal requirement until we get 64G per cog) 😊).

    I don't know that I have the technical chops to port kernel erlang (but isn't that always the point?) yet, but an implementation of OTP is an obvious target which would allow us to build hardware that would continue to operate flawlessly even if you sawed your PCBs in half.

    I think I'll de-lurk my project.
  • Heater.Heater. Posts: 21,233
    I toyed with Erlang a few years ago. Gave me headache. After a while I still could not see how to get it to do what I wanted to do at the time so I moved on. Perhaps I should have another look.
  • K2K2 Posts: 684
    Hybrid Parallax parallel processing in one month. :)

    Now where's my copy of Occam??

    T800.jpg
    1785 x 1246 - 355K
    T800.jpg 355.2K
  • Heater. wrote: »
    I toyed with Erlang a few years ago. Gave me headache. After a while I still could not see how to get it to do what I wanted to do at the time so I moved on. Perhaps I should have another look.

    Take a look at elixir. It's a language with a syntax that's more typical to modern languages and compiles down to the exact same code. It lessens the learning-wall significantly for a lot of people.
  • Heater.Heater. Posts: 21,233
    Nooo....Yet Another F. Language....YAFL.

    Looks interesting. Just now I'm busy with Verilog and Scala.
  • RaymanRayman Posts: 11,966
    The TFP410 dvi transmitter also has a minimum clock of 25 MHz.
    Guess we're looking at a hard floor here...
    Seems like 250 MHz clock is going to be the minimum required...
  • Horizontal Pixels 800 (Active: 640) Vertical Pixels 525 (Active: 480) at 60Hz: 250MHz

    But going down to 24fps, you should be able to get higher resolution like xga: Active1024x768 needs 260MHz

    These would be pushing it:
    Active 1368x768 needs 340Mhz
    720P (active 1280x720) needs 360MHz
  • Do TVs/Monitors support 960i? that'd have the same bandwidth as 480p
  • tonyp12 wrote: »
    These would be pushing it:
    Active 1368x768 needs 340Mhz
    720P (active 1280x720) needs 360MHz

    Why does a lower resolution require a higher frequency ?

    j
  • K2 wrote: »
    Hybrid Parallax parallel processing in one month. :)

    Now where's my copy of Occam??

    Where did you get a pair of T-800s? :D
  • tonyp12tonyp12 Posts: 1,950
    edited 2018-10-18 17:51
    Why does a lower resolution require a higher frequency ?

    Larger front and back porch, 720P24 total pixel is 1980x750
    unless the site have an error, but it seems the lower the fps the bandwith savings is not liner as porch increases for hdtv resolutions but not for vga styles.
    https://k.kramerav.com/support/bwcalculator.asp

  • cgraceycgracey Posts: 13,574
    edited 2018-10-18 18:58
    thej wrote: »
    tonyp12 wrote: »
    These would be pushing it:
    Active 1368x768 needs 340Mhz
    720P (active 1280x720) needs 360MHz

    Why does a lower resolution require a higher frequency ?

    j

    It has to do with the original DVI spec from 1999, where they said that if a packet clock rate of less than 22MHz is detected, then shut off. This has to do with the design of PLL's and their bottom-end lock range. So, signaling at less than 220MHz is verboten.
  • TonyB_TonyB_ Posts: 1,701
    edited 2018-10-18 19:37
    720x480 @ 60Hz and 720x576 @ 50Hz require a 27 MHz pixel clock, which should be achievable. The latter tweaked to run at 28 MHz has been proven to work with at least one HDMI TV:
    http://joco.homeserver.hu/zxpipi/

    I don't know whether or not 640x480 @ 50Hz is supported on HDMI.
  • cgracey wrote: »
    So, signaling at less than 220MHz is verboten.

    Sorry. Cain't he'p m'se'f. :)

    I couldn't, either...

    verboten.png
    1572 x 1050 - 2M
  • K2K2 Posts: 684
    pedward wrote: »
    Where did you get a pair of T-800s? :D
    It's a trio - I didn't show the rest of the board. Inmos gave me the first first one. The other two were purchased.

  • K2 wrote: »
    pedward wrote: »
    Where did you get a pair of T-800s? :D
    It's a trio - I didn't show the rest of the board. Inmos gave me the first first one. The other two were purchased.

    Pretty cool. I worked on digital TV decoders back in the 90's where we used ST's crippled versions of the Transputer in their MPEG decoders.

    Neat architecture.
  • TonyB_TonyB_ Posts: 1,701
    edited 2018-10-22 23:55
    I've done TMDS encoding in software. 204 byte values have two encoded values the same and 52 all three, making a total of 460 different codes which is the correct number and they all decode correctly.

    8b = 8-bit input
    10b+ = 10-bit output when disparity input is positive
    10b0 = 10-bit output when disparity input is zero
    10b- = 10-bit output when disparity input is negative
    disparity = number of '1' bits - number of '0' bits for 8-bit value
    #8b,10b+,10b0,10b-
    00,100,100,3FF
    01,300,1FF,1FF
    02,301,1FE,1FE
    03,101,101,3FE
    04,303,1FC,1FC
    05,103,103,3FC
    06,102,102,3FD
    07,302,1FD,1FD
    08,307,1F8,1F8
    09,107,107,3F8
    0A,106,106,3F9
    0B,306,1F9,1F9
    0C,104,104,3FB
    0D,304,1FB,1FB
    0E,305,1FA,1FA
    0F,105,105,3FA
    10,1F0,1F0,1F0
    11,10F,10F,10F
    12,10E,10E,3F1
    13,30E,1F1,1F1
    14,10C,10C,3F3
    15,30C,1F3,1F3
    16,30D,1F2,1F2
    17,10D,10D,3F2
    18,108,108,3F7
    19,308,1F7,1F7
    1A,309,1F6,1F6
    1B,109,109,3F6
    1C,30B,1F4,1F4
    1D,10B,10B,3F4
    1E,0A0,25F,25F
    1F,2A0,2A0,05F
    20,1E0,1E0,31F
    21,3E0,11F,11F
    22,11E,11E,11E
    23,1E1,1E1,1E1
    24,11C,11C,3E3
    25,31C,1E3,1E3
    26,1E2,1E2,1E2
    27,11D,11D,11D
    28,118,118,3E7
    29,318,1E7,1E7
    2A,319,1E6,1E6
    2B,119,119,3E6
    2C,1E4,1E4,1E4
    2D,11B,11B,11B
    2E,0B0,24F,24F
    2F,2B0,2B0,04F
    30,110,110,3EF
    31,310,1EF,1EF
    32,311,1EE,1EE
    33,111,111,3EE
    34,313,1EC,1EC
    35,113,113,3EC
    36,247,247,247
    37,2B8,2B8,2B8
    38,1E8,1E8,1E8
    39,117,117,117
    3A,243,243,0BC
    3B,043,2BC,2BC
    3C,241,241,0BE
    3D,041,2BE,2BE
    3E,040,2BF,2BF
    3F,240,240,0BF
    40,1C0,1C0,33F
    41,3C0,13F,13F
    42,3C1,13E,13E
    43,1C1,1C1,33E
    44,13C,13C,13C
    45,1C3,1C3,1C3
    46,1C2,1C2,33D
    47,3C2,13D,13D
    48,138,138,3C7
    49,338,1C7,1C7
    4A,1C6,1C6,1C6
    4B,139,139,139
    4C,1C4,1C4,33B
    4D,3C4,13B,13B
    4E,090,26F,26F
    4F,290,290,06F
    50,130,130,3CF
    51,330,1CF,1CF
    52,331,1CE,1CE
    53,131,131,3CE
    54,1CC,1CC,1CC
    55,133,133,133
    56,098,267,267
    57,298,298,067
    58,1C8,1C8,337
    59,3C8,137,137
    5A,263,263,263
    5B,29C,29C,29C
    5C,261,261,09E
    5D,061,29E,29E
    5E,060,29F,29F
    5F,260,260,09F
    60,120,120,3DF
    61,320,1DF,1DF
    62,321,1DE,1DE
    63,121,121,3DE
    64,323,1DC,1DC
    65,123,123,3DC
    66,088,277,277
    67,288,288,077
    68,1D8,1D8,1D8
    69,127,127,127
    6A,08C,273,273
    6B,28C,28C,073
    6C,271,271,271
    6D,28E,28E,28E
    6E,070,28F,28F
    6F,270,270,08F
    70,1D0,1D0,32F
    71,3D0,12F,12F
    72,084,27B,27B
    73,284,284,07B
    74,086,279,279
    75,286,286,079
    76,287,287,287
    77,278,278,278
    78,082,27D,27D
    79,282,282,07D
    7A,283,283,07C
    7B,083,27C,27C
    7C,281,281,07E
    7D,081,27E,27E
    7E,080,27F,27F
    7F,280,280,07F
    80,180,180,37F
    81,380,17F,17F
    82,381,17E,17E
    83,181,181,37E
    84,383,17C,17C
    85,183,183,37C
    86,182,182,37D
    87,382,17D,17D
    88,178,178,178
    89,187,187,187
    8A,186,186,379
    8B,386,179,179
    8C,184,184,37B
    8D,384,17B,17B
    8E,0D0,22F,22F
    8F,2D0,2D0,02F
    90,170,170,38F
    91,370,18F,18F
    92,18E,18E,18E
    93,171,171,171
    94,18C,18C,373
    95,38C,173,173
    96,227,227,227
    97,2D8,2D8,2D8
    98,188,188,377
    99,388,177,177
    9A,223,223,0DC
    9B,023,2DC,2DC
    9C,221,221,0DE
    9D,021,2DE,2DE
    9E,020,2DF,2DF
    9F,220,220,0DF
    A0,160,160,39F
    A1,360,19F,19F
    A2,361,19E,19E
    A3,161,161,39E
    A4,19C,19C,19C
    A5,163,163,163
    A6,0C8,237,237
    A7,2C8,2C8,037
    A8,198,198,367
    A9,398,167,167
    AA,233,233,233
    AB,2CC,2CC,2CC
    AC,231,231,0CE
    AD,031,2CE,2CE
    AE,030,2CF,2CF
    AF,230,230,0CF
    B0,190,190,36F
    B1,390,16F,16F
    B2,0C4,23B,23B
    B3,2C4,2C4,03B
    B4,239,239,239
    B5,2C6,2C6,2C6
    B6,038,2C7,2C7
    B7,238,238,0C7
    B8,0C2,23D,23D
    B9,2C2,2C2,03D
    BA,2C3,2C3,2C3
    BB,23C,23C,23C
    BC,2C1,2C1,03E
    BD,0C1,23E,23E
    BE,0C0,23F,23F
    BF,2C0,2C0,03F
    C0,140,140,3BF
    C1,340,1BF,1BF
    C2,341,1BE,1BE
    C3,141,141,3BE
    C4,343,1BC,1BC
    C5,143,143,3BC
    C6,217,217,217
    C7,2E8,2E8,2E8
    C8,1B8,1B8,1B8
    C9,147,147,147
    CA,213,213,0EC
    CB,013,2EC,2EC
    CC,211,211,0EE
    CD,011,2EE,2EE
    CE,010,2EF,2EF
    CF,210,210,0EF
    D0,1B0,1B0,34F
    D1,3B0,14F,14F
    D2,21B,21B,21B
    D3,2E4,2E4,2E4
    D4,219,219,0E6
    D5,019,2E6,2E6
    D6,018,2E7,2E7
    D7,218,218,0E7
    D8,21D,21D,21D
    D9,2E2,2E2,2E2
    DA,01C,2E3,2E3
    DB,21C,21C,0E3
    DC,2E1,2E1,2E1
    DD,21E,21E,21E
    DE,0E0,21F,21F
    DF,2E0,2E0,01F
    E0,1A0,1A0,35F
    E1,3A0,15F,15F
    E2,20B,20B,0F4
    E3,00B,2F4,2F4
    E4,209,209,0F6
    E5,009,2F6,2F6
    E6,008,2F7,2F7
    E7,208,208,0F7
    E8,20D,20D,0F2
    E9,00D,2F2,2F2
    EA,00C,2F3,2F3
    EB,20C,20C,0F3
    EC,00E,2F1,2F1
    ED,20E,20E,0F1
    EE,20F,20F,20F
    EF,2F0,2F0,2F0
    F0,205,205,0FA
    F1,005,2FA,2FA
    F2,004,2FB,2FB
    F3,204,204,0FB
    F4,006,2F9,2F9
    F5,206,206,0F9
    F6,207,207,0F8
    F7,007,2F8,2F8
    F8,002,2FD,2FD
    F9,202,202,0FD
    FA,203,203,0FC
    FB,003,2FC,2FC
    FC,201,201,0FE
    FD,001,2FE,2FE
    FE,000,2FF,2FF
    FF,200,200,0FF
    
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