Rayman,
Each P2 pin can do high speed serial. So you can just connect to P2's together with one or more pins and use that serial feature.
You just write a byte/word/long to the smartpin and it spits it out serially.
So, maybe chances of anybody wanting to connect two P2 is low...
I'm sure that will be done.
Smart Pin Cells can shift up to 32 bits in Serial modes.
ASYNC is simplest, but usually has some clock limit, /8 seems widely used, /6 and /4 are stretch numbers, and if both P2s share the same clock generation, then /4 could work.
Above that I think there are external clock modes for SPI and streamer, but those will be sysCLK sampled, so the likely limit there is <= SysCLK / 2 max (same SysCLK)
Given the high code clk numbers being reported, it's likely the pin-io itself will limit the highest link speeds.
Anyone lucky enough to have two P2 boards they can connect & test P2-P2 links ?
Without any exceptional agreement by ON Semi, they are going to send us 175 Amkor-packaged chips on November 8. There are more chips which could be packaged from the first wafer run, but they don't want to ship too much before the product qualification is complete. These 175 should be enough to get everyone started. This came up in a discussion last week. Yes, there are enough to make 1500 chips, but their business model is not in agreement with turning those into a production run. If we wind up needing more chips, I think they'll help us out, but for now, we've only got 175 of them coming.
Hmm, that's sounding a bit light, given there are two PCBs that will be targeted for builds ? (P2D2x, and your own Parallax one)
Any chance they can nudge that a little, maybe 175 for each PCB flow ?
Many boards will not be live-testing all the time, I'd say you need higher numbers to get the best test coverage.
Seems there should be a digital version of an "arbitrary waveform generator" that we could use to test the P2V bitstream with an HDMI monitor for sanity checking...
I looked around work for something, but couldn't find anything that does digital that fast...
It would be very good if we could run a P2 at 240MHz and clock out DVI/HDMI video at this frequency instead of the usual 250MHz in those cases where you are also wanting USB as well as the digital video, as this 240MHz is a nice multiple of 12MHz for USB. However I'm not sure that all monitors will reliably sync up to this lower 24MHz pixel clock using HDMI/DVI and display the output; that may be very monitor dependent.
There's nothing really stopping an HDMI/DVI monitor from receiving the actual TMDS bitstream at the lower frequency but it will affect the frame refresh rate if you don't also reduce the total number of lines sent accordingly (such as sending 504 instead of 525 to compensate). Having too low a frame rate is likely something that could upset a monitor the most if it just expects to run at 60Hz, but it's not too far off (96%) and might even work okay. I imagine HDTVs are probably somewhat fussier than PC monitors in detecting and accepting standard resolution/frame rates. PC monitors hopefully don't care quite as much. My older Dell monitors can take a huge range of lines and frame rates you throw at it over DVI for example, but that may not be the norm in the TV world.
If it turns out that operating at 240MHz is a problem for DVI/HDMI then perhaps with more effort we can go the other way and get USB operating with the 250MHz P2 clock but that will need some inserted clock skips here and there, so the USB sampling code and/or smart pin timing control may start to get ugly in that case. I expect it's probably going to be much easier to try to clock HDMI at 240MHz whenever you need your USB as well. Unfortunately HDMI audio has some timing dependencies on the video clock too and I know this would need adjustments if you want to keep it working at the correct sample rate. But that's something for another day...
I think it would just be nice to have both USB devices and also a VGA resolution over DVI/HDMI working on a P2. Keep the cake and eat it too.
It would be very good if we could run a P2 at 240MHz and clock out DVI/HDMI video at this frequency instead of the usual 250MHz in those cases where you are also wanting USB as well as the digital video, as this 240MHz is a nice multiple of 12MHz for USB....
I think it would just be nice to have both USB devices and also a VGA resolution over DVI/HDMI working on a P2. Keep the cake and eat it too.
USB works now with 80MHz, so it does not appear to be that important to have "a nice multiple of 12MHz".
The NCO generates a 12MHz timing to 1/SysCLK jitter, so higher sysclks only improve on that jitter.
I think we are still waiting on USB on P2-Silicon test confirmation, and how SysCLK changes affect the USB code (if at all)
I don't think there are any issues with USB at 250MHz. I hoped to get to 192MHz because of the multiplier. If necessary, some extra wait states could be inserted. This is for bit-banging USB FS. Gary has used the smart pins and it's running at 80MHz on the FPGA so I think we are good to go at anything >=192MHz
As for HDMI, it's all digital. I am unsure if the actual HDMI clock rate matters that much.
Great! From reading various earlier comments about 192MHz operation for USB etc it seems I believed that there was (still) some synchronous aspect to the USB implementation on a P2. Guess I've not been keeping up with current events!
HDMI supports 24 Hz modes, as well as interlaced modes. Most TVs support them. Some (most?) TVs will also accept 240p/60Hz over HDMI. Not sure whether they actually lower the pixel clock or just insert lots of padding.
Could be useful for testing the P2 HDMI generator. I don't know of many devices that actually put out 480p/24Hz or any 15kHz linerate modes (for testing whether the display supports them and for comparing the waveforms to P2) All of them are obscure-ish gaming related video processors.
HDMI supports 24 Hz modes, as well as interlaced modes. Most TVs support them. Some (most?) TVs will also accept 240p/60Hz over HDMI. Not sure whether they actually lower the pixel clock or just insert lots of padding.
Could be useful for testing the P2 HDMI generator. I don't know of many devices that actually put out 480p/24Hz or any 15kHz linerate modes (for testing whether the display supports them and for comparing the waveforms to P2) All of them are obscure-ish gaming related video processors.
Hmm, that's a bummer. Of course one might just try their luck and see if it works anyways. 240p mode would likely have the same timing as NTSC 240p. The actual clock is not that important. Some old computers output a whopping 62Hz framerate and it mostly works when translated to HDMI.
Any chance you could implement hdmi encoding only in a second fpga?
Another approach would be to increase the CLK in the HDMI section only, so the P2 Clock is 80MHz,(or 72MHz?) but the HDMI cell is run at 240MHz, and the streamer then paces at 24MHz 32b feeds.
Another approach would be to increase the CLK in the HDMI section only
how much silicon-space/money does a high-frequency PLL even cost? That could even end up in silicon. Either run the hdmi at slower main clocks or get higher resolutions.
Comments
So, maybe chances of anybody wanting to connect two P2 is low...
Each P2 pin can do high speed serial. So you can just connect to P2's together with one or more pins and use that serial feature.
You just write a byte/word/long to the smartpin and it spits it out serially.
One P2 for programs and the other for graphics.
Seeing as there is a 110nm, 16 core, 1MB Hub, 400MHz+ (overclocked) P2 "on the horizon", this could be quite a snappy little system !
J
I'm sure that will be done.
Smart Pin Cells can shift up to 32 bits in Serial modes.
ASYNC is simplest, but usually has some clock limit, /8 seems widely used, /6 and /4 are stretch numbers, and if both P2s share the same clock generation, then /4 could work.
Above that I think there are external clock modes for SPI and streamer, but those will be sysCLK sampled, so the likely limit there is <= SysCLK / 2 max (same SysCLK)
Given the high code clk numbers being reported, it's likely the pin-io itself will limit the highest link speeds.
Anyone lucky enough to have two P2 boards they can connect & test P2-P2 links ?
Hmm, that's sounding a bit light, given there are two PCBs that will be targeted for builds ? (P2D2x, and your own Parallax one)
Any chance they can nudge that a little, maybe 175 for each PCB flow ?
Many boards will not be live-testing all the time, I'd say you need higher numbers to get the best test coverage.
Do you mean packaged parts, in your hands ? - or is that the wafer-run timing, to which needs to add packaging & test ?
How many parts will be in that shuttle run ? It looks like those 175 parts, need to last many months ?
What did Chip say? Did I miss something?
I looked around work for something, but couldn't find anything that does digital that fast...
There's nothing really stopping an HDMI/DVI monitor from receiving the actual TMDS bitstream at the lower frequency but it will affect the frame refresh rate if you don't also reduce the total number of lines sent accordingly (such as sending 504 instead of 525 to compensate). Having too low a frame rate is likely something that could upset a monitor the most if it just expects to run at 60Hz, but it's not too far off (96%) and might even work okay. I imagine HDTVs are probably somewhat fussier than PC monitors in detecting and accepting standard resolution/frame rates. PC monitors hopefully don't care quite as much. My older Dell monitors can take a huge range of lines and frame rates you throw at it over DVI for example, but that may not be the norm in the TV world.
If it turns out that operating at 240MHz is a problem for DVI/HDMI then perhaps with more effort we can go the other way and get USB operating with the 250MHz P2 clock but that will need some inserted clock skips here and there, so the USB sampling code and/or smart pin timing control may start to get ugly in that case. I expect it's probably going to be much easier to try to clock HDMI at 240MHz whenever you need your USB as well. Unfortunately HDMI audio has some timing dependencies on the video clock too and I know this would need adjustments if you want to keep it working at the correct sample rate. But that's something for another day...
I think it would just be nice to have both USB devices and also a VGA resolution over DVI/HDMI working on a P2. Keep the cake and eat it too.
USB works now with 80MHz, so it does not appear to be that important to have "a nice multiple of 12MHz".
The NCO generates a 12MHz timing to 1/SysCLK jitter, so higher sysclks only improve on that jitter.
I think we are still waiting on USB on P2-Silicon test confirmation, and how SysCLK changes affect the USB code (if at all)
As for HDMI, it's all digital. I am unsure if the actual HDMI clock rate matters that much.
Mike
Great! From reading various earlier comments about 192MHz operation for USB etc it seems I believed that there was (still) some synchronous aspect to the USB implementation on a P2. Guess I've not been keeping up with current events!
This is good to know.
Could be useful for testing the P2 HDMI generator. I don't know of many devices that actually put out 480p/24Hz or any 15kHz linerate modes (for testing whether the display supports them and for comparing the waveforms to P2) All of them are obscure-ish gaming related video processors.
Is the RaspPi any help here ?
I find
https://weblogs.asp.net/bleroy/getting-your-raspberry-pi-to-output-the-right-resolution
https://www.raspberrypi.org/forums/viewtopic.php?f=26&t=5851
I see there these lower end options, and the first post shows how to query supported modes.
HDMI_CEA_240p60 = 8
HDMI_CEA_240p60H = 9
HDMI_CEA_288p50 = 23
HDMI_CEA_288p50H = 24
HDMI_CEA_288p50_4x = 27
HDMI_CEA_288p50_4xH = 28
HDMI_CEA_720p24 = 60
HDMI_CEA_720p25 = 61
HDMI_CEA_720p30 = 62
..
HDMI_DMT_640x350_85 = 0x1, /**<640x350 */
HDMI_DMT_640x400_85 = 0x2, /**<640x400 */
HDMI_DMT_IBM_VGA_85 = 0x3, /**<720x400 */
HDMI_CEA_240p60 = 8
HDMI_CEA_240p60H = 9
HDMI_CEA_288p50 = 23
HDMI_CEA_288p50H = 24
HDMI_CEA_288p50_4x = 27
HDMI_CEA_288p50_4xH = 28
From HDMI spec v1.4:
Video formats with native pixel rates below 25 Mpixels/sec require pixel-repetition in order to be carried across a TMDS link.
But think 60hz
It's probably still a good idea to run a P2-silicon test, to check pin-skew and termination effects ?
Newhaven hdmi lcd uses tfp401 receiver with 25 MHz min clock
Another approach would be to increase the CLK in the HDMI section only, so the P2 Clock is 80MHz,(or 72MHz?) but the HDMI cell is run at 240MHz, and the streamer then paces at 24MHz 32b feeds.
Could you configure a 2 cog setup on the A9 FPGA and raise the fmax to something much higher for testing HDMI?