SFUNC question

jmg · 2017-04-30 03:48

AJL wrote: »

Is BITOR essentially the same as?

if_c    BITC D,{#}S

I make that equiv to Bit = Bit OR C, not quite the same as C = BIT OR C ?
Bit = Bit OR C is nice to have, but I'd implement C = BIT OR C first.

jmg · 2017-04-30 03:57

cgracey wrote: »

There is need for source and destination to be any of C, Z, and a register bit. You'd want to be able to make a register bit the destination, as well as a flag, and have operations between flags. I gotta' think about what that would look like.

Expanding on the 8051 opcodes, I have this table :

8051 C.BIT Opcodes  P2 C.BIT opcodes
CLR C               SETCZ  #11  WC   alias coded
CLR bit             BITL     Clear bit S[4:0] of D.
SETB C              SETCZ  #00  WC    alias coded
SETB bit            BITH     Set bit S[4:0] of D
CPL C               NOTC   *new
CPL bit             BITN     Not bit S[4:0] of D.
ANL C, bit          ANDC  *new
ANL C, /bit         ?
ORL C, bit          ORC    *new
ORL C, /bit         ?
MOV C, bit          TESTB  wc  Test bit. C/!Z = bit S[4:0] of D.
MOV bit, C          BITC     Set bit S[4:0] of D to C.
JC rel              IF_C     JMP
JNC rel             IF_NC    JMP
JB bit, rel         TESTB + JC  Two lines
JNB bit, rel        TESTB + JNC Two lines
JBC bit, rel        [Jump Bit and Clear, not on P2]
RL A                ROL  Rotate left
RLC A               RCL  Rotate carry left
RR A                ROR  Rotate right.
RRC A               RCR  Rotate carry right.

Note they do not have BIT AND BIT, but the AND.OR operations are saved to C only.

"You'd want to be able to make a register bit the destination, as well as a flag, and have operations between flags"
True for moves, but for the operators, you can limit to destination as flag only, if space is an issue.
If C and Z aliased into accessible bit space, that would allow your operations between flags

Cluso99 · 2017-04-30 04:35

cgracey wrote: »

Cluso99,
.....
I also made new CLC/STC-type instructions to easily affect the flags:

-------
aliases
-------

CLC                             =       RCZR    #%00        WC
STC                             =       RCZR    #%10        WC
CLZ                             =       RCZR    #%00        WZ
STZ                             =       RCZR    #%01        WZ
CLC_CLZ                         =       RCZR    #%00        WC,WZ
CLC_STZ                         =       RCZR    #%01        WC,WZ
STC_CLZ                         =       RCZR    #%10        WC,WZ
STC_STZ                         =       RCZR    #%11        WC,WZ

As was pointed out, CLx and STx names are not that clear (pardon the pun)?

What about these aliases (presuming SETCZ is gone)?

SETNC
SETC
SETNZ
SETZ
SETNCNZ
SETNCZ
SETCNZ
SETCZ

jmg · 2017-04-30 04:46

Cluso99 wrote: »
What about these aliases (presuming SETCZ is gone)?
SETNC
SETC
SETNZ
SETZ
SETNCNZ
SETNCZ
SETCNZ
SETCZ

SETC makes sense, and does what it says.

However, SETNZ is rather convoluted, first it says SET (which most understand means make HI), and then it says NOT Carry, so I think the double-negative here is a very long winded way of saying what others already use CLRC (or CLC) to say.

cgracey · 2017-04-30 04:58

Cluso99 wrote: »

show previous quotes

As was pointed out, CLx and STx names are not that clear (pardon the pun)?

What about these aliases (presuming SETCZ is gone)?

SETNC
SETC
SETNZ
SETZ
SETNCNZ
SETNCZ
SETCNZ
SETCZ

I like yours better.

cgracey · 2017-04-30 05:00

jmg wrote: »
show previous quotes
Cluso99 wrote: »
What about these aliases (presuming SETCZ is gone)?
SETNC
SETC
SETNZ
SETZ
SETNCNZ
SETNCZ
SETCNZ
SETCZ
SETC makes sense, and does what it says.

However, SETNZ is rather convoluted, first it says SET (which most understand means make HI), and then it says NOT Carry, so I think the double-negative here is a very long winded way of saying what others already use CLRC to say.

If you want to mix them into one root word, and set both flags differently, you can't use SETxx or CLRxx. I attempted to do something like that with my names, but they weren't that good.

jmg · 2017-04-30 05:13

cgracey wrote: »

If you want to mix them into one root word, and set both flags differently, you can't use SETxx or CLRxx. I attempted to do something like that with my names, but they weren't that good.

Understood, but the effort at seeking one root word, should not result in opcodes that by themselves then look silly.
If you wanted a single root word, I'd favour BIT, and include C,Z in that group.

However, I notice 8051 & AVR have not given priority to one root word, instead they use

SETB  BitName, SETB   C,  in 8051
CLR BitName, CLR  C,  in 8051
SBI or SBR or SEC  in AVR (tho here they also use SBIC for Skip-bit-is-clear)
CBI or CBR or CLC in AVR

To me, the 8051 is cleaner, as they simply use C or BitName as an operand, whilst AVR is turning into spaghetti soup...
In P2 land, the extension here for C,Z would be something like

SETB   CZ
CLR    CZ
or 
SETB   C,Z
CLR    C,Z

AVR has this collection of mnemonics for all their 'Set' flags

SBI - Set Bit in I/O Register
SBR - Set Bits in Register
SEC - Set Carry Flag
SEH - Set Half Carry Flag
SEI - Set Global Interrupt Flag
SEN - Set Negative Flag
SER - Set all bits in Register
SES - Set Signed Flag
SET - Set T Flag
SEV - Overflow Flag
SEZ - Set Zero Flag

whilst 8051 uses
SETB  ReservedName ; where Reserved name is one of C CY AC F0 RS1 RS0 OV F1 P

potatohead · 2017-04-30 05:35

SETNC
SETC
SETNZ
SETZ
SETNCNZ
SETNCZ
SETCNZ
SETCZ

I like these too.

cgracey · 2017-04-30 06:27

I think this concern about bit-level logic operations is maybe not as big as we think. I was diagramming out all the possibilities, trying to figure out the number of possible permutations and determine how much opcode space it would require when I started thinking about what we can already do with the current instructions.

Look here:

'
'
' Checking for all high bits
' e := a & b & c & d
'
	TESTB	rega,#bita	WC
IF_C	TESTB	regb,#bitb	WC
IF_C	TESTB	regc,#bitc	WC
IF_C	TESTB	regd,#bitd	WC
	BITC	rege,#bite
'
'
' AND'ing bits
' b &= a
'
	TESTB	rega,#bita	WC
IF_NC	BITL	regb,#bitb
'
'
' OR'ing bits
' b |= a
'
	TESTB	rega,#bita	WC
IF_C	BITH	regb,#bitb
'
'
' XOR'ing bits
' a ^ b
'
		TESTB	rega,#bita	WC
		TESTB	regb,#bitb	WZ
IF_C_EQ_Z	XOR_IS_1

Not only can we already do logical operations on bits, but we have some nice things about our current bit instructions, like how they can set a new value and return what the bit was, before the operation, into C or Z.

The only weakness I'm perceiving is C and Z being easy recipients of state. ANDs and ORs are easy using conditionals, but XOR is a pain.

cgracey · 2017-04-30 06:32

I've tried to figure out what a complete and practical bit-logic instruction set would look like:

b = register bit (reg,#bit)
c = c flag
z = z flag


All operations:

MOVBIT	b,	c/!c/z/!z
	c,	b/!b/z/!z
	z,	b/!b/c/!c

ANDBIT	b,	c/!c/z/!z
	c,	b/!b/z/!z
	z,	b/!b/c/!c

ORBIT	b,	c/!c/z/!z
	c,	b/!b/z/!z
	z,	b/!b/c/!c

XORBIT	b,	c/!c/z/!z
	c,	b/!b/z/!z
	z,	b/!b/c/!c

NOTBIT	b/c/z

CLRBIT	b/c/z

SETBIT	b/c/z


Bit operations (need a range of 'D,#/S' inst's):

MOVBIT	b,	c/!c/z/!z
	c,	b/!b
	z,	b/!b

ANDBIT	b,	c/!c/z/!z
	c,	b/!b
	z,	b/!b

ORBIT	b,	c/!c/z/!z
	c,	b/!b
	z,	b/!b

XORBIT	b,	c/!c/z/!z
	c,	b/!b
	z,	b/!b

NOTBIT	b

CLRBIT	b

SETBIT	b


Non-bit operations (need a single '#D' inst):

MOVBIT	c,	z/!z
	z,	c/!c

ANDBIT	c,	z/!z
	z,	c/!c

ORBIT	c,	z/!z
	z,	c/!c

XORBIT	c,	z/!z
	z,	c/!c

NOTBIT	c/z

CLRBIT	c/z

SETBIT	c/z

The last group is just one single '#D' instruction and it could affect C and Z simultaneously.

It's that middle group that needs a block of 'D,S/#' instructions that puts pressure on the encoding map. Actually, MOVBIT, ANDBIT, ORBIT, and XORBIT would fit into the current space. Only NOTBIT, CLRBIT, and SETBIT would need to have some room made.

Sprucing up the bit instructions would be really nice, but it would break convention, somewhat, as flag writing would become fixed per instruction, since those C/Z bits would be needed to encode the instruction.

I know some of you might be thinking this is madness, but it's probably not even a whole day's work to accomplish. What would you think about this?

jmg · 2017-04-30 06:44

The above is not bad for bit := Bit Operator bit, but not so good for C,Z targets...

cgracey wrote: »

The only weakness I'm perceiving is C and Z being easy recipients of state.

Yes, (ideally) that needs to be improved.

cgracey wrote: »

ANDs and ORs are easy using conditionals, but XOR is a pain.

XOR can also be thought of as a conditional complement, (if one bit is hi, flip the result), you mentioned already adding NOTC ? There is already a BITN for Bit-Flip.

ozpropdev · 2017-04-30 06:49

MOVBIT	c,	z/!z

I like this one in particular, currently I have to do this.

	bitz	$+2,#10
	nop		'pipeline spacer
	setcz	#0 wc

cgracey · 2017-04-30 06:56

This change would allow for very simple bit-logic coding.

In the example below, I reduced the 'BIT' to 'B' in the mnemonics, since it's easier on the eyes. C and Z would become reserved words in PASM, or we could use 'CF' and 'ZF'. These look better, I think:

	movb	c,rega,#bita
	xorb	c,regb,#bitb
	andb	regc,#bitc,c

	movb	z,regd,#bitd
	orb	z,rege,#bite

	xorb	c,z
	andb	c,regf,#bitf

if_c	jmp	#Oh_No

We could have a constant type which would form a composite bit address, with both the register and the bit number. That would really clean up the code.

jmg · 2017-04-30 07:00

cgracey wrote: »
I've tried to figure out what a complete and practical bit-logic instruction set would look like:
b = register bit (reg,#bit)
c = c flag
z = z flag


All operations:

MOVBIT	b,	c/!c/z/!z
	c,	b/!b/z/!z
	z,	b/!b/c/!c

ANDBIT	b,	c/!c/z/!z
	c,	b/!b/z/!z
	z,	b/!b/c/!c

ORBIT	b,	c/!c/z/!z
	c,	b/!b/z/!z
	z,	b/!b/c/!c

XORBIT	b,	c/!c/z/!z
	c,	b/!b/z/!z
	z,	b/!b/c/!c

NOTBIT	b/c/z

CLRBIT	b/c/z

SETBIT	b/c/z


Bit operations (need a range of 'D,#/S' inst's):

MOVBIT	b,	c/!c/z/!z
	c,	b/!b
	z,	b/!b

ANDBIT	b,	c/!c/z/!z
	c,	b/!b
	z,	b/!b

ORBIT	b,	c/!c/z/!z
	c,	b/!b
	z,	b/!b

XORBIT	b,	c/!c/z/!z
	c,	b/!b
	z,	b/!b

NOTBIT	b

CLRBIT	b

SETBIT	b


Non-bit operations (need a single '#D' inst):

MOVBIT	c,	z/!z
	z,	c/!c

ANDBIT	c,	z/!z
	z,	c/!c

ORBIT	c,	z/!z
	z,	c/!c

XORBIT	c,	z/!z
	z,	c/!c

NOTBIT	c/z

CLRBIT	c/z

SETBIT	c/z
The last group is just one single '#D' instruction and it could affect C and Z simultaneously.

It's that middle group that needs a block of 'D,S/#' instructions that puts pressure on the encoding map. Actually, MOVBIT, ANDBIT, ORBIT, and XORBIT would fit into the current space. Only NOTBIT, CLRBIT, and SETBIT would need to have some room made.

I know some of you might be thinking this is madness, but it's probably not even a whole day's work to accomplish. What would you think about this?

Looking very nice

Given how tight COG memory is, being able to use true boolean vars and compress expressions, is going to be a large long term gain.
The above table is VERY comprehensive, well ahead of any other controller, and nicely sets the P2 up for PLC work.

cgracey wrote: »

Sprucing up the bit instructions would be really nice, but it would break convention, somewhat, as flag writing would become fixed per instruction, since those C/Z bits would be needed to encode the instruction.

To me that's quite ok, as in most of these opcodes, the C,Z are clearly stated, and would not be sensibly tacked on as suffix anyway.

jmg · 2017-04-30 07:13

cgracey wrote: »
This change would allow for very simple bit-logic coding.

In the example below, I reduced the 'BIT' to 'B' in the mnemonics, since it's easier on the eye's. C and Z would become reserved words in PASM, or we could use 'CF' and 'ZF'. These look better, I think:
	movb	c,rega,#bita
	xorb	c,regb,#bitb
	andb	regc,#bitc,c

	movb	z,regd,#bitd
	orb	z,rege,#bite

	xorb	c,z
	andb	c,regf,#bitf

if_c	jmp	#Oh_No
We could have a constant type which would form a composite bit address, with both the register and the bit number. That would really clean up the code.

That all looks great

The composite bit address, can also include PINS, allowing any mix of Named Physical Pins, and Named internal boolean vars, (aka virtual pins...)
It also removes the double commas, to make things even easier on the eyes.

BITs as targets for AND/OR are nice, but if the logic cost is high, just having C,Z as and.or.xor targets is tolerable.

cgracey · 2017-04-30 07:20

Eh, eh!!!! It turns out that there is more than enough room for these instructions, since the four biggies can use the current BITxx space and they'll obviate the current TESTB instruction, which we can fit NOTBIT/CLRBIT/SETBIT into and still have another slot.

I wish I didn't need to sleep, because I could have these instructions all done in the next two or three hours. I'll have to wait for Monday morning now. In the last 36 hours, I've only gotten two hours of sleep. I feel good, but don't want to push my luck too hard. I love this plant-based diet I've been on, as it's really clean and I feel like a kid again. I'm down 35 lbs and its a huge difference. I think eating right is the key to not croaking too soon, way more important than exercise, actually. I wish sleep wasn't necessary.

jmg · 2017-04-30 07:27

cgracey wrote: »

Eh, eh!!!! It turns out that there is more than enough room for these instructions, since the four biggies can use the current BITxx space and they'll obviate the current TESTB instruction, which we can fit NOTBIT/CLRBIT/SETBIT into and still have another slot.

Sounds good.

cgracey wrote: »

I wish I didn't need to sleep, because I could have these instructions all done in the next two or three hours. I'll have to wait for Monday morning now. In the last 36 hours, I've only gotten two hours of sleep...

Hmmm, now that does not sound good. Get some sleep!!!.

idbruce · 2017-04-30 09:43

Chip

In the last 36 hours, I've only gotten two hours of sleep.

That is not good for a healthy man, not to mention one who just got out of the hospital. As much as I want to see the P2, it won't do anyone any good if you have more health problems. You must set aside time to rest on a regular basis

Cluso99 · 2017-04-30 13:04

Chip,
YOU ABSOLUTELY MUST GET REGULAR REST !!!

You have been given the wake up call. Make sure you heed the warning please. P2 needs you to be well. Your no good to us, or more importantly your family, if your laid up in hospital, or worse still, 6 foot under.

Take Care,
Ray

Cluso99 · 2017-04-30 13:08

I had a response partially written for RCZL and RCZR. With all these extras I need to digest them to see whether there is any impact.

It's late here in Oz and I need my beauty sleep. Those wrinkles are showing and the grey hair is turning white

cgracey · 2017-04-30 21:44

Sorry to alarm you guys. Sleeping is hard for me sometimes when I'm excited about things. I wound up sleeping for 9 hours last night, since I was quite tired. I feel pretty good these days. The plant-based diet makes such a huge difference in how I feel. I've been walking 4 miles each day, which also helps. The diet is key, though. I feel like I'm going to live a very long life now.

potatohead · 2017-04-30 22:08

I'm on walks now too. Hard winter for me. Those do wonders.

Good news Chip! Diet... Yeah, gonna have to work on that.

Cluso99 · 2017-04-30 22:53

cgracey wrote: »

Sorry to alarm you guys. Sleeping is hard for me sometimes when I'm excited about things. I wound up sleeping for 9 hours last night, since I was quite tired. I feel pretty good these days. The plant-based diet makes such a huge difference in how I feel. I've been walking 4 miles each day, which also helps. The diet is key, though. I feel like I'm going to live a very long life now.

While diet is certainly a major key, the body requires sleep to replenish everything too!
It was not designed for 36 hour stints. It needs 7-9 hours sleep in every 24 hours. I have done those 36+ hour stints in the past too. But I cannot do this anymore, and I feel it has taken its toll along the way. And I haven't received the same warning as you, although I did get other warnings and suffer mildly as a result. Take it from a 65 yo, slow down now.

At least you seem to have found a good diet, you take time out for walks. You also need to spend time with your family, especially watching the kids as they grow up. I missed some of that due to my working hours, but at least I mostly worked from home so I at least ate dinner with them and we had sailing or snow skiing most weekends. I see what I missed as we watch our grandkids grow up.

Which leads to another point.

Ain't the internet grand. Our daughter, husband and 3yo twin boys now live in London (previously S Korea). We chat to them by FaceTime (Skype video equiv on iPad/iPhone) most evenings, often for an hour. We feel like we know these grandkids better that the two who only live a few blocks away, and I pick them up from school at least once a week!
FaceTime is so good that on their last visit (we had been with them 6 months previously) they came running to me saying grandpa. BTW off there for a month next week

cgracey · 2017-05-01 17:45

Cluso99 wrote: »

show previous quotes

cgracey wrote: »

Sorry to alarm you guys. Sleeping is hard for me sometimes when I'm excited about things. I wound up sleeping for 9 hours last night, since I was quite tired. I feel pretty good these days. The plant-based diet makes such a huge difference in how I feel. I've been walking 4 miles each day, which also helps. The diet is key, though. I feel like I'm going to live a very long life now.

While diet is certainly a major key, the body requires sleep to replenish everything too!
It was not designed for 36 hour stints. It needs 7-9 hours sleep in every 24 hours. I have done those 36+ hour stints in the past too. But I cannot do this anymore, and I feel it has taken its toll along the way. And I haven't received the same warning as you, although I did get other warnings and suffer mildly as a result. Take it from a 65 yo, slow down now.

At least you seem to have found a good diet, you take time out for walks. You also need to spend time with your family, especially watching the kids as they grow up. I missed some of that due to my working hours, but at least I mostly worked from home so I at least ate dinner with them and we had sailing or snow skiing most weekends. I see what I missed as we watch our grandkids grow up.

Which leads to another point.

Ain't the internet grand. Our daughter, husband and 3yo twin boys now live in London (previously S Korea). We chat to them by FaceTime (Skype video equiv on iPad/iPhone) most evenings, often for an hour. We feel like we know these grandkids better that the two who only live a few blocks away, and I pick them up from school at least once a week!
FaceTime is so good that on their last visit (we had been with them 6 months previously) they came running to me saying grandpa. BTW off there for a month next week

I agree with everything you've said. Having a family means there's a lot more to handle than just work. That's why I've been stretching my awake time.

cgracey · 2017-05-01 17:56

To implement the bit-logic instructions, this block of instructions:

EEEE 0100000 CZI DDDDDDDDD SSSSSSSSS        BITL    D,S/#       {WC,WZ}
EEEE 0100001 CZI DDDDDDDDD SSSSSSSSS        BITH    D,S/#       {WC,WZ}
EEEE 0100010 CZI DDDDDDDDD SSSSSSSSS        BITC    D,S/#       {WC,WZ}
EEEE 0100011 CZI DDDDDDDDD SSSSSSSSS        BITNC   D,S/#       {WC,WZ}
EEEE 0100100 CZI DDDDDDDDD SSSSSSSSS        BITZ    D,S/#       {WC,WZ}
EEEE 0100101 CZI DDDDDDDDD SSSSSSSSS        BITNZ   D,S/#       {WC,WZ}
EEEE 0100110 CZI DDDDDDDDD SSSSSSSSS        BITN    D,S/#       {WC,WZ}
EEEE 0100111 CZI DDDDDDDDD SSSSSSSSS        BITX    D,S/#       {WC,WZ}

EEEE 0101000 CZI DDDDDDDDD SSSSSSSSS        ANDN    D,S/#       {WC,WZ}
EEEE 0101001 CZI DDDDDDDDD SSSSSSSSS        AND     D,S/#       {WC,WZ}
EEEE 0101010 CZI DDDDDDDDD SSSSSSSSS        OR      D,S/#       {WC,WZ}
EEEE 0101011 CZI DDDDDDDDD SSSSSSSSS        XOR     D,S/#       {WC,WZ}

EEEE 0101100 CZI DDDDDDDDD SSSSSSSSS        MUXC    D,S/#       {WC,WZ}
EEEE 0101101 CZI DDDDDDDDD SSSSSSSSS        MUXNC   D,S/#       {WC,WZ}
EEEE 0101110 CZI DDDDDDDDD SSSSSSSSS        MUXZ    D,S/#       {WC,WZ}
EEEE 0101111 CZI DDDDDDDDD SSSSSSSSS        MUXNZ   D,S/#       {WC,WZ}

EEEE 0110000 CZI DDDDDDDDD SSSSSSSSS        MOV     D,S/#       {WC,WZ}
EEEE 0110001 CZI DDDDDDDDD SSSSSSSSS        NOT     D,S/#       {WC,WZ}
EEEE 0110010 CZI DDDDDDDDD SSSSSSSSS        ABS     D,S/#       {WC,WZ}
EEEE 0110011 CZI DDDDDDDDD SSSSSSSSS        NEG     D,S/#       {WC,WZ}

EEEE 0110100 CZI DDDDDDDDD SSSSSSSSS        NEGC    D,S/#       {WC,WZ}
EEEE 0110101 CZI DDDDDDDDD SSSSSSSSS        NEGNC   D,S/#       {WC,WZ}
EEEE 0110110 CZI DDDDDDDDD SSSSSSSSS        NEGZ    D,S/#       {WC,WZ}
EEEE 0110111 CZI DDDDDDDDD SSSSSSSSS        NEGNZ   D,S/#       {WC,WZ}

EEEE 0111000 CZI DDDDDDDDD SSSSSSSSS        INCMOD  D,S/#       {WC,WZ}
EEEE 0111001 CZI DDDDDDDDD SSSSSSSSS        DECMOD  D,S/#       {WC,WZ}
EEEE 0111010 CZI DDDDDDDDD SSSSSSSSS        TOPONE  D,S/#       {WC,WZ}
EEEE 0111011 CZI DDDDDDDDD SSSSSSSSS        BOTONE  D,S/#       {WC,WZ}

EEEE 0111100 CZI DDDDDDDDD SSSSSSSSS        TESTN   D,S/#       {WC,WZ}
EEEE 0111101 CZI DDDDDDDDD SSSSSSSSS        TEST    D,S/#       {WC,WZ}
EEEE 0111110 CZI DDDDDDDDD SSSSSSSSS        ANYB    D,S/#       {WC,WZ}
EEEE 0111111 CZI DDDDDDDDD SSSSSSSSS        TESTB   D,S/#       {WC,WZ}

Is going to change into this:

CCCC 0100000 CZI DDDDDDDDD SSSSSSSSS        MOV     D,S/#       {WC,WZ}
CCCC 0100001 CZI DDDDDDDDD SSSSSSSSS        NOT     D,S/#       {WC,WZ}
CCCC 0100010 CZI DDDDDDDDD SSSSSSSSS        ABS     D,S/#       {WC,WZ}
CCCC 0100011 CZI DDDDDDDDD SSSSSSSSS        NEG     D,S/#       {WC,WZ}

CCCC 0100100 CZI DDDDDDDDD SSSSSSSSS        NEGC    D,S/#       {WC,WZ}
CCCC 0100101 CZI DDDDDDDDD SSSSSSSSS        NEGNC   D,S/#       {WC,WZ}
CCCC 0100110 CZI DDDDDDDDD SSSSSSSSS        NEGZ    D,S/#       {WC,WZ}
CCCC 0100111 CZI DDDDDDDDD SSSSSSSSS        NEGNZ   D,S/#       {WC,WZ}

CCCC 0101000 CZI DDDDDDDDD SSSSSSSSS        INCMOD  D,S/#       {WC,WZ}
CCCC 0101001 CZI DDDDDDDDD SSSSSSSSS        DECMOD  D,S/#       {WC,WZ}
CCCC 0101010 CZI DDDDDDDDD SSSSSSSSS        TOPONE  D,S/#       {WC,WZ}
CCCC 0101011 CZI DDDDDDDDD SSSSSSSSS        BOTONE  D,S/#       {WC,WZ}

CCCC 0101100 CZI DDDDDDDDD SSSSSSSSS        TESTN   D,S/#       {WC,WZ}
CCCC 0101101 CZI DDDDDDDDD SSSSSSSSS        TEST    D,S/#       {WC,WZ}
CCCC 0101110 CZI DDDDDDDDD SSSSSSSSS        ANYB    D,S/#       {WC,WZ}
CCCC 0101111 CZI DDDDDDDDD SSSSSSSSS        <empty> D,S/#       {WC,WZ}

CCCC 0110000 CZI DDDDDDDDD SSSSSSSSS        ANDN    D,{#}S      {WC,WZ}
CCCC 0110001 CZI DDDDDDDDD SSSSSSSSS        AND     D,{#}S      {WC,WZ}
CCCC 0110010 CZI DDDDDDDDD SSSSSSSSS        OR      D,{#}S      {WC,WZ}
CCCC 0110011 CZI DDDDDDDDD SSSSSSSSS        XOR     D,{#}S      {WC,WZ}

CCCC 0110100 00I DDDDDDDDD SSSSSSSSS        MUXC    D,{#}S
CCCC 0110100 01I DDDDDDDDD SSSSSSSSS        MUXNC   D,{#}S
CCCC 0110100 10I DDDDDDDDD SSSSSSSSS        MUXZ    D,{#}S
CCCC 0110100 11I DDDDDDDDD SSSSSSSSS        MUXNZ   D,{#}S

CCCC 0110101 00I DDDDDDDDD SSSSSSSSS        MASKC   D,{#}S
CCCC 0110101 01I DDDDDDDDD SSSSSSSSS        MASKNC  D,{#}S
CCCC 0110101 10I DDDDDDDDD SSSSSSSSS        MASKZ   D,{#}S
CCCC 0110101 11I DDDDDDDDD SSSSSSSSS        MASKNZ  D,{#}S

CCCC 0110110 C0I DDDDDDDDD SSSSSSSSS        CLRB    D\{#}S      {WC}
CCCC 0110110 C1I DDDDDDDDD SSSSSSSSS        SETB    D\{#}S      {WC}
CCCC 0110111 C0I DDDDDDDDD SSSSSSSSS        NOTB    D\{#}S      {WC}
CCCC 0110111 C1I DDDDDDDDD SSSSSSSSS        RNDB    D\{#}S      {WC}

CCCC 0111000 00I DDDDDDDDD SSSSSSSSS        MOVB    D\{#}S, CF
CCCC 0111000 01I DDDDDDDDD SSSSSSSSS        MOVB    D\{#}S,!CF
CCCC 0111000 10I DDDDDDDDD SSSSSSSSS        MOVB    D\{#}S, ZF
CCCC 0111000 11I DDDDDDDDD SSSSSSSSS        MOVB    D\{#}S,!ZF
CCCC 0111001 00I DDDDDDDDD SSSSSSSSS        MOVB    CF, D\{#}S
CCCC 0111001 01I DDDDDDDDD SSSSSSSSS        MOVB    CF,!D\{#}S
CCCC 0111001 10I DDDDDDDDD SSSSSSSSS        MOVB    ZF, D\{#}S
CCCC 0111001 11I DDDDDDDDD SSSSSSSSS        MOVB    ZF,!D\{#}S

CCCC 0111010 00I DDDDDDDDD SSSSSSSSS        ANDB    D\{#}S, CF
CCCC 0111010 01I DDDDDDDDD SSSSSSSSS        ANDB    D\{#}S,!CF
CCCC 0111010 10I DDDDDDDDD SSSSSSSSS        ANDB    D\{#}S, ZF
CCCC 0111010 11I DDDDDDDDD SSSSSSSSS        ANDB    D\{#}S,!ZF
CCCC 0111011 00I DDDDDDDDD SSSSSSSSS        ANDB    CF, D\{#}S
CCCC 0111011 01I DDDDDDDDD SSSSSSSSS        ANDB    CF,!D\{#}S
CCCC 0111011 10I DDDDDDDDD SSSSSSSSS        ANDB    ZF, D\{#}S
CCCC 0111011 11I DDDDDDDDD SSSSSSSSS        ANDB    ZF,!D\{#}S

CCCC 0111100 00I DDDDDDDDD SSSSSSSSS        ORB     D\{#}S, CF
CCCC 0111100 01I DDDDDDDDD SSSSSSSSS        ORB     D\{#}S,!CF
CCCC 0111100 10I DDDDDDDDD SSSSSSSSS        ORB     D\{#}S, ZF
CCCC 0111100 11I DDDDDDDDD SSSSSSSSS        ORB     D\{#}S,!ZF
CCCC 0111101 00I DDDDDDDDD SSSSSSSSS        ORB     CF, D\{#}S
CCCC 0111101 01I DDDDDDDDD SSSSSSSSS        ORB     CF,!D\{#}S
CCCC 0111101 10I DDDDDDDDD SSSSSSSSS        ORB     ZF, D\{#}S
CCCC 0111101 11I DDDDDDDDD SSSSSSSSS        ORB     ZF,!D\{#}S

CCCC 0111110 00I DDDDDDDDD SSSSSSSSS        XORB    D\{#}S, CF
CCCC 0111110 01I DDDDDDDDD SSSSSSSSS        XORB    D\{#}S,!CF
CCCC 0111110 10I DDDDDDDDD SSSSSSSSS        XORB    D\{#}S, ZF
CCCC 0111110 11I DDDDDDDDD SSSSSSSSS        XORB    D\{#}S,!ZF
CCCC 0111111 00I DDDDDDDDD SSSSSSSSS        XORB    CF, D\{#}S
CCCC 0111111 01I DDDDDDDDD SSSSSSSSS        XORB    CF,!D\{#}S
CCCC 0111111 10I DDDDDDDDD SSSSSSSSS        XORB    ZF, D\{#}S
CCCC 0111111 11I DDDDDDDDD SSSSSSSSS        XORB    ZF,!D\{#}S

I figured we could use "\" to separate the register and bit number for bit addresses. This allows a comma to separate the flag operand.

Using "C" and "Z" would preempt common variable names, so I figured "CF" and "ZF" would be better. For MOVB/ANDB/ORB/XORB, the assembler would have to check for a "!" first in the 2nd operand, before letting the expression resolver do its work, since "!" is also a unary operator.

To preserve the convenience of the old bit-modifying instructions, where a C/!Z can receive the bit's prior state, CLRB/SETB/NOTB/RNDB can be used with WC to write the original bit state into C.

These new instructions take about the same number of gates as the old ones did.

TonyB · 2017-05-01 18:55

Some of those instructions looks overcomplicated to me.

potatohead · 2017-05-01 19:04

Using "C" and "Z" would preempt common variable names, so I figured "CF" and "ZF" would be better.

Thank you. Agreed.

cgracey · 2017-05-01 19:16

I forgot to mention that there are other intra-flag operations like:

XORB    CF,!ZF
ANDB    ZF,CF
NOTB    CF

With the more elaborate operand syntax, all you have to remember, mnemonic-wise, is:

MOVB
ANDB
ORB
XORB
CLRB
SETB
NOTB
RNDB

Then your destination operands are:

D\{#}S
CF
ZF

And your source operands are:

D\{#}S
!D\{#}S
CF
!CF
ZF
!ZF

jmg · 2017-05-01 19:26

cgracey wrote: »
I forgot to mention that there other intra-flag operations like:
XORB    CF,!ZF
ANDB    ZF,CF
NOTB    CF
With the more elaborate operand syntax, all you have to remember, mnemonic-wise, is:
MOVB
ANDB
ORB
XORB
CLRB
SETB
NOTB
RNDB
Then your destination operands are:
D\{#}S
CF
ZF
And your source operands are:
D\{#}S
!D\{#}S
CF
!CF
ZF
!ZF

Yes, this form is great

B suffix clearly signals a Boolean Address and Boolean operator.

jmg · 2017-05-01 19:31

TonyB wrote: »

Some of those instructions looks overcomplicated to me. How about:

Err, no...
The B suffix operators are ALL BOOLEAN ones, that take a BIT variable
CF and ZF are simply reserved special case boolean locations.

Far from being 'overcomplicated', this is actually a very simple subgroup.

ADDC on the other hand, ADDs a 32b operand with carry, and includes the carry flag in the operator.
ie Very different, and it would be confusing to try to merge the two semantics.

This will all be clearer when Chip adds the operation equations to the mnemonics.

SFUNC question

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