I think I can save 8 instructions
in Propeller 2
All instructions same length and same execution time as now.
Would anyone like more info?
Would anyone like more info?
Comments
Does 'save 8 instructions' mean the opcode map reduces, or opcodes get more efficient, or ?
Is the any logic-cost downside to this 'save 8 instructions' ?
1 bit of encoding would change in 16 existing instructions.
Probably 8 new instruction proposals...
Okay, so how do we get 8 more instructions?
0000 0000000 000 000000000 000000000 NOP EEEE 0000001 CZI DDDDDDDDD SSSSSSSSS ? EEEE 0000010 CZI DDDDDDDDD SSSSSSSSS ? EEEE 0000011 CZI DDDDDDDDD SSSSSSSSS ? EEEE 0000100 CZI DDDDDDDDD SSSSSSSSS ? EEEE 0000101 CZI DDDDDDDDD SSSSSSSSS ? EEEE 0000110 CZI DDDDDDDDD SSSSSSSSS ? EEEE 0000111 CZI DDDDDDDDD SSSSSSSSS ? EEEE 0100000 CZ0 DDDDDDDDD SSSSSSSSS ROR D,S EEEE 0100000 CZ1 DDDDDDDDD SSSSSSSSS ROL D,S EEEE 0100001 CZ0 DDDDDDDDD SSSSSSSSS SHR D,S EEEE 0100001 CZ1 DDDDDDDDD SSSSSSSSS SHL D,S EEEE 0100010 CZ0 DDDDDDDDD SSSSSSSSS RCR D,S EEEE 0100010 CZ1 DDDDDDDDD SSSSSSSSS RCL D,S EEEE 0100011 CZ0 DDDDDDDDD SSSSSSSSS SAR D,S EEEE 0100011 CZ1 DDDDDDDDD SSSSSSSSS SAL D,S EEEE 0100100 CZ0 DDDDDDDDD SSSSSSSSS BITL D,S EEEE 0100100 CZ1 DDDDDDDDD SSSSSSSSS BITH D,S EEEE 0100101 CZ0 DDDDDDDDD SSSSSSSSS BITC D,S EEEE 0100101 CZ1 DDDDDDDDD SSSSSSSSS BITNC D,S EEEE 0100110 CZ0 DDDDDDDDD SSSSSSSSS BITZ D,S EEEE 0100110 CZ1 DDDDDDDDD SSSSSSSSS BITNZ D,S EEEE 0100111 CZ0 DDDDDDDDD SSSSSSSSS BITN D,S EEEE 0100111 CZ1 DDDDDDDDD SSSSSSSSS BITX D,S EEEE 1101011 CZ0 DDDDDDDDD 1000SSSSS ROR D,#S EEEE 1101011 CZ1 DDDDDDDDD 1000SSSSS ROL D,#S EEEE 1101011 CZ0 DDDDDDDDD 1001SSSSS SHR D,#S EEEE 1101011 CZ1 DDDDDDDDD 1001SSSSS SHL D,#S EEEE 1101011 CZ0 DDDDDDDDD 1010SSSSS RCR D,#S EEEE 1101011 CZ1 DDDDDDDDD 1010SSSSS RCL D,#S EEEE 1101011 CZ0 DDDDDDDDD 1011SSSSS SAR D,#S EEEE 1101011 CZ1 DDDDDDDDD 1011SSSSS SAL D,#S EEEE 1101011 CZ0 DDDDDDDDD 1100SSSSS BITL D,#S EEEE 1101011 CZ1 DDDDDDDDD 1100SSSSS BITH D,#S EEEE 1101011 CZ0 DDDDDDDDD 1101SSSSS BITC D,#S EEEE 1101011 CZ1 DDDDDDDDD 1101SSSSS BITNC D,#S EEEE 1101011 CZ0 DDDDDDDDD 1110SSSSS BITZ D,#S EEEE 1101011 CZ1 DDDDDDDDD 1110SSSSS BITNZ D,#S EEEE 1101011 CZ0 DDDDDDDDD 1111SSSSS BITN D,#S EEEE 1101011 CZ1 DDDDDDDDD 1111SSSSS BITX D,#S
That breaks things a lot.
Split encoding but 8 new instructions gained.
Low complexity there matters.
When the V9 FPGA image was released with smartpins my nice little Parallax P123-A9 board (with its huge Cyclone V FPGA) had all 64 smartpins available.
Now at V18a I have 14!
A bit scary....
That would free up a lot of space, all right. It really wouldn't be that much to make such a change, but the bigger problem is that we probably don't have the logic budget to make good use of all that space. We are pretty heavy on logic, as it is. At this point, less disruption is probably best. This line of thinking is important for the future, though.
a) run as fast as, or faster than, the current one ?
b) have no more logic consumed?
It is not a bad idea to have reserved opcode space, even if on this version, no logic is attached.
Other MCUs have done that, and then future versions can keep binary compatible, but super-set.
Personally, I'm feeling good about the tweaks to get SPIN, C and language performance support in there.
It's a win, designing together like that. I feel we will have a no B.S. SPIN, lean, mean, fast. C and friends lining up the same way. Worth it.
I suppose there is always another niche seriously improved by an instruction. But, we do have 16 COGS, and all of those are x16 cost per logic unit too.
Because of that, it's really hard to say worth it outside that scope now.
And none of that is about the ideas. It's about moving to actualize this thing. We need to.
We all probably have a list of niche instructions we would like but at last count we have 320+ instructions.
I'm excited about the new SPIN tweaks but have fingers crossed that FPGA image V19 is the FINAL release.
This change would add logic to the instruction decoding, but not that much. It probably wouldn't impact Fmax timing.
I don't want to do it, though, because it adds another ripple into the architecture and will make the tools more complex, given where they probably are, due to the long-standing 9-bit S field.
Yes, this is a sobering "creepage metric" from ozpropdev ....
I wonder what the final RAM allowance will be ? 512k was looking limiting, what about 128k