Shop OBEX P1 Docs P2 Docs Learn Events
I think I can save 8 instructions — Parallax Forums

I think I can save 8 instructions

TonyBTonyB Posts: 73
in Propeller 2
All instructions same length and same execution time as now.
Would anyone like more info?
«1

Comments

  • jmgjmg Posts: 15,173
    A bit cryptic.
    Does 'save 8 instructions' mean the opcode map reduces, or opcodes get more efficient, or ?
    Is the any logic-cost downside to this 'save 8 instructions' ?
  • TonyBTonyB Posts: 73
    8 opcodes would be freed up for 8 new instructions.
    1 bit of encoding would change in 16 existing instructions.
  • TonyBTonyB Posts: 73
    edited 2017-04-29 00:20
    Or 7 new instructions and a real NOP!


  • potatoheadpotatohead Posts: 10,261
    the any logic-cost downside to this 'save 8 instructions' ?

    Probably 8 new instruction proposals...

    :/
  • cgraceycgracey Posts: 14,152
    I'm just going through the SFUNC instructions, trying to figure out the best way to move them to the D-only instructions.

    Okay, so how do we get 8 more instructions?
  • ozpropdevozpropdev Posts: 2,792
    We have a real NOP encoded as 0.
  • TonyBTonyB Posts: 73
    edited 2017-04-29 22:49 
    0000 0000000 000 000000000 000000000	NOP
EEEE 0000001 CZI DDDDDDDDD SSSSSSSSS	?
EEEE 0000010 CZI DDDDDDDDD SSSSSSSSS	?
EEEE 0000011 CZI DDDDDDDDD SSSSSSSSS	?
EEEE 0000100 CZI DDDDDDDDD SSSSSSSSS	?
EEEE 0000101 CZI DDDDDDDDD SSSSSSSSS	?
EEEE 0000110 CZI DDDDDDDDD SSSSSSSSS	?
EEEE 0000111 CZI DDDDDDDDD SSSSSSSSS	?

EEEE 0100000 CZ0 DDDDDDDDD SSSSSSSSS	ROR D,S
EEEE 0100000 CZ1 DDDDDDDDD SSSSSSSSS	ROL D,S
EEEE 0100001 CZ0 DDDDDDDDD SSSSSSSSS	SHR D,S
EEEE 0100001 CZ1 DDDDDDDDD SSSSSSSSS	SHL D,S
EEEE 0100010 CZ0 DDDDDDDDD SSSSSSSSS	RCR D,S
EEEE 0100010 CZ1 DDDDDDDDD SSSSSSSSS	RCL D,S
EEEE 0100011 CZ0 DDDDDDDDD SSSSSSSSS	SAR D,S
EEEE 0100011 CZ1 DDDDDDDDD SSSSSSSSS	SAL D,S
EEEE 0100100 CZ0 DDDDDDDDD SSSSSSSSS	BITL D,S
EEEE 0100100 CZ1 DDDDDDDDD SSSSSSSSS	BITH D,S
EEEE 0100101 CZ0 DDDDDDDDD SSSSSSSSS	BITC D,S
EEEE 0100101 CZ1 DDDDDDDDD SSSSSSSSS	BITNC D,S
EEEE 0100110 CZ0 DDDDDDDDD SSSSSSSSS	BITZ D,S
EEEE 0100110 CZ1 DDDDDDDDD SSSSSSSSS	BITNZ D,S
EEEE 0100111 CZ0 DDDDDDDDD SSSSSSSSS	BITN D,S
EEEE 0100111 CZ1 DDDDDDDDD SSSSSSSSS	BITX D,S

EEEE 1101011 CZ0 DDDDDDDDD 1000SSSSS	ROR D,#S
EEEE 1101011 CZ1 DDDDDDDDD 1000SSSSS	ROL D,#S
EEEE 1101011 CZ0 DDDDDDDDD 1001SSSSS	SHR D,#S
EEEE 1101011 CZ1 DDDDDDDDD 1001SSSSS	SHL D,#S
EEEE 1101011 CZ0 DDDDDDDDD 1010SSSSS	RCR D,#S
EEEE 1101011 CZ1 DDDDDDDDD 1010SSSSS	RCL D,#S
EEEE 1101011 CZ0 DDDDDDDDD 1011SSSSS	SAR D,#S
EEEE 1101011 CZ1 DDDDDDDDD 1011SSSSS	SAL D,#S
EEEE 1101011 CZ0 DDDDDDDDD 1100SSSSS	BITL D,#S
EEEE 1101011 CZ1 DDDDDDDDD 1100SSSSS	BITH D,#S
EEEE 1101011 CZ0 DDDDDDDDD 1101SSSSS	BITC D,#S
EEEE 1101011 CZ1 DDDDDDDDD 1101SSSSS	BITNC D,#S
EEEE 1101011 CZ0 DDDDDDDDD 1110SSSSS	BITZ D,#S
EEEE 1101011 CZ1 DDDDDDDDD 1110SSSSS	BITNZ D,#S
EEEE 1101011 CZ0 DDDDDDDDD 1111SSSSS	BITN D,#S
EEEE 1101011 CZ1 DDDDDDDDD 1111SSSSS	BITX D,#S
  • ozpropdevozpropdev Posts: 2,792
    edited 2017-04-29 00:22
    You have lost the immediate flag.
    That breaks things a lot.
  • potatoheadpotatohead Posts: 10,261
    Yeah, we need that.
  • ozpropdevozpropdev Posts: 2,792
    Having two encodings for the same instructions adds more logic (x 16 cogs) too.
  • TonyBTonyB Posts: 73
    Rotates, shifts and bits could go at the beginning.
    Split encoding but 8 new instructions gained.
  • TonyBTonyB Posts: 73
    edited 2017-04-29 18:54
    .
  • TonyBTonyB Posts: 73
    edited 2017-04-29 22:44
    .
  • ozpropdevozpropdev Posts: 2,792
    Having the immediate flag at two different locations breaks the architecture not to mentions would cause headaches in the assembler.
  • TonyBTonyB Posts: 73
    edited 2017-04-29 18:54
    .
  • potatoheadpotatohead Posts: 10,261
    We just streamlined instruction decode to improve timing too.

    Low complexity there matters.
  • Dave HeinDave Hein Posts: 6,347
    edited 2017-04-29 02:23
    TonyB, we're hoping to see a P2 in silicon sometime in the foreseeable future. The instruction set for the P2 is almost done, and it is somewhat reckless to suggest major changes at this point in the development. I see that you've joined the forum recently. I would suggest you scan through the last few years of posts on the P2 to get a perspective on what has been tried in the past, and how the P2 got to where it is today. You have some good suggestions, but it is very late in the game to make the changes you're suggesting. Where have you been the past 5 years? We could have used your suggestions back then.
  • David BetzDavid Betz Posts: 14,516
    Dave Hein wrote: »
    The instruction set for the P2 is almost done
    I've thought this several times and it has been announced several times. I guess what I failed to notice is the word "almost".
  • ozpropdevozpropdev Posts: 2,792
    Here's a statistic that might highlight the caution required in adding features to P2.

    When the V9 FPGA image was released with smartpins my nice little Parallax P123-A9 board (with its huge Cyclone V FPGA) had all 64 smartpins available.
    Now at V18a I have 14! :(
    A bit scary....
  • potatoheadpotatohead Posts: 10,261
    Ouch!

  • cgraceycgracey Posts: 14,152
    TonyB, those are great ideas! They have never occurred to me before. I wish they would have, earlier.

    That would free up a lot of space, all right. It really wouldn't be that much to make such a change, but the bigger problem is that we probably don't have the logic budget to make good use of all that space. We are pretty heavy on logic, as it is. At this point, less disruption is probably best. This line of thinking is important for the future, though.
  • jmgjmg Posts: 15,173
    cgracey wrote: »
    TonyB, those are great ideas! They have never occurred to me before. I wish they would have, earlier.

    That would free up a lot of space, all right. It really wouldn't be that much to make such a change, but the bigger problem is that we probably don't have the logic budget to make good use of all that space. We are pretty heavy on logic, as it is. At this point, less disruption is probably best. This line of thinking is important for the future, though.
    Would the changed opcode map
    a) run as fast as, or faster than, the current one ?
    b) have no more logic consumed?
    It is not a bad idea to have reserved opcode space, even if on this version, no logic is attached.
    Other MCUs have done that, and then future versions can keep binary compatible, but super-set.


  • fengfeng Posts: 39
    Brilliant!
  • potatoheadpotatohead Posts: 10,261
    edited 2017-04-29 06:10
    Remember, we still have synthesis to get past.

    Personally, I'm feeling good about the tweaks to get SPIN, C and language performance support in there.

    It's a win, designing together like that. I feel we will have a no B.S. SPIN, lean, mean, fast. C and friends lining up the same way. Worth it.

    I suppose there is always another niche seriously improved by an instruction. But, we do have 16 COGS, and all of those are x16 cost per logic unit too.

    Because of that, it's really hard to say worth it outside that scope now.

    And none of that is about the ideas. It's about moving to actualize this thing. We need to.



  • ozpropdevozpropdev Posts: 2,792
    potatohead wrote: »
    And none of that is about the ideas. It's about moving to actualize this thing. We need to.
    That's right, lots of good ideas here.
    We all probably have a list of niche instructions we would like but at last count we have 320+ instructions.

    I'm excited about the new SPIN tweaks but have fingers crossed that FPGA image V19 is the FINAL release. :)

  • cgraceycgracey Posts: 14,152
    jmg wrote: »
    cgracey wrote: »
    TonyB, those are great ideas! They have never occurred to me before. I wish they would have, earlier.

    That would free up a lot of space, all right. It really wouldn't be that much to make such a change, but the bigger problem is that we probably don't have the logic budget to make good use of all that space. We are pretty heavy on logic, as it is. At this point, less disruption is probably best. This line of thinking is important for the future, though.
    Would the changed opcode map
    a) run as fast as, or faster than, the current one ?
    b) have no more logic consumed?
    It is not a bad idea to have reserved opcode space, even if on this version, no logic is attached.
    Other MCUs have done that, and then future versions can keep binary compatible, but super-set.


    This change would add logic to the instruction decoding, but not that much. It probably wouldn't impact Fmax timing.

    I don't want to do it, though, because it adds another ripple into the architecture and will make the tools more complex, given where they probably are, due to the long-standing 9-bit S field.
  • kwinnkwinn Posts: 8,697
    Have to stop adding things at some point, otherwise we will be adding the straw that breaks the camels back.
  • David BetzDavid Betz Posts: 14,516
    kwinn wrote: »
    Have to stop adding things at some point, otherwise we will be adding the straw that breaks the camels back.
    Yes. It would be nice to get through synthesis to verify that this hasn't already happened.

  • TonyBTonyB Posts: 73
    edited 2017-04-29 22:37
    Four weeks ago I knew nothing about the P1 or P2. A friend sent me an email about his P1 project, I had a look at the datasheet, became fascinated and joined this forum two weeks ago. Late last night I had a brainwave that I thought was worth sharing. I don't really know what breaking the architecture means, the opcodes are just bits to me. I'm not asking you to change anything. I have a few more thoughts on the subject that I'll post soon.
  • jmgjmg Posts: 15,173
    David Betz wrote: »
    kwinn wrote: »
    Have to stop adding things at some point, otherwise we will be adding the straw that breaks the camels back.
    Yes. It would be nice to get through synthesis to verify that this hasn't already happened.

    Yes, this is a sobering "creepage metric" from ozpropdev ....
    ozpropdev wrote: »
    Here's a statistic that might highlight the caution required in adding features to P2.

    When the V9 FPGA image was released with smartpins my nice little Parallax P123-A9 board (with its huge Cyclone V FPGA) had all 64 smartpins available.
    Now at V18a I have 14! :(
    A bit scary....
    I wonder what the final RAM allowance will be ? 512k was looking limiting, what about 128k :( ?

Sign In or Register to comment.