Acknowledge polling with I2CIN/I2COUT on a 24LC32A
Zoot
Posts: 2,227
I'm using a 24LC32A 4K EE chip with my Stamp BS2p40 -- with great success.
My only sticking point has been timing while the 24LC32A writes multiple bytes. The chip stores incoming bytes in a buffer, and after the master issues a STOP, it writes the bytes, which takes time.
I got into trouble when trying to read from the chip too quickly after sending bytes for writing. My short term solution was to put a PAUSE 3 into my program after the write and before the read (anything less than PAUSE 3 and the chip doesn't have time to write bytes before the next read cycle).
Now, the literature for the chip says you can do acknowledge polling while waiting for a write cycle to finish, but I am not sure how to do this with I2COUT/I2CIN. Would I have to bit bang it?
Here's the relevant quote from page. 9 of the datasheet:
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When the going gets weird, the weird turn pro. -- HST
My only sticking point has been timing while the 24LC32A writes multiple bytes. The chip stores incoming bytes in a buffer, and after the master issues a STOP, it writes the bytes, which takes time.
I got into trouble when trying to read from the chip too quickly after sending bytes for writing. My short term solution was to put a PAUSE 3 into my program after the write and before the read (anything less than PAUSE 3 and the chip doesn't have time to write bytes before the next read cycle).
Now, the literature for the chip says you can do acknowledge polling while waiting for a write cycle to finish, but I am not sure how to do this with I2COUT/I2CIN. Would I have to bit bang it?
Here's the relevant quote from page. 9 of the datasheet:
Attached is the full datasheet. Thanks in advance.Somebody said...
5.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally-timed write cycle. ACK polling
can then be initiated immediately. This involves the
master sending a Start condition followed by the control
byte for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, the Start bit and control byte must
be re-sent. If the cycle is complete, the device will
return the ACK and the master can then proceed with
the next Read or Write command. See Figure 5-1 for
flow diagram of this operation.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
When the going gets weird, the weird turn pro. -- HST
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