Well, not quite; the conventional RF synthesizer approach is to divide-down the final output frequency, and then phaselock that result to a selectable reference. In our case here, the reference is good (other than probably needing to be a square wave to provide purity to the phase comparator), but we would like to be able to have the divide-down feature.
At present, a base frequency is generated, and that is cranked up by a selectable PLL ratio. For generationg (almost) any desired high frequency, this is backwards and leads to a large frequency granularity. Instead (or as well) we would like a VCO that can run at a high (as high as possible for "best coverage") RF frequency which then be divided down, and that result fed to the VCO's phase comparator.
I don't know, be I may be asking for too much here.
That said though, I still think an NCO should have a square wave output........
I can understand how this would always get you a square wave, but I still can't see the benefit for any kind of precise FM'ing. By having·programmable multipliers and dividers, you can hit close to many frequencies with a real square wave, but you must always do a multiplier-divisor search to find the optimal combo for any frequency, right? Doesn't this make FM'ing a 100MHz carrier by +/- 0-50KHz (in small steps)·quite unlikely? What the Propeller has now, while phase-noisy, does have simple, numerically linear control over average frequency of the NCO - from a programming standpoint this couldn't be much simpler. And with 32 bits, your frequency·granularity is sub-Hz, even with 16x VCO multiplication.·I think that if·the VCO's·charge-pump current was reduced, it might be way cleaner spectrum-wise. I used a multiply-divide type PLL before on the SX-Key and there was a ~0.1% limit on frequency accuracy with, I believe, 8 and 9 bits of multiplier and divisor resolutions. At 100MHz that would be ~100KHz steps - pretty rough, and not necessarily identical on either side of the 'center'.
Is it most important to you to be able to get NEAR what frequency you care about with a real square wave because you can live with big frequency steps in either direction?
What about this: Do you think you could play some variable loading game on the crystal pins to detune the master clock to get the gentle, but spectrally pure FM you're looking for at higher frequencies via the PLL? Maybe an I/O pin could be modulated to introduce some variable impeadance through·an RLC network into the XIN and/or XOUT pins. I've never attempted this, and I don't understand exactly HOW this should work, but I assume there must be a way to achieve this. I'm thinking you would program a power-of-2 value into the FRQ register and, like Tracy said, go for the master clock, instead, to keep things clean.
pjv said...
Hi Chip;
Well, not quite; the conventional RF synthesizer approach is to divide-down the final output frequency, and then phaselock that result to a selectable reference. In our case here, the reference is good (other than probably needing to be a square wave to provide purity to the phase comparator), but we would like to be able to have the divide-down feature.
At present, a base frequency is generated, and that is cranked up by a selectable PLL ratio. For generationg (almost) any desired high frequency, this is backwards and leads to a large frequency granularity. Instead (or as well) we would like a VCO that can run at a high (as high as possible for "best coverage") RF frequency which then be divided down, and that result fed to the VCO's phase comparator.
I don't know, be I may be asking for too much here.
That said though, I still think an NCO should have a square wave output........
If what I'm requesting is difficult to do in the next rev of silicon, then please abandon it. As the Propeller appeared to have the capability of true RF genereration, I was hoping to get the "whole package" and be able to get to higher frequencies, but that will then not be the case. While a lot of folks may be interested in the rudimentary RF capability the Propeller currently has, I expect they will be unable to get FCC certification with it.
I don't know if your suggestion will work, but to me it seems like a rather odd work-around, and if that is what is required, I will prefer to use an RF synthesizer meant for the job.
From my perspective, I think we've pretty much beat this subject to death; thanks for listening, and your perseverance!
At the risk of annoying some of the forum members, I'll have another go at explaining my point......
I continue to harp about the same approach, trying to use different word to get my point accross, but from your responses I can't sense that I'm getting through. Maybe it's just my thick skull.
Now, for the technology........ I would suggest a close read through the documentation on one of the National or Philips RF synthesizer chips.
Again, in somewhat different words, the FINAL VCO's RF OUTPUT frequency, Fvco, is divided down, say by M to generate a frequency Fo, and that is fed to a frequency/phase comparator. Similarly, some crystal oscillator (in our case perhaps the system clock, or a stable counter output) is divided-down, say by N to generate a reference Fc.
Both these divide-down signals Fo and Fc are fed to the phase comarator, and are (need to be), square waves to prevent jitter in the output of the phase comparator, and hence in the VCO output, Fvco.
The net effect of all this is that the phase lock loop controls the VCO such that Fvco is M times Fc.
Typically the reference Fc is chosen by selecting the base (crystal) frequency and divider N to yield a desired channel spacing for a multi-channel RF signal. Then by selecting different integer values for M, numerous channels at spacing Fc can be derived; all within the limits of the VCO's range of course.
Typically the reference Fc is chosen by selecting the base (crystal) frequency and divider N to yield a desired channel spacing for a multi-channel RF signal. Then by selecting different integer values for M, numerous channels at spacing Fc can be derived; all within the limits of the VCO's range of course.
I hope this explanation makes more sense.
Also, you still have N to play with to give a lot of flexibility...
Is there any possibility of just adding an RF DDS similar to the AD98xx series to the chip? http://www.analog.com/en/subCat/0,2879,770%255F843%255F0%255F%255F0%255F,00.html
Of course, one could just buy an AD chip, and paste it down on a circuit board.·
(But, since we're looking at the mostest,·bestest, fastest single·chip·solution for
everything...·· ...it's worth asking [noparse]:)[/noparse]
If I remember correctly from my college days, any squarewave or pulse could be described
as a series of sines and cosines from 0 (DC) to infinity.
In digital systems you would like to have square waves or pulses with fast rise and fall times.
This creates a condition for large harmonic content (chirps if you desired).
In the other hand for FM modulation, you want a pure sine wave carrier.
You can obtain a pure sine wave from a square wave by means of high Q passband filters.
Your statements are basically correct, although I did not study the formulas provided; too much math for my liking.
My issues are how to generate a stable high frequency waveform with good purity, and good selection range of frequencies, all done within the bounds of what's possible with the (perhaps somewhat modified) architecture of a Propeller.
Sure, very good synthesizers can be built, but how best to do that with or within a Propeller ?
Chip's the man who can best determine this; the rest of us can only offer suggestions and put forth our wishes. And sometimes that takes a bit of interaction. If all that is done "behind the scenes" through Private Messages, then we are missing the opportunity for others to add their insight and desires; furthermore, the public forum has the added benefit of helping teach or expose others to areas where they have not ventured before.
I realize this thread is dragging on a bit, and in my post of April 28, I was happy to abandon it. But a PM from Chip suggesting I not get discouraged and keep it alive prompted me to have "another go", so if "all the fuzz" is bothersome, please don't take it as an attempt to annoy folks; I'm just trying to express my wishes and needs and help others.
Well said, Peter. The counter system on the Propeller is perplexing, right up there with multiprocessing, and this thread has made me focus in on the issues.. Open discusssion can help us all understand it better.
The frequency synth you are suggesting is quite dfferent from the current propeller topology, so I'm wondering how how much of a stretch it is.
Translated to propeller, it might work like this: There would be
---divide by N counter from the master clock (ctra) as reference
---divide by M counter from the VCO (ctrb).
These would be separate dividers, not just binary, but with M and N any integer (within a limited range). If M and N are both divisible by two, the output of divider chains can be symmetrical square waves.
The phase comparison occurs at the low frequency, and the error term pushes the VCO in the direction that makes the two low frequencies equal. That is, frequencyA / N = frequencyVCO / M. Or to write it another way:
frequencyVCO = frequencyB = frequencyA * M/N
If N and M are large numbers, the spacing between adjacent frequencies can be small. For example, with frequencyA = 80mhz and N = 1280, the base comparison frequency would be 75khz, and different even values of M could give stable carriers spaced at M * 150 khz. That could be suitable carrier spacing for wideband FM channels. The modulation would have to be injected directly into the phase comparator, or into the VCO, or into the reference clock, to give continuous phase or frequency modulation of the carrier.
That scheme differs from the current Propeller topology in that it would require separate /N and /M counters (as opposed to the currrent simple /16 + NCO), and it would require a phase comparator between ctra and ctrb (instead of within each counter by itself), and finally, it would require analog access to either the VCO or the phase comparator, to inject continuous modulation, or modulation of the master clock.
The PLL associated with each Propeller COG counter currently has a fixed divide by 16 binary divider. The output of the /16 is compared with the output of the NCO (ctra or ctrb), and the error term pushes the VCO in the direction that makes the VCO output 16 times the NCO frequency. The output from the PLL system can be taken from any of the binary taps in the divider, at x1,x2,x4,x8 or x16. Some of the discussion in this thread has been about how to slow down the PLL response time so that it could act as a better filter, and Chip has said that could be easily done by setting a parameter. But that is a long way from the arbitrary N and M divders Peter is talking about.
El Paisa, it is true that the NCO as it exists now can (superficially) generate the desired division ratio:
frqa = masterClock * M/N
The thing about it is, the output of the NCO (from phsa(31)) is not a simple square wave. It is a much more complicated waveform that has frequency components that your equations do not account for. These are not just harmonics as you would have from a fourier expansion of a square or triangle wave. There are subharmonics that are not subpowers of two, and those noncommensurate subharmonics each have their own set of harmonics. That makes for a messy spectrum and jitter. It is true you could reduce of a lot of those undesired components with a good filter. For example with a slower PLL response. Plus LC filter externally.
The spectrum of the NCO is one thing. It has other important properties as well, that affect what frequencies are attainable in practical terms, and limit the possiblity for fine tuning or continuous FM modulation.
The behavior of the phsa register in the Propeller at each tick of the system clock can be generalized:
··phsa := (phsa + frqa) mod n,
where (in the Propeller's case) n = 232, with the NCO output that feeds the PLL corresponding to bit 31 of phsa. I'm wondering if any advantage could be bought by allowing the user to choose n, where the NCO output would change state whenever the modulo addition overflowed. In other words, how much of the undesired harmonic and subharmonic content derives from being constrained to a single modulus, and how much comes from the fact that the NCO's edges must always coincide with those of the system clock?
If there's any advantage to be gained, the implementation would not be much of a stretch from what we have now.
Phil, I don't think the mod 2^32 term will make much difference for most purposes. At 80 megahertz, it takes just short of one minute to run a full cycle. If the object is to generate a period of 30 seconds, a bobble of 12.5 nanoseconds is not going to make a big difference. On the other hand, for generation of short periods, high frequencies,, the numerical problem comes from the ratio of the desired output perod to the clock period and manifests itself over shorter time periods.
I don't mean to be overly pessimistic about the NCO. The difficulty is most acute at high output frequencies, where there are not many clock periods in each period of the output. For example, in order to generate an NCO output frequency of 6 mhz, from an 80mhz clk, the NCO output has to be made up of half-periods of 6 and 7 time slots in a pattern analogous to the number of days in the months, 30 or 31 (Feb=exception), with occasional leap years, and corrections every four centuries. The NCO is more regular than that, as the half-periods in the stated case will always be either 6 or 7, never 5 or 8, but there will be longer patterns in how the 6s and 7s are arranged in time. (It has a property of self-similarity, like fractals).
At lower frequencies, the number numbers are larger and the bobble from cycle to cycle is relatively small. For example at 40 khz output, the cycle is composed of 1000 ones followed by 1000 zeros. (frqa:=2147484) For slightly lower output frequencies, the period will have to bobble regularly to 1001 to make up the difference, but that wil be much less perceptable than the difference of 7 to 6.
I wonder, could phase locking lower NCO frequency could give a better spectral purity at the output? Say a PLL with division ratio of 256 locking to the NCO between 15625 hz and 31250 hz, instead of a Pll with division ratio 16 locking between 4 and 8 mhz?
Phil, I've been thinking about the notion of the "utility function" you brought up in another post. It would be an interesting kind of function.
I don't think the mod 2^32 term will make much difference. At 80 megahertz, it takes just short of one minute to run a full cycle. If the object is to generate a period of 30 seconds, a bobble of 12.5 nanoseconds won't matter. On the other hand, for generation of short periods, high frequencies,, the numerical problem comes from the ratio of the desired output perod to the clock period and manifests itself over shorter time periods.
I don't mean to be overly pessimistic about the NCO. The difficulty is most acute at high output frequencies, where there are not many clock periods in each period of the output. For example, in order to generate an NCO output frequency of 6 mhz from an 80mhz clk, the NCO output has to be made up of periods of 13 or 14 time slots in a pattern analogous to the number of days in the months, 30 or 31 (Feb=exception), with occasional leap years, and corrections every four centuries. The NCO is more regular than that, as the periods in the stated case will always be either 13 or 14, never 12 or 15. There are longer patterns in how the periods 13 and 14 are arranged in time to approximate a desired ratio, analogous to the arangement of months into a year, and the century corrections. But more systematic.
At lower frequencies, the numbers are larger and the bobble from cycle to cycle is relatively small. For example at 40 khz output, the cycle is composed of 1000 ones followed by 1000 zeros. (frqa:=2147484) (80M/40K = 2147483.648) There is a slight discrepancy in the mod 2^32 approximation, rounding up. In order to complete a cycle of 2^32, the period will have to bobble by one occasionally to make up the difference, but that wil be much less proportionally than the jitter from 6 to 7. The longer period is much closer to a symmetrical square wave.
I wonder, would phase locking lto a lower NCO frequency yield better spectral purity at the output? Suppose the PLL had a division ratio of 512 locking to the NCO between 125 khz->250 khz, multiplied up to an output frequency of 64 to 128mhz? Instead of a pll division ratio of 16.
Phil, I've been thinking about the notion of the "utility function" you brought up in another post. It would be an interesting kind of function, hard to describe.
Tracy, as a pathological example, suppose you wanted to generate a clean 128MHz signal with an 80MHz clock and a 232 counter. To generate the base NCO frequency of 8MHz, frqa would have to be 232 / 10, or about $19999999. The output of the NCO will be jittery, since frqa doesn't evenly divide 232. On the other hand, if you could choose the counter's modulus, you'd pick a value of 5, with a frqa value of 1 (for half cycles) and get clean square waves with no jitter.
Now I realize that total lack of jitter will occur only for those frequencies whose periods are even multiples of 12.5nS. But it's not hard to imagine (or at least hope) that improvements at these even-integer nodes would entail similar improvements across the board. But picking the best modulus and frequency adder for off-integer periods could be a challenge. And that's where the utility function comes in. If you could model the total system (PLLs, output filters, and all), you could define a function over the domain of moduli and frequency adders that would be high for high-purity, on-frequency signals and low for dirty or off-frequency ones. My optimism from being allowed to choose the counter modulus is based on the fact that the number of exact nodes available (and thus their density in any particular region of the utility function's domain) is increased dramatically over just the powers of two. Thus for any chosen frequency the number of nearby even-integer nodes is higher. And if the utility function is well-behaved, it's also more likely to take on higher values between those more closely-spaced nodes.
Phil,
For values like $19999999, there is no jitter, except once every !232 cycles due·to an imperfect fraction.·You will see a perfect square wave out of the NCO, with the jitter·occuring once every ~50 seconds·in the form of a phase decline. This is pretty perfect, otherwise. So, for 1/n values, you get pretty much the benefits of a divider-mode PLL. In the case of *m/n type numbers, the jitter is high-frequency only and the PLL can clean this up on its own. Try this out!
Phil Pilgrim (PhiPi) said...
Tracy, as a pathological example, suppose you wanted to generate a clean 128MHz signal with an 80MHz clock and a 232 counter. To generate the base NCO frequency of 8MHz, frqa would have to be 232 / 10, or about $19999999. The output of the NCO will be jittery, since frqa doesn't evenly divide 232. On the other hand, if you could choose the counter's modulus, you'd pick a value of 5, with a frqa value of 1 (for half cycles) and get clean square waves with no jitter.
Now I realize that total lack of jitter will occur only for those frequencies whose periods are even multiples of 12.5nS. But it's not hard to imagine (or at least hope) that improvements at these even-integer nodes would entail similar improvements across the board. But picking the best modulus and frequency adder for off-integer periods could be a challenge. And that's where the utility function comes in. If you could model the total system (PLLs, output filters, and all), you could define a function over the domain of moduli and frequency adders that would be high for high-purity, on-frequency signals and low for dirty or off-frequency ones. My optimism from being allowed to choose the counter modulus is based on the fact that the number of exact nodes available (and thus their density in any particular region of the utility function's domain) is increased dramatically over just the powers of two. Thus for any chosen frequency the number of nearby even-integer nodes is higher. And if the utility function is well-behaved, it's also more likely to take on higher values between those more closely-spaced nodes.
-Phil
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Chip Gracey
Parallax, Inc.
Post Edited (Chip Gracey) : 5/2/2006 8:46:33 PM GMT
It took a simulation to hammer it in, but I think I get it now: Any contribution to the undesired frequency content due to one's choice of modulus is going to have such a long period as to be insignificant (unless the modulus is too small, in which case the fundamental could be way off). The only significant contributor is the quantization of NCO half-periods on 1/clk intervals, and no choice of modulus will make a dent in that. Moreover, in general it would appear that the larger the modulus, the better for obtaining an accurate fundamental, even though exceptions abound for fundamental periods which are even multiples of the clock period.
It took a simulation to hammer it in, but I think I get it now: Any contribution to the undesired frequency content due to one's choice of modulus is going to have such a long period as to be insignificant (unless the modulus is too small, in which case the fundamental could be way off).
Yeah! That's right.
The only significant contributor is the quantization of NCO half-periods on 1/clk intervals, and no choice of modulus will make a dent in that.
I'm not sure I follow this, but it is the edge-to-edge NCO period that determines the spectral purity of the PLL, since it is corrected on an edge basis.
Moreover, in general it would appear that the larger the modulus, the better for obtaining an accurate fundamental, even though exceptions abound for fundamental periods which are even multiples of the clock period.
Is that an accurate summary?
That sounds right to me.
-Phil
I hope Peter sees that and comments, because this is what he was talking about achieving through multipliers and dividers. I hope he tries this to see if it makes what he wants any more possible.
The sequence of values in phsa is, in mathematical terms, a linear congruencial sequence, and the properties of such sequences are well understood mathematically. While they are very regular in the overall behavior, they also have a fine structure that reflects the properties of the rational numbers (M/N). So I can believe Peter's issue with the jitter and birdies that are enough to limit the utility and spectral purity for the purpose he has in mind, and I can also believe Chip that "This is pretty perfect, otherwise. ". Each ratio M/N has its own unique character, just like the different integers have prime factors and the numbers M and N have co-primes. The jitter component can vary wildly between two numbers that are close to one another, simply because of the decomposition of M and N into primes. And modulo 2^32 contributes an additional long period cycle.
Okay, I hate to beat this to death, but heck, I get a kick out of it. I just want to emphasize that there is exact math behind these cycles, but it may not be the kind of math (elementary number theory) that people are used to seeing.
Phil, the following examines the case you brought up of generating the the 8mhz ctra clock from the 80mhz master clock.
.....232 * 8/80 = 232 / 10 = 429496729.6
That can be rounded off either up or down, to 429496730=$1999999a or 429496729=$19999999
Depending on that choice, the long term periods will be slightly different. Probably insignificant, but this is an effort to pick nits for the sake of understanding. For most of the time, the cycle is a square wave of 5 low time slots plus 5 high time slots, each time slot being 12.5 nanoseconds.
Ten divides 232 with a remainder of 6. The question is what happens with the extra 6 time slots? Or it we round up, what happens to the four "holes" that come about when phsa overshoots 232, and wraps around to 4? The extra or missing time slots are not all bunched at the end. They are spread out evenly through the cycle.
In congruential sequences, the overall cycle can have a length up to 232, but no longer. The overall cycle length can be less than 232, and that happens when the divisor has factors of 2 in its prime factorization, as does in this case with 10=5*2.
Case 1, frqa:= $19999999
The entire cycle will repeat 3 times in 231 iterations, 26.8435456 seconds, with three phase corrections at intervals of 8.947853 seconds Look at it this way, making up 6 times 12.5ns time slots in 232 iterations is the same as making up 3 slots in 231 iterations. The factor of 3 is incommensurate, so it forces the overall cycle to have the /3 subharmonic with corrections at the 8+ second intervals. There are actually two possible cycles of length 231. The cycle starting with phsa=0 has no numbers in common with the cycle that starts with phsa=1. They are mutually exclusive, but both of length 231. One steps through all the even numbers, the other through all the odd numbers.
Case 2, frqa:= $1999999a
The entire cycle repeats in 231 iterations (due to that factor of 2 in 10=5*2), 26.8435456 seconds, with two phase corrections at intervals of 13.4217728 seconds. Making up two in 231 cycles is the same as making up four in 232. There are two mutually exclusive cycles, spanning the even numbers and the odd numbers.
I like to think about these problems in terms of smaller numbers. For example, think about a 5 bit counter with 64 states instead of a 32 bit counter with 4 million+ states. The sequence of phsa values in this miniature 5 bit ctra with frqa=10 is:
Note that every even number is covered. If it instead starts with phsa=1, it will cover every odd number. The cycle length is 32, not 64. Here is the sequence of zeros and ones emitted by phsa(4), the high bit output, which is 1 iff phsa>31.
There are a total of 16 zeros and 16 ones in the cycle and there are two phase corrections where the number of zeros or number of ones in a run blips to 4 instead of the usual 3. There are 5 groups in the cycle (which has to do with the factor 5*2 = 10).
The logic for the 32 bit cycle is the same. The phase corrections are spread out by long long stretches of "regular" behavior. The long cycles are possible because of the 32 bit modulus, which allows a really good approximation to the ratio 1/10, but the phase corrections are necessary to make it fit. The number and position of the corrections are deterministic, and there is math to predict where they will occur.
Thanks for your exhaustive treatment! Oddly enough, when I did my simulation, I used exactly the same output format in my printout as in your second illustration above. You can see at a glance what's happening.
Of course, none of this solves Peter's issues with birdies -- except maybe Chip's suggestion to couple the PLL's phase detector more loosely. But there's another idea that's been kicking around my head, and that's to use two counters and heterodyne their outputs. The idea is that if generating the desired frequency on a single counter produces too many undesirables, maybe one could find two, more cleanly-generated frequencies whose sum or difference yields the frequency of choice. Of course, they would also have to be selected such that any unwanted mixer products could easily be filtered out. The mixing might be as simple as XORing the two counter outputs, which is the same as multiplying two (-1, 1) squarewaves. OTOH, that may produce so many extra harmonics, that it may be better to filter them first and use more traditional mixing techniques.
In Peter's case, he might benefit from mixing 64MHz (4MHz NCO) and 128MHz (8MHz NCO) to get his 96MHz. Both 4 and 8 MHz NCOs should produce clean PLL outputs, since their periods are multiples of the clock period; whereas 6MHz does not. It may not always be possible to find two frequencies that would help in this regard, though. Maybe there's an answer in number theory...
You've been doing some significant mathematical analysis...... the theory is more than I care to try to recall from university days; my brain will hurt too much as that was way too long ago.
Please understand that I was not specifically looking for RF at 96 MHz. That was thought to simply be a convenient test frequency to generate in the FM band. I'm looking to generate a selection of frequencies in the 915 MHz. ISM band. Since the PLL frequency (currently) is specified only to 128 MHz, I'd hoped to be able to pull the 7th harmonic out of about 130 Mhz.
But this is when I discovered to FM band plastered with birdies, and that led to my investigation.
Another point, in generating RF that may need to be FCC certified, "pretty clean" doesn't cut it. Those boys are pretty strict, and its not trivial to get past them even if you start of "squeaky clean".
I think I may be pushing too hard on the square peg into the round hole here........ though I still believe that any NCO should have a square wave output!
And to do that, a down counter off the VCO output is the answer. Perhaps in the next rev of silicon.
Comments
Well, not quite; the conventional RF synthesizer approach is to divide-down the final output frequency, and then phaselock that result to a selectable reference. In our case here, the reference is good (other than probably needing to be a square wave to provide purity to the phase comparator), but we would like to be able to have the divide-down feature.
At present, a base frequency is generated, and that is cranked up by a selectable PLL ratio. For generationg (almost) any desired high frequency, this is backwards and leads to a large frequency granularity. Instead (or as well) we would like a VCO that can run at a high (as high as possible for "best coverage") RF frequency which then be divided down, and that result fed to the VCO's phase comparator.
I don't know, be I may be asking for too much here.
That said though, I still think an NCO should have a square wave output........
Cheers,
Peter (pjv)
I can understand how this would always get you a square wave, but I still can't see the benefit for any kind of precise FM'ing. By having·programmable multipliers and dividers, you can hit close to many frequencies with a real square wave, but you must always do a multiplier-divisor search to find the optimal combo for any frequency, right? Doesn't this make FM'ing a 100MHz carrier by +/- 0-50KHz (in small steps)·quite unlikely? What the Propeller has now, while phase-noisy, does have simple, numerically linear control over average frequency of the NCO - from a programming standpoint this couldn't be much simpler. And with 32 bits, your frequency·granularity is sub-Hz, even with 16x VCO multiplication.·I think that if·the VCO's·charge-pump current was reduced, it might be way cleaner spectrum-wise. I used a multiply-divide type PLL before on the SX-Key and there was a ~0.1% limit on frequency accuracy with, I believe, 8 and 9 bits of multiplier and divisor resolutions. At 100MHz that would be ~100KHz steps - pretty rough, and not necessarily identical on either side of the 'center'.
Is it most important to you to be able to get NEAR what frequency you care about with a real square wave because you can live with big frequency steps in either direction?
What about this: Do you think you could play some variable loading game on the crystal pins to detune the master clock to get the gentle, but spectrally pure FM you're looking for at higher frequencies via the PLL? Maybe an I/O pin could be modulated to introduce some variable impeadance through·an RLC network into the XIN and/or XOUT pins. I've never attempted this, and I don't understand exactly HOW this should work, but I assume there must be a way to achieve this. I'm thinking you would program a power-of-2 value into the FRQ register and, like Tracy said, go for the master clock, instead, to keep things clean.
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Chip Gracey
Parallax, Inc.
If what I'm requesting is difficult to do in the next rev of silicon, then please abandon it. As the Propeller appeared to have the capability of true RF genereration, I was hoping to get the "whole package" and be able to get to higher frequencies, but that will then not be the case. While a lot of folks may be interested in the rudimentary RF capability the Propeller currently has, I expect they will be unable to get FCC certification with it.
I don't know if your suggestion will work, but to me it seems like a rather odd work-around, and if that is what is required, I will prefer to use an RF synthesizer meant for the job.
From my perspective, I think we've pretty much beat this subject to death; thanks for listening, and your perseverance!
Cheers,
Peter (pjv)
At the risk of annoying some of the forum members, I'll have another go at explaining my point......
I continue to harp about the same approach, trying to use different word to get my point accross, but from your responses I can't sense that I'm getting through. Maybe it's just my thick skull.
Now, for the technology........ I would suggest a close read through the documentation on one of the National or Philips RF synthesizer chips.
Again, in somewhat different words, the FINAL VCO's RF OUTPUT frequency, Fvco, is divided down, say by M to generate a frequency Fo, and that is fed to a frequency/phase comparator. Similarly, some crystal oscillator (in our case perhaps the system clock, or a stable counter output) is divided-down, say by N to generate a reference Fc.
Both these divide-down signals Fo and Fc are fed to the phase comarator, and are (need to be), square waves to prevent jitter in the output of the phase comparator, and hence in the VCO output, Fvco.
The net effect of all this is that the phase lock loop controls the VCO such that Fvco is M times Fc.
Typically the reference Fc is chosen by selecting the base (crystal) frequency and divider N to yield a desired channel spacing for a multi-channel RF signal. Then by selecting different integer values for M, numerous channels at spacing Fc can be derived; all within the limits of the VCO's range of course.
I hope this explanation makes more sense.
Cheers,
Peter (pjv)
Is there any possibility of just adding an RF DDS similar to the AD98xx series to the chip?
http://www.analog.com/en/subCat/0,2879,770%255F843%255F0%255F%255F0%255F,00.html
Of course, one could just buy an AD chip, and paste it down on a circuit board.·
(But, since we're looking at the mostest,·bestest, fastest single·chip·solution for
everything...·· ...it's worth asking [noparse]:)[/noparse]
-Dan
·
If I remember correctly from my college days, any squarewave or pulse could be described
as a series of sines and cosines from 0 (DC) to infinity.
In digital systems you would like to have square waves or pulses with fast rise and fall times.
This creates a condition for large harmonic content (chirps if you desired).
In the other hand for FM modulation, you want a pure sine wave carrier.
You can obtain a pure sine wave from a square wave by means of high Q passband filters.
I am correct or I am wrong?
Your statements are basically correct, although I did not study the formulas provided; too much math for my liking.
My issues are how to generate a stable high frequency waveform with good purity, and good selection range of frequencies, all done within the bounds of what's possible with the (perhaps somewhat modified) architecture of a Propeller.
Sure, very good synthesizers can be built, but how best to do that with or within a Propeller ?
Chip's the man who can best determine this; the rest of us can only offer suggestions and put forth our wishes. And sometimes that takes a bit of interaction. If all that is done "behind the scenes" through Private Messages, then we are missing the opportunity for others to add their insight and desires; furthermore, the public forum has the added benefit of helping teach or expose others to areas where they have not ventured before.
I realize this thread is dragging on a bit, and in my post of April 28, I was happy to abandon it. But a PM from Chip suggesting I not get discouraged and keep it alive prompted me to have "another go", so if "all the fuzz" is bothersome, please don't take it as an attempt to annoy folks; I'm just trying to express my wishes and needs and help others.
Cheers,
Peter (pjv)
The frequency synth you are suggesting is quite dfferent from the current propeller topology, so I'm wondering how how much of a stretch it is.
Translated to propeller, it might work like this: There would be
---divide by N counter from the master clock (ctra) as reference
---divide by M counter from the VCO (ctrb).
These would be separate dividers, not just binary, but with M and N any integer (within a limited range). If M and N are both divisible by two, the output of divider chains can be symmetrical square waves.
The phase comparison occurs at the low frequency, and the error term pushes the VCO in the direction that makes the two low frequencies equal. That is, frequencyA / N = frequencyVCO / M. Or to write it another way:
frequencyVCO = frequencyB = frequencyA * M/N
If N and M are large numbers, the spacing between adjacent frequencies can be small. For example, with frequencyA = 80mhz and N = 1280, the base comparison frequency would be 75khz, and different even values of M could give stable carriers spaced at M * 150 khz. That could be suitable carrier spacing for wideband FM channels. The modulation would have to be injected directly into the phase comparator, or into the VCO, or into the reference clock, to give continuous phase or frequency modulation of the carrier.
That scheme differs from the current Propeller topology in that it would require separate /N and /M counters (as opposed to the currrent simple /16 + NCO), and it would require a phase comparator between ctra and ctrb (instead of within each counter by itself), and finally, it would require analog access to either the VCO or the phase comparator, to inject continuous modulation, or modulation of the master clock.
The PLL associated with each Propeller COG counter currently has a fixed divide by 16 binary divider. The output of the /16 is compared with the output of the NCO (ctra or ctrb), and the error term pushes the VCO in the direction that makes the VCO output 16 times the NCO frequency. The output from the PLL system can be taken from any of the binary taps in the divider, at x1,x2,x4,x8 or x16. Some of the discussion in this thread has been about how to slow down the PLL response time so that it could act as a better filter, and Chip has said that could be easily done by setting a parameter. But that is a long way from the arbitrary N and M divders Peter is talking about.
El Paisa, it is true that the NCO as it exists now can (superficially) generate the desired division ratio:
frqa = masterClock * M/N
The thing about it is, the output of the NCO (from phsa(31)) is not a simple square wave. It is a much more complicated waveform that has frequency components that your equations do not account for. These are not just harmonics as you would have from a fourier expansion of a square or triangle wave. There are subharmonics that are not subpowers of two, and those noncommensurate subharmonics each have their own set of harmonics. That makes for a messy spectrum and jitter. It is true you could reduce of a lot of those undesired components with a good filter. For example with a slower PLL response. Plus LC filter externally.
The spectrum of the NCO is one thing. It has other important properties as well, that affect what frequencies are attainable in practical terms, and limit the possiblity for fine tuning or continuous FM modulation.
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Tracy Allen
www.emesystems.com
··phsa := (phsa + frqa) mod n,
where (in the Propeller's case) n = 232, with the NCO output that feeds the PLL corresponding to bit 31 of phsa. I'm wondering if any advantage could be bought by allowing the user to choose n, where the NCO output would change state whenever the modulo addition overflowed. In other words, how much of the undesired harmonic and subharmonic content derives from being constrained to a single modulus, and how much comes from the fact that the NCO's edges must always coincide with those of the system clock?
If there's any advantage to be gained, the implementation would not be much of a stretch from what we have now.
-Phil
I don't mean to be overly pessimistic about the NCO. The difficulty is most acute at high output frequencies, where there are not many clock periods in each period of the output. For example, in order to generate an NCO output frequency of 6 mhz, from an 80mhz clk, the NCO output has to be made up of half-periods of 6 and 7 time slots in a pattern analogous to the number of days in the months, 30 or 31 (Feb=exception), with occasional leap years, and corrections every four centuries. The NCO is more regular than that, as the half-periods in the stated case will always be either 6 or 7, never 5 or 8, but there will be longer patterns in how the 6s and 7s are arranged in time. (It has a property of self-similarity, like fractals).
At lower frequencies, the number numbers are larger and the bobble from cycle to cycle is relatively small. For example at 40 khz output, the cycle is composed of 1000 ones followed by 1000 zeros. (frqa:=2147484) For slightly lower output frequencies, the period will have to bobble regularly to 1001 to make up the difference, but that wil be much less perceptable than the difference of 7 to 6.
I wonder, could phase locking lower NCO frequency could give a better spectral purity at the output? Say a PLL with division ratio of 256 locking to the NCO between 15625 hz and 31250 hz, instead of a Pll with division ratio 16 locking between 4 and 8 mhz?
Phil, I've been thinking about the notion of the "utility function" you brought up in another post. It would be an interesting kind of function.
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Tracy Allen
www.emesystems.com
I don't think the mod 2^32 term will make much difference. At 80 megahertz, it takes just short of one minute to run a full cycle. If the object is to generate a period of 30 seconds, a bobble of 12.5 nanoseconds won't matter. On the other hand, for generation of short periods, high frequencies,, the numerical problem comes from the ratio of the desired output perod to the clock period and manifests itself over shorter time periods.
I don't mean to be overly pessimistic about the NCO. The difficulty is most acute at high output frequencies, where there are not many clock periods in each period of the output. For example, in order to generate an NCO output frequency of 6 mhz from an 80mhz clk, the NCO output has to be made up of periods of 13 or 14 time slots in a pattern analogous to the number of days in the months, 30 or 31 (Feb=exception), with occasional leap years, and corrections every four centuries. The NCO is more regular than that, as the periods in the stated case will always be either 13 or 14, never 12 or 15. There are longer patterns in how the periods 13 and 14 are arranged in time to approximate a desired ratio, analogous to the arangement of months into a year, and the century corrections. But more systematic.
At lower frequencies, the numbers are larger and the bobble from cycle to cycle is relatively small. For example at 40 khz output, the cycle is composed of 1000 ones followed by 1000 zeros. (frqa:=2147484) (80M/40K = 2147483.648) There is a slight discrepancy in the mod 2^32 approximation, rounding up. In order to complete a cycle of 2^32, the period will have to bobble by one occasionally to make up the difference, but that wil be much less proportionally than the jitter from 6 to 7. The longer period is much closer to a symmetrical square wave.
I wonder, would phase locking lto a lower NCO frequency yield better spectral purity at the output? Suppose the PLL had a division ratio of 512 locking to the NCO between 125 khz->250 khz, multiplied up to an output frequency of 64 to 128mhz? Instead of a pll division ratio of 16.
Phil, I've been thinking about the notion of the "utility function" you brought up in another post. It would be an interesting kind of function, hard to describe.
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Tracy Allen
www.emesystems.com
Now I realize that total lack of jitter will occur only for those frequencies whose periods are even multiples of 12.5nS. But it's not hard to imagine (or at least hope) that improvements at these even-integer nodes would entail similar improvements across the board. But picking the best modulus and frequency adder for off-integer periods could be a challenge. And that's where the utility function comes in. If you could model the total system (PLLs, output filters, and all), you could define a function over the domain of moduli and frequency adders that would be high for high-purity, on-frequency signals and low for dirty or off-frequency ones. My optimism from being allowed to choose the counter modulus is based on the fact that the number of exact nodes available (and thus their density in any particular region of the utility function's domain) is increased dramatically over just the powers of two. Thus for any chosen frequency the number of nearby even-integer nodes is higher. And if the utility function is well-behaved, it's also more likely to take on higher values between those more closely-spaced nodes.
-Phil
For values like $19999999, there is no jitter, except once every !232 cycles due·to an imperfect fraction.·You will see a perfect square wave out of the NCO, with the jitter·occuring once every ~50 seconds·in the form of a phase decline. This is pretty perfect, otherwise. So, for 1/n values, you get pretty much the benefits of a divider-mode PLL. In the case of *m/n type numbers, the jitter is high-frequency only and the PLL can clean this up on its own. Try this out!
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Chip Gracey
Parallax, Inc.
Post Edited (Chip Gracey) : 5/2/2006 8:46:33 PM GMT
It took a simulation to hammer it in, but I think I get it now: Any contribution to the undesired frequency content due to one's choice of modulus is going to have such a long period as to be insignificant (unless the modulus is too small, in which case the fundamental could be way off). The only significant contributor is the quantization of NCO half-periods on 1/clk intervals, and no choice of modulus will make a dent in that. Moreover, in general it would appear that the larger the modulus, the better for obtaining an accurate fundamental, even though exceptions abound for fundamental periods which are even multiples of the clock period.
Is that an accurate summary?
-Phil
Chip Gracey
Parallax, Inc.
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Tracy Allen
www.emesystems.com
Phil, the following examines the case you brought up of generating the the 8mhz ctra clock from the 80mhz master clock.
.....232 * 8/80 = 232 / 10 = 429496729.6
That can be rounded off either up or down, to 429496730=$1999999a or 429496729=$19999999
Depending on that choice, the long term periods will be slightly different. Probably insignificant, but this is an effort to pick nits for the sake of understanding. For most of the time, the cycle is a square wave of 5 low time slots plus 5 high time slots, each time slot being 12.5 nanoseconds.
Ten divides 232 with a remainder of 6. The question is what happens with the extra 6 time slots? Or it we round up, what happens to the four "holes" that come about when phsa overshoots 232, and wraps around to 4? The extra or missing time slots are not all bunched at the end. They are spread out evenly through the cycle.
In congruential sequences, the overall cycle can have a length up to 232, but no longer. The overall cycle length can be less than 232, and that happens when the divisor has factors of 2 in its prime factorization, as does in this case with 10=5*2.
Case 1, frqa:= $19999999
The entire cycle will repeat 3 times in 231 iterations, 26.8435456 seconds, with three phase corrections at intervals of 8.947853 seconds Look at it this way, making up 6 times 12.5ns time slots in 232 iterations is the same as making up 3 slots in 231 iterations. The factor of 3 is incommensurate, so it forces the overall cycle to have the /3 subharmonic with corrections at the 8+ second intervals. There are actually two possible cycles of length 231. The cycle starting with phsa=0 has no numbers in common with the cycle that starts with phsa=1. They are mutually exclusive, but both of length 231. One steps through all the even numbers, the other through all the odd numbers.
Case 2, frqa:= $1999999a
The entire cycle repeats in 231 iterations (due to that factor of 2 in 10=5*2), 26.8435456 seconds, with two phase corrections at intervals of 13.4217728 seconds. Making up two in 231 cycles is the same as making up four in 232. There are two mutually exclusive cycles, spanning the even numbers and the odd numbers.
I like to think about these problems in terms of smaller numbers. For example, think about a 5 bit counter with 64 states instead of a 32 bit counter with 4 million+ states. The sequence of phsa values in this miniature 5 bit ctra with frqa=10 is:
Note that every even number is covered. If it instead starts with phsa=1, it will cover every odd number. The cycle length is 32, not 64. Here is the sequence of zeros and ones emitted by phsa(4), the high bit output, which is 1 iff phsa>31.
There are a total of 16 zeros and 16 ones in the cycle and there are two phase corrections where the number of zeros or number of ones in a run blips to 4 instead of the usual 3. There are 5 groups in the cycle (which has to do with the factor 5*2 = 10).
The logic for the 32 bit cycle is the same. The phase corrections are spread out by long long stretches of "regular" behavior. The long cycles are possible because of the 32 bit modulus, which allows a really good approximation to the ratio 1/10, but the phase corrections are necessary to make it fit. The number and position of the corrections are deterministic, and there is math to predict where they will occur.
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Tracy Allen
www.emesystems.com
Thanks for your exhaustive treatment! Oddly enough, when I did my simulation, I used exactly the same output format in my printout as in your second illustration above. You can see at a glance what's happening.
Of course, none of this solves Peter's issues with birdies -- except maybe Chip's suggestion to couple the PLL's phase detector more loosely. But there's another idea that's been kicking around my head, and that's to use two counters and heterodyne their outputs. The idea is that if generating the desired frequency on a single counter produces too many undesirables, maybe one could find two, more cleanly-generated frequencies whose sum or difference yields the frequency of choice. Of course, they would also have to be selected such that any unwanted mixer products could easily be filtered out. The mixing might be as simple as XORing the two counter outputs, which is the same as multiplying two (-1, 1) squarewaves. OTOH, that may produce so many extra harmonics, that it may be better to filter them first and use more traditional mixing techniques.
In Peter's case, he might benefit from mixing 64MHz (4MHz NCO) and 128MHz (8MHz NCO) to get his 96MHz. Both 4 and 8 MHz NCOs should produce clean PLL outputs, since their periods are multiples of the clock period; whereas 6MHz does not. It may not always be possible to find two frequencies that would help in this regard, though. Maybe there's an answer in number theory...
-Phil
You've been doing some significant mathematical analysis...... the theory is more than I care to try to recall from university days; my brain will hurt too much as that was way too long ago.
Please understand that I was not specifically looking for RF at 96 MHz. That was thought to simply be a convenient test frequency to generate in the FM band. I'm looking to generate a selection of frequencies in the 915 MHz. ISM band. Since the PLL frequency (currently) is specified only to 128 MHz, I'd hoped to be able to pull the 7th harmonic out of about 130 Mhz.
But this is when I discovered to FM band plastered with birdies, and that led to my investigation.
Another point, in generating RF that may need to be FCC certified, "pretty clean" doesn't cut it. Those boys are pretty strict, and its not trivial to get past them even if you start of "squeaky clean".
I think I may be pushing too hard on the square peg into the round hole here........ though I still believe that any NCO should have a square wave output!
And to do that, a down counter off the VCO output is the answer. Perhaps in the next rev of silicon.
Cheers,
Peter (pjv)