The new controller mentioned in Nuts & Volts

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Comments

  • DiablodeMorteDiablodeMorte Posts: 238
    edited 2006-02-20 - 00:20:08
    Holy Crap. I just realzied something. a few weeks back i asked if there was ever going to be multitasking on a basic stamp.. Damn. When you people said my statment was ironic you REALLY ment it
  • Paul BakerPaul Baker Posts: 6,351
    edited 2006-02-20 - 03:01:16
    I too was lucky enough to be invited to the seminar, and it was great being able to meet all the folks at Parallax in person. They are as great in person as they are online. Im the guy in the picture sitting next to the gentleman with the (full) white beard. I have a red shirt on and have my hand raised.

    I will not answer anyones technical or business related questions on the chip, Jon and Jeff will answer what they want to release. After the official release I of course will answer whatever I can. I have heard what thier target realease date is, but I won't say, just know that is isn't too far off. From my brief experience with the chip, it appears to me there with be a steeper learning curve for someone coming straight from a BASIC Stamp without having SX or other microcontroller experience, but that doesn't mean a Stamper couldn't learn. The Spin language should make it a little easier of a transition for that crowd, but dont expect it to be quite as plug and play as the stamp and don't expect it to be a multi-processor version Stamp, since there is quite a difference between PBASIC and Spin.

    Some qualitative properties are that its lean, fast, versatile, very powerful and runs very cool (can't really detect any heating with the old finger test).

    The only tech question already posed that I will answer is RoboGeek's, each pin can drive 50mA, but they haven't tested total package current ability. They designed it extremely well but it hasn't specifically been tested to output all pins at 50mA simultaneously yet, so don't expect it can until they do test what total current it can handle.

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  • Dave_BellDave_Bell Posts: 11
    edited 2006-02-20 - 03:38:36
    Is there a chance of posting (or a link to) a better block diagram picture?
    The gif already out there is too low res to make much sense out of...

    Dave
  • Agent CobaltAgent Cobalt Posts: 88
    edited 2006-02-20 - 03:49:46
    I can wait for the processor to come out because I know Parallax is going to make sure that everything's perfect (they spent years on it so why screw that up), but I'd like to see maybe some of the commands and some example code so I could get a head start at learning some of the language so that when it does come out, I don't have the chip sitting around for awhile while I read how some of the stuff works, even though I'll probably have some simple things running withing 5 minutes of receiving it. lol.gif

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    Truth can be dangerous... Trust can be deadly.
  • Martin HebelMartin Hebel Posts: 1,231
    edited 2006-02-20 - 04:24:18
    The installer will provide many example programs to help you get started, including direct out to to audio, TV video or VGA, and input from Keyboard or mouse.· Using them all simultaneously if you like!· As mentioned, it's totally software driven, and while they are working on it, there will still be plenty of objects to create in software, such as I2C and SPI drivers, and PBASIC standards like FREQOUT, RCTime, etc,·which will·keep many here creating and sharing for many years to come.

    Not only is the device itself above and beyond anything else out there, the IDE that goes with it is also fantastic.· It should really help in code development, re-usable code, and documentation!

    One thing that I really like is that the main memory is shared by all processors. So let's say you have 3 different 'cogs' running, which all need to perform common routines, such as number conversions, they all tap the same common memory for those code objects reducing redundant code significantly.

    While sorely tempted to post some code snippets, it would lead to too many Q's, and who knows, they took some feedback on how the code was·formatted and may·do some tweaks before release.· I think those of us who attended are free to answer general Q's concerning it, but any specifics such·marketing plans or release of documents will be left to Parallax.

    The gif image of the internals also have some revs coming (renaming of certain parts), so I'm reluctant to post even that in a better image with an OK from our hosts.

    BTW, I'm in the back row, 2nd from right from camera's perspective.· It was a·great group of Parallax partners/contacts in education, engineering and end customers.

    -Martin

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    Martin Hebel
    Southern Illinois University Carbondale -Electronic Systems Technologies
    Personal Links with plenty of BASIC Stamp info
    and SelmaWare Solutions - StampPlot - Graphical Data Acquisition and Control
  • currentccurrentc Posts: 9
    edited 2006-02-20 - 05:50:35
    If you download the 2006 product catalog there is a better diagram on page 79.
  • LoopyBytelooseLoopyByteloose Posts: 12,537
    edited 2006-02-20 - 06:09:41
    50ma on each pin may be very convienent for avoiding bench wiring errors causing undue failures, but with a 40-44 pin package there has to be a thermodynamic reality to how much heat can be generated at one time. [noparse][[/noparse]The total power consumption converts to total heat generated]

    In other words, unless there is a Pelteir cooling·device inside, the total surface area and the package material ultimately determine when the heat becomes destructive.

    Of course there may be localized power hogs and limits within a chip too. I noticed the Amtels [noparse][[/noparse]which are really wimpy about power output per pin] mention a limit per each 8bit i/o port. In some ways that is a more useful design limit [noparse][[/noparse]if it is a real limit of course]. We tend to bank data into 8 bit ports even when it may not be termally best.

    The SX-48 and SX-28 seem to handle about 200ma total. That is one watt. Seems to me that even doubling to two watts would be a challenge, heat-wise.

    The beauty of the Propeller seems to be its MIPS and its ability to multitask. While I think everyone knows that I don't know much about that, I am still quite interested to learn. [noparse][[/noparse]please forgive my speculations.]

    I don't expect to use this to drive more that the SX's 25ma. The extra power consumption may just create EMI or shorten the device's useful life. Why use 10, 20, or 50 ma to do the job that 1ma can do?

    In sum, consider moving your power consumption into support devices that are meant to take the abuse and can be easily replaced if they fail frequently or unexpectedly.

    The real challange remains to understand how to support and teach such a sophisticated concept.

    And, PLEASE, PLEASE MAKE THE POSTED DIAGRAM BIGGER. Even under 20x magnification it is all a blur.

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    "When all think alike, no one is thinking very much.' - Walter Lippmann (1889-1974)

    ······································································ Warm regards,····· G. Herzog [noparse][[/noparse]·黃鶴 ]·in Taiwan

    Post Edited (Kramer) : 2/20/2006 6:18:05 AM GMT
  • Beau SchwabeBeau Schwabe Posts: 6,427
    edited 2006-02-20 - 06:41:19
    Kramer,

    No Peltier device inside the Propeller. smile.gif

    "The SX-48 and SX-28 seem to handle about 200ma total. That is one watt."

    Kramer, you are correct, but that is also at 5V. The Propeller runs at 3.3V... at 200mV that's only 660mW


    "I don't expect to use this to drive more that the SX's 25ma. The extra power consumption may just create
    EMI or shorten the device's useful life. Why use 10, 20, or 50 ma to do the job that 1ma can do?"

    I agree 100%, this is the way you should think when considering a new design. If you think about it, these
    kinds of specifications are really just a way to quantify how much abuse the device can take. Certainly with
    good design practice that leans more towards the minimum values, you will increase the life expectancy of
    ANY IC that you choose to use in a design.

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    [url=mailto:bschwabe@parallax.com]Beau Schwabe[/url]

    IC Layout Engineer
    Parallax, Inc.
  • Dave_BellDave_Bell Posts: 11
    edited 2006-02-20 - 07:04:21
    Thanks, currentc - the 2006 catalog page is MUCH better!
    Check it out, Kramer...

    Dave
  • Dave_BellDave_Bell Posts: 11
    edited 2006-02-20 - 07:11:44
    The improved drawing clarifies a good bit about the internals of the Propeller, but that always leads to more questions. :{) The Cog & Hub interaction drawing is intriguing, with the distributor-like action. Does this rlate to the common data and address bus shared by all the Cogs? Presumably by the Bus Sequencer? Is there then some inherent order in which the Cogs get access to the common resources? What effect does this have on latency between Cog processes?

    Dave
  • Paul BakerPaul Baker Posts: 6,351
    edited 2006-02-20 - 07:13:49
    Guys stop asking for diagrams, prices, release dates, commands and any other specific info on the new chip. Its clear that the Parallax staff isn't going to release them ahead when they want to. Those of us who do have the information have been asked not to divulge anything beyond vague paraphrasing of what has been provided to us. And none of us want to break our assurance to Parallax to keep the details under wraps, I for one want to be considered for future special events and wont jeprodize that by releasing info on a chip that isn't availible yet. You will find out everything you are seeking in due course, its not like you are going to be able to do anything with the information at this moment anyways. A very good reason is many of the details aren't completely set in stone and are subject to changes before release. The chip is much more like the SX than stamp in that many functions such as the video generation and other features are in user level software (akin to source code level libraries) and hence may change before the release date.

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    ·1+1=10

    Post Edited (Paul Baker) : 2/20/2006 7:16:45 AM GMT
  • LoopyBytelooseLoopyByteloose Posts: 12,537
    edited 2006-02-20 - 08:21:13
    Hi Paul,
    I realize the dilemma, but it all is a bit silly. We want to know more and no one will say much.

    I can appreciate that there are software programmers and writers involved in trapping last minute errors [noparse][[/noparse]product development is just about the most grueling things that a human can do to oneself].

    I am very happy that the chip is like the SX [noparse][[/noparse]I really hope and pray that the Assembler uses the same Mnemonics as a sub-set, RISC of course] because that has been my focus for over a year now. And I am somewhat pleased that there is little or no need for interrupts [noparse][[/noparse]even if that turns my thinking upside-down].

    But, this is the problem with creating a buzz. People want to speculate about what it is, people want to try to figure it into their personal context, and people want to express their appreciation for being so innovative, rather than hum-drum.

    I am very, very, very [noparse][[/noparse]add very X 10000] interested in being able to use a keyboard and video. I am also interested in adding a uALFAT-SD for significant RAM support. But, I really don't know if I am dreaming [noparse][[/noparse]as I often do].

    Software changes are to be expected -- both before and after. But, after all this is buzz. .. . . I will reaffirm that I am one of many that will jump in and buy the first release. Waiting for Christmas is just not easy.

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    "When all think alike, no one is thinking very much.' - Walter Lippmann (1889-1974)

    ······································································ Warm regards,····· G. Herzog [noparse][[/noparse]·黃鶴 ]·in Taiwan

    Post Edited (Kramer) : 2/20/2006 1:57:31 PM GMT
  • Martin HebelMartin Hebel Posts: 1,231
    edited 2006-02-20 - 14:05:08
    If all goes as planned, it will be well before Christmas. Hey wouldn't have had us out and released information if it was still that far off. They can handle a buzz for a bit, not a revolt [noparse]:)[/noparse]

    -MH

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    Martin Hebel
    Southern Illinois University Carbondale -Electronic Systems Technologies
    Personal Links with plenty of BASIC Stamp info
    and SelmaWare Solutions - StampPlot - Graphical Data Acquisition and Control
  • ElectronegativityElectronegativity Posts: 311
    edited 2006-02-20 - 14:59:10
    To answer Gadgetman's Question:

    80 MHz = 20 MIPS because each instruction requires 4 clock cycles:

    1. Fetch
    2. Decode
    3. Execute
    4. Write back

    This is referred to as the instruction pipeline in the SX documentation.

    Note that the actual speed would be somewhat less than 20 MIPS because branching instructions (jumps) clear the pipeline.


    P.S. If we know what's good for us we should lowball our price estimates, starting with me:

    I think the propellor will cost $4 and there will be $10 prototype boards like the ones for the SX48 wink.gif

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    I wonder if this wire is hot...
  • SteveWSteveW Posts: 246
    edited 2006-02-20 - 15:15:43
    >80 MHz = 20 MIPS because each instruction requires 4 clock cycles:

    Err, that's not necessarily the case. The SX retires one intruction per clock (unless you cripple it to emulate a PIC), since it's pipelined. I'd really hope that the new architecture isn't crippled...

    Steve
  • ElectronegativityElectronegativity Posts: 311
    edited 2006-02-20 - 15:43:50
    blush.gif Steve is right, I realized my mistake a few seconds after posting that.

    20 MIPS is the minimum, if all the commands were jumps, the maximum is close to 80 MIPS.

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    I wonder if this wire is hot...
  • GadgetmanGadgetman Posts: 2,436
    edited 2006-02-20 - 16:23:41
    Do you have any datasheets on it if you can write that?

    Nowhere in what Parallax have let us see does it mention anything about how many cycles an instruction takes.

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  • Jeff MartinJeff Martin Posts: 610
    edited 2006-02-20 - 16:27:24
    rockin_rick said...
    Can any cog start and stop any other cog? Or are the cogs 'prioritized' so that only a higher level cog can 'control' a lower level cog? How much interaction is there cog-to-cog?
    Yes, any cog can start and stop any other cog or can even stop itself or relaunch itself with new code.
    Cogs are not prioritized in any way other than the fact that they are launched, typically, from the 0th to the 7th, in order, unless you suggest otherwise when launching them.
    There is no interaction cog-to-cog built-in... any desired interaction is created and directed by your program.· All cogs have immediate access to any and all 32 I/O pins at any moment in time.· All cogs have immediate access to the 32-bit System Counter at any time.· Main Memory and configuration system-level configuration registers are available to one cog at a time, in a time-sliced, round-robin fashion, to prevent read/write collisions on elemental items.

    rockin_rick said...
    How many max MIPS can an individual cog run? Is it 20 MIPS as 'unofficially' stated in a previous post?
    Each cog can run at 20 MIPS max.· All cogs run at the same speed as each other, but only those that you request to run actually run and consume power... all others don't even receive a clock pulse until the moment they are launched by a program.
    rockin_rick said...
    How many clock ticks per cycle?

    How many clock cycles does each instruction take?
    Aren't both of these the same question?· Please clarify if I misunderstood.
    Most instructions take 4 clock cycles, including those that access a cog's private memory.· The "hub operation" instructions, those that require mutually-exclusive access to resources such as main memory, requires 7 to 22 clocks, depending on where in time that cog's hub access window occurs in relation to the moment the instruction was reached.· Once "synced" to the hub, you can execute a hub instruction in 7 clocks, then two non-hub instructions and another hub instruction, etc.·in a period of 23 clocks total.· Conditional branches take 4 or 8 clocks, depending on if it jumps or not.
    rockin_rick said...
    Are there any future plans for a scaled back (and lower priced) propeller chip, say with only 4 or 2 cogs? I'd guess that the bulk of the use of the propeller would be with less than 8 cogs....
    We have a number of options we're considering, but I cannot release that information at this time.· Thank you for the suggestion.

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    --Jeff Martin

    · Sr. Software Engineer
    · Parallax, Inc.
  • ElectronegativityElectronegativity Posts: 311
    edited 2006-02-20 - 16:29:42
    Hi GadgetMan.

    Here is the link tho the SX20/28 data sheet on Parralax's web site:

    www.parallax.com/dl/docs/prod/datast/SX20AC-SX28AC-Data-v1.01.pdf

    The specific information is on page 4.

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    I wonder if this wire is hot...
  • Jeff MartinJeff Martin Posts: 610
    edited 2006-02-20 - 16:41:28
    ToneDefJam said...
    I think I read that each cog is identical so that would imply each cog can start/stop another.
    Exactly.
    ToneDefJam said...

    So if each cog gets 2k bytes of ram/instruction space and the instructions are 32 bits then that gives you 512 instructions per cog. That is like having 8 sx28 chips in one package in a way.
    Yes, but a bit like "... apples and oranges."· The Propeller Assembly and underlying hardware is MUCH more powerful than that of the SX, so in many cases, similar operations on the Propeller take less code than the same on the SX.
    ToneDefJam said...

    I say this because since the cog instruction space seems to be shared with the data space, this says that self modifying code is possible.
    Absolutely, in fact there are a few Propeller Assembly instructions meant specifically for this purpose.
    ToneDefJam said...

    Thinking about it, you could partition the code in a way that it could overlay a part of the cog ram so you could swap in different routines from global ram, effectively expanding the local cog ram up to the limit of 32k with paging techniques.

    I think that the sky is the limit here. I get really frustrated with chips that lock you into using the chip only one way. This chip really seems to let you be creative like no other before.
    Yes.· There's a programmer working on such schemes right now.
    We love the·idea of general purpose·devices·and trying not to limit creativity where it doesn't need to be.· There are creative uses for this architecture that we haven't even thought of yet.
    ToneDefJam said...

    This chip seems to be what the industry needs. A cpu in the standard sense but with on the fly configuration capabilities. A bridge if you will. Use it a a· mega controller or morph it into something new.
    I bet if you ask, 'can it do this?' or 'can it do that?', that the answer would boil down to, it can if you program it that way.
    Thank you!· We do too.·
    You completely hit it on the head... "if you program it that way" is the what the usual answer boils down to.
    ToneDefJam said...

    As far as size goes, 9mm/9mm would almost fit in my toothbrush so I guess it would fit in a cell phone. Besides, I'm sure a custom version could be created with less IO pins if the customer needed.
    8 processors, not 8 threads but 8 processors. This chip is going to rock the controller world and set a new standard for future controllers.
    Right, 8 processors; means multi-processing... not just multi-tasking as we've all been limited to before.

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    --Jeff Martin

    · Sr. Software Engineer
    · Parallax, Inc.
  • Jeff MartinJeff Martin Posts: 610
    edited 2006-02-20 - 16:44:06
    KenLem said...
    Am I correct in stating that there is no analog or flash on the propreller?

    Correct.· It boots up from external EEPROM, then runs entirely from fast internal RAM.· There is no analog, but there is hardware to do very fast digital operations that approach analog.

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    --Jeff Martin

    · Sr. Software Engineer
    · Parallax, Inc.
  • Jeff MartinJeff Martin Posts: 610
    edited 2006-02-20 - 16:45:05
    RoboGeek said...
    freaked.gif·50mA on each pin!?!?freaked.gif That's a total of 1.6A! Could you send me one now!burger.gif
    RoboGeek
    We have not done any testing for maximum current draw over the chip as a whole.· But we will release that information as soon as we have official figures.

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    --Jeff Martin

    · Sr. Software Engineer
    · Parallax, Inc.
  • Jeff MartinJeff Martin Posts: 610
    edited 2006-02-20 - 16:45:59
    Dave_Bell said...
    Is there a chance of posting (or a link to) a better block diagram picture?
    The gif already out there is too low res to make much sense out of...

    Dave
    On Tuesday the image you mentioned should be a link to a pdf form of the same diagram.

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    --Jeff Martin

    · Sr. Software Engineer
    · Parallax, Inc.
  • SteveWSteveW Posts: 246
    edited 2006-02-20 - 16:47:51
    >Most instructions take 4 clock cycles, including those that access a cog's private memory

    Hmm, that's quite sad - looks like the (not-)interrupt latency is going to be worse than an SX clocked hard, under most cases. That rules out a class of operation I've come to quite enjoy. It'll be interesting to see how much, if any, of that can be clawed back with the IO assistant block, whatever that turns out to be [noparse]:)[/noparse]
    (I'll stop wildly speculating when I see data...)
    (Hmm, pondering - I wonder if pipelining is made so much trickier by having combined code / data space, since you can't guarantee what code you'll be executing... My head hurts)

    Steve
  • Jeff MartinJeff Martin Posts: 610
    edited 2006-02-20 - 16:59:28
    The SX-48 and SX-28...
    We understand how it is natural to compare the Propeller to the SX chips, because that's what you're familiar with, but to be clear so no one misunderstands:

    The Propeller chip was designed totally from scratch, at the transistor level, as a·unique design.··It is not "similar" to an SX chip either in design, function, size, cost,·current draw, power, usefulness, etc.· The Propeller chip is a completely new design born of our·own dreams of·a better controller than anything we've seen on the market.· Essentially, we wanted a tool that didn't exist, so instead of fashioning one out of other tools, we decided to build one from the ground up to meet out needs.· The Propeller chip is that tool.

    As you learn more about it, you'll see why we want to make this distinction so clearly.

    Thank you.

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    --Jeff Martin

    · Sr. Software Engineer
    · Parallax, Inc.
  • Jeff MartinJeff Martin Posts: 610
    edited 2006-02-20 - 17:06:23
    Dave_Bell said...
    The improved drawing clarifies a good bit about the internals of the Propeller, but that always leads to more questions. :{) The Cog & Hub interaction drawing is intriguing, with the distributor-like action. Does this rlate to the common data and address bus shared by all the Cogs? Presumably by the Bus Sequencer? Is there then some inherent order in which the Cogs get access to the common resources? What effect does this have on latency between Cog processes?
    Good questions, Dave.

    We think of it exactly like a distributor in a V8 engine.· Yes, it relates to the common addr/data bus; it is a conceptual drawing of how main bus access is shared between cogs.· The cogs get access from Cog 0 through Cog 7, then back to Cog 0 again.· Each Cog gets a main bus access every 16 system clocks, regardless of how many other cogs are running; completely deterministic once you're synched to the hub.

    The cogs themselves are free to do non-hub (main bus) processes simultaneously as they have direct access to their own Cog RAM (2K bytes, 512 longs), video hardware, I/O hardware, System Counter and I/O pins (32 I/O pins shared by all through gated access... no need for time-slicing there).· The overall effect leads to much more effective throughput and bandwidth than is apparent at first glance.

    Don't get hung up on main bus access timing too much; in most cases it becomes a non-issue.

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    --Jeff Martin

    · Sr. Software Engineer
    · Parallax, Inc.

    Post Edited (Jeff Martin) : 2/20/2006 6:41:02 PM GMT
  • Jeff MartinJeff Martin Posts: 610
    edited 2006-02-20 - 17:17:20
    Paul Baker said...
    Guys stop asking for diagrams, prices, release dates, commands and any other specific info on the new chip. Its clear that the Parallax staff isn't going to release them ahead when they want to. Those of us who do have the information have been asked not to divulge anything beyond vague paraphrasing of what has been provided to us. And none of us want to break our assurance to Parallax to keep the details under wraps, I for one want to be considered for future special events and wont jeprodize that by releasing info on a chip that isn't availible yet. You will find out everything you are seeking in due course, its not like you are going to be able to do anything with the information at this moment anyways. A very good reason is many of the details aren't completely set in stone and are subject to changes before release. The chip is much more like the SX than stamp in that many functions such as the video generation and other features are in user level software (akin to source code level libraries) and hence may change before the release date.

    Thank you Paul.·

    Paul, and everyone else lucky enough to attend our training last week:· I have officially received direction to tell you this: at this moment, we'd like you to feel free to share details as you have learned them about the Propeller chips and hardware·you've received.· Please share these details "in·your own words" as we can not release Parallax-written documentation at this time.· Paraphrasing is allowed and recommended while·copying and pasting anything other than small items (not entire sentences) is not.· If you have any concerns about something you'd like to share, feel free to contact me directly beforehand.

    Everyone, we will release additional details as soon as we feel they are solid and we have the time (to take away from development issues) to post it.·

    Here's more details we can release now:· Release date for the Propeller chip:· April '06.· Pricing is still to be determined.





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    --Jeff Martin

    · Sr. Software Engineer
    · Parallax, Inc.
  • Jeff MartinJeff Martin Posts: 610
    edited 2006-02-20 - 17:24:57
    SteveW said...
    >Most instructions take 4 clock cycles, including those that access a cog's private memory

    Hmm, that's quite sad - looks like the (not-)interrupt latency is going to be worse than an SX clocked hard, under most cases. That rules out a class of operation I've come to quite enjoy. It'll be interesting to see how much, if any, of that can be clawed back with the IO assistant block, whatever that turns out to be [noparse]:)[/noparse]
    (I'll stop wildly speculating when I see data...)
    (Hmm, pondering - I wonder if pipelining is made so much trickier by having combined code / data space, since you can't guarantee what code you'll be executing... My head hurts)

    Steve
    Don't jump to conclusions about this... for one thing, there are 8 cogs (processors), thats ~20 MIPS * 8 = ~ 160 MIPS.· Another thing, the Propeller Assembly has very powerful features we have not seen in any other that greatly shortens many routines... comparing it to an SX literally is like comparing apples and oranges, there's very little that can be compared in equivelant terms.

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    --Jeff Martin

    · Sr. Software Engineer
    · Parallax, Inc.
  • Dave_BellDave_Bell Posts: 11
    edited 2006-02-20 - 17:25:33
    Jeff Martin said...
    Each Cog gets a main bus access every system clocks, regardless of how many other cogs are running

    Lost a number or somehting in there, but it sounds like the "distributor" runs at a constant rate, so the COGs receive central access at the same time, regardless of whether other are launched.

    Dave
  • GadgetmanGadgetman Posts: 2,436
    edited 2006-02-20 - 17:51:16
    Jeff Martin said...


    Here's more details we can release now: Release date for the Propeller chip: April '06. Pricing is still to be determined.

    Hallelujah!

    And in a curious coincidence, that's when I finally expect to have some leeway on my budget again...
    (Well, I was thinking of maybe buying a used moped then, but needs are needs, and the car doesn't use that much gas, really... )

    It boots from EEPROM?
    Can it be connected to any pin?
    (I can't see any pins dedicated to this function in the pictures in the catalog)
    Or is that from Internal ROM?


    AAAGH!!!
    Too little detail, too many questions..
    And the answers we're getting only leads to new questions...

    Maybe Pandora's box would have been a better name for it?
    It's certainly about to bring chaos to the world of hobbyists...
    (Pros, too)
    smile.gif

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    Don't visit my new website...
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