The link-- you are calculating power at 5V? Rather than just the 1.8V core rail?
So you've the regulator losses, and the VIO switching 3.3V rail I assume, feeding your results? Maybe your IO fets are active?
ignore if I've miss-understood that thread. It's long so I skipped over it!
@M1k3y said:
If that's the flexcc compiler, I already tried it. It sadly turned out to be very limited and missing a lot of C functionalities.
What C functionality is it missing? It should implement pretty much all of C99. If you meant "C++ functionalities" then yeah, it's really just a C compiler with a few C++ extensions bolted on.
I'll have to check later, but I think I was trying to pass a pointer or array to a function and the compiler did not like it. However the code has changed a lot since I switched to the p2llvm so I'll have to try and reproduce what I did before.
@evanh said:
I'm unsure if there is even a spec for the thermal resistance of the exposed pad.
>
…..
Maximum junction temperature TJ max : 150°C
Thermal resistance θJA : 20.6 °C/watt (°C/W)
θJC (to the pad ) will be much lower than that, but the total final resistance is highly dependent on the PCB cooling copper layers and area.
OnSemi will have chosen some representative copper layers/area for that spec.
As far as I can tell, there is no temperature sensor in the p2, but the pins have a huge amount of resistors in them that can be used in various configurations and there are also the DACs that are (if I'm not mistaken) located in the COGs. If someone knows how those resistors are made in silicon (so we can find their thermal coefficient) it might be possible to use them as a way to measure the temperature of the actual die. It's probably useless in measuring the thermal conductivity of the part.
All I/O circuits, including the DACs, are located in the outer custom "pad ring" that runs around the full outside perimeter of the die. There is a linking group of 17 signals, including CLK, for each pin, between the custom pad ring and the synthesised core logic. 13 of these are the M[12:0] pin mode bits as documented in the hardware/silicon manuals.
Wow, that's a huge infodump right there. I had found the block diagram of the pins before, but that is much more detailed information than I had ever hoped for. It also comes at the perfect time as I'm also trying to wrap my head around some of the more complex Pin modes.
Thought you might like it.
I wish there was even more there, TBH. Many of the links were added a long time after the data was first posted on the forums. We certainly didn't didn't keep track of everything.
It might be possible to measure temperature using the ESD protection diodes. Has anyone done this? The P2 ADCs can measure beyond the rails, -0.825 to 4.125 volts according to my calculations. Not sure if this needs a proper constant current source or if a bias resistor will work. An easy way to test this would be to hook up a multimeter, positive to the pin, and negative to 3.3v. Use the diode check function.
Should be valid, in theory, but signal might be obscured a lot. Between the ADC's sore low frequency noisiness and the VIO lift from the pull-up, it'll probably be hard to see.
Heh, I wonder if the RevB Prop2 would have an advantage here. That can have twin ADCs sampling the same pin.
@SaucySoliton said:
It might be possible to measure temperature using the ESD protection diodes. Has anyone done this? The P2 ADCs can measure beyond the rails, -0.825 to 4.125 volts according to my calculations. Not sure if this needs a proper constant current source or if a bias resistor will work. An easy way to test this would be to hook up a multimeter, positive to the pin, and negative to 3.3v. Use the diode check function.
You could measure the body diodes, of an unused 'off' port MOSFETS, which you can do with a multimeter as the diode range injects a current. My meter says ~ 610mV
To self-measure would need a small injection current outside the rails, which could come from a battery + resistor.
Comments
The link-- you are calculating power at 5V? Rather than just the 1.8V core rail?
So you've the regulator losses, and the VIO switching 3.3V rail I assume, feeding your results? Maybe your IO fets are active?
You're probably right about the regulator losses. I don't remember accommodating that. I/O was nothing really, maybe 50 mW.
60 - 5.5 * 0.9 * 20.6 = -42. So the heatsink at -40 degC should work.
What C functionality is it missing? It should implement pretty much all of C99. If you meant "C++ functionalities" then yeah, it's really just a C compiler with a few C++ extensions bolted on.
I'll have to check later, but I think I was trying to pass a pointer or array to a function and the compiler did not like it. However the code has changed a lot since I switched to the p2llvm so I'll have to try and reproduce what I did before.
θJC (to the pad ) will be much lower than that, but the total final resistance is highly dependent on the PCB cooling copper layers and area.
OnSemi will have chosen some representative copper layers/area for that spec.
Thank you JMG. I wasn't confident to say anything myself.
So we really want the thermal resistance just to the exposed pad alone.
I just had an idea for checking the thermals.
As far as I can tell, there is no temperature sensor in the p2, but the pins have a huge amount of resistors in them that can be used in various configurations and there are also the DACs that are (if I'm not mistaken) located in the COGs. If someone knows how those resistors are made in silicon (so we can find their thermal coefficient) it might be possible to use them as a way to measure the temperature of the actual die. It's probably useless in measuring the thermal conductivity of the part.
Here's some handy links. The ADC schematic is the relevant one - https://forums.parallax.com/discussion/comment/1479568/#Comment_1479568
All I/O circuits, including the DACs, are located in the outer custom "pad ring" that runs around the full outside perimeter of the die. There is a linking group of 17 signals, including CLK, for each pin, between the custom pad ring and the synthesised core logic. 13 of these are the M[12:0] pin mode bits as documented in the hardware/silicon manuals.
Here's a block diagram of the pin and smartpin connections - https://forums.parallax.com/discussion/171420/smartpin-diagram/p1
Here's a floorplan of the die with just the pad ring:
And a GDS file of the same:
Wow, that's a huge infodump right there. I had found the block diagram of the pins before, but that is much more detailed information than I had ever hoped for. It also comes at the perfect time as I'm also trying to wrap my head around some of the more complex Pin modes.
Thought you might like it.
I wish there was even more there, TBH. Many of the links were added a long time after the data was first posted on the forums. We certainly didn't didn't keep track of everything.
It might be possible to measure temperature using the ESD protection diodes. Has anyone done this? The P2 ADCs can measure beyond the rails, -0.825 to 4.125 volts according to my calculations. Not sure if this needs a proper constant current source or if a bias resistor will work. An easy way to test this would be to hook up a multimeter, positive to the pin, and negative to 3.3v. Use the diode check function.
Should be valid, in theory, but signal might be obscured a lot. Between the ADC's sore low frequency noisiness and the VIO lift from the pull-up, it'll probably be hard to see.
Heh, I wonder if the RevB Prop2 would have an advantage here. That can have twin ADCs sampling the same pin.
You could measure the body diodes, of an unused 'off' port MOSFETS, which you can do with a multimeter as the diode range injects a current. My meter says ~ 610mV
To self-measure would need a small injection current outside the rails, which could come from a battery + resistor.