Improved ADC Pin Techniques - Page 3 — Parallax Forums

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• Posts: 15,049
edited 2023-12-04 16:50

@"Christof Eb." said:
What is the size of these capacitors "C"? As far as I understand, this together with R=450k gives the answer to the question, how long you have to wait after switching the input?

Full circuit is attached, but not that simple sorry. Far above my skill level, real ADC hardware uses a current balancing circuit in between the front end resistors and the modulated capacitor. Here's the capacitor pair. I can make out 10 x 10 = 100 um gate area on each. 3.3 Volt transistor means a thicker dielectric I guess. No idea what Wtot means.

• Posts: 1,073

@evanh said:

@"Christof Eb." said:
What is the size of these capacitors "C"? As far as I understand, this together with R=450k gives the answer to the question, how long you have to wait after switching the input?

Full circuit is attached, but not that simple sorry. Far above my skill level, real ADC hardware uses a current balancing circuit in between the front end resistors and the modulated capacitor. Here's the capacitor pair. I can make out 10 x 10 = 100 um gate area on each. 3.3 Volt transistor means a thicker dielectric I guess. No idea what Wtot means.

Thank you, evanh!

@cgracey what absolute value in mV do you get, when you connect a pin directly to GND with you new method?
I did some measurements and had the impression, that not noise but the absolute error is the bigger problem?

• Posts: 14,124
edited 2023-12-05 11:38

@"Christof Eb." said:

@evanh said:

@"Christof Eb." said:
What is the size of these capacitors "C"? As far as I understand, this together with R=450k gives the answer to the question, how long you have to wait after switching the input?

Full circuit is attached, but not that simple sorry. Far above my skill level, real ADC hardware uses a current balancing circuit in between the front end resistors and the modulated capacitor. Here's the capacitor pair. I can make out 10 x 10 = 100 um gate area on each. 3.3 Volt transistor means a thicker dielectric I guess. No idea what Wtot means.

Thank you, evanh!

@cgracey what absolute value in mV do you get, when you connect a pin directly to GND with you new method?
I did some measurements and had the impression, that not noise but the absolute error is the bigger problem?

Yes, the absolute errors at GND and VIO are the biggest problems. I should have designed the ADC differently, so that the same high-z resistor was used for GIO, VIO, and pin measurement. Instead, I have three separate matched resistors that differ more than I thought they would. So, I've seen pins that are as much as 15mV off. The only way to overcome that error is if you are able to drive the pin low (which can be done when using the ADC) and overcome the analog input signal, forcing the pin very close to GND and then measuring it. Same could be done for VIO by driving it high.

To answer the cap question, the 3p3v gate capacitors have a capacitance of 4.4 fF / um2. So, for eight (m=8) 10um x 10um gate caps, that's 3520 fF (4.4 fF * 8 * 10 * 10). Because we have both PMOS and NMOS cap sets for power supply noise rejection, double that to get 7040 fF or about 7 pF. That's not much, but consider that the circuit was designed to run at 200 MHz.

• Posts: 14,124
edited 2023-12-05 13:05

I found a way to make a time-halving, resolution-doubling N-stage filter that takes almost no memory and a constant amount of time to operate. It outputs 17 stages of samples, from the raw base sample to the average of 64K samples.

Here are WHEN the stages are computed for up to stage 7, but the stages could be infinitely higher:

```00000000000000000000000000000000000000000000000000000000000000000
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2   2   2   2   2   2   2   2   2   2   2   2   2   2   2   2
3       3       3       3       3       3       3       3
4               4               4               4
5                               5
6
7
```

Stage 0 is the ADC sample that is generated each period.
Stage 1 is the sum of two Stage 0 samples. It is generated every second period.
Stage 2 is the sum of two Stage 1 samples. It is generated every fourth period.
Stage 3 is the sum of two Stage 2 samples. It is generated every eighth period.
etc.

I found a way to pick which stage needs to be computed each period by reversing the bits in an incrementing counter, taking the magnitude via ENCOD, then subtracting it from 32.

Each time a stage executes, it outputs a sample by right-shifting its stored value by its stage number.

The idea is that you don't need to specify a sample rate and quality. You just pick the sample stream that gives the best tradeoff between rate and resolution. The ADC is running full speed all the time, generating fast low-res samples.

Here is the code for it, along with the ADC and DAC generator for testing.

• Posts: 13,721

@"Christof Eb." said:

This drawing is helpful to understand how it works...

I see it as a current measuring circuit... There is a current coming into to ADC from the voltage applied to the pin, through one of for resistors.
Then, there is current coming from the digital circuit through the 300 kOhm resistor. The digital circuit works to cancel out the input current with it's output current to maintain VIO/2 voltage where they meet.

I think the first of those four buffers in series is more like a voltage comparator than a buffer. Giving 0 if above VIO/2 and 1 if below VIO/2...

So, if one wanted to measure a much higher voltage, could just add an extra series resistor between voltage to be measured and pin.
As long as that resistance was bigger than say, 10k, the protection diodes should keep chip save when ADC is off...
But, probably need to look into spec for how much current protection diodes can take to be sure it's OK...

• Posts: 15,049
edited 2023-12-06 00:28

@Rayman said:
So, if one wanted to measure a much higher voltage, could just add an extra series resistor between voltage to be measured and pin.

Totally, it's a good solution. Maybe throw in a high frequency capacitor from the pin to GIO to absorb spikes.

The ADC electrically centres on VIO/2 so you have to accept that there is an offset. But it's a fixed value voltage and at large voltage ranges the lopsided current becomes insignificant.

• Posts: 15,140

@Rayman said:

So, if one wanted to measure a much higher voltage, could just add an extra series resistor between voltage to be measured and pin.

On paper, yes.
In practice the on chip resistors have a tempco that should be matched by that external R.

• Posts: 15,049
edited 2023-12-06 23:17

Could use the x100 setting for a smaller internal resistor so that the external resistor completely dominates. With internal 5 kOhm, a 50 MOhm to handle up to 500 Volts peak would make any small difference in the coefficients well below noise floor.

PS: That functional drawing was made years before Chip released the full schematic. The 4k5R to 450kR was a pure guess on my part originally. The real x1 resistors are over 500 kOhms.

• Posts: 14,124

@evanh said:
Could use the x100 setting for a smaller internal resistor so that the external resistor completely dominates. With internal 5 kOhm, a 50 MOhm to handle up to 500 Volts peak would make any small difference in the coefficients well below noise floor.

PS: That functional drawing was made years before Chip released the full schematic. The 4k5R to 450kR was a pure guess on my part originally. The real x1 resistors are over 500 kOhms.

The pin will bias itself somewhere around VIO/2, but not exactly at VIO/2. So, the amplified modes (ie 100x) need to be allowed to go to their center voltage, because the full range may be as little as 50mV peak-peak around that center voltage. You would want a huge series resistor (megohms) in that case. For AC signals, just a series capacitor is sufficient, since it will allow the DC to settle where it wants, but will convey voltage changes.

• Posts: 15,049

Oops, you reminded me, 50 MOhm makes 500 V peak-peak, so only 250 V peak.

• Posts: 15,049
edited 2023-12-07 00:01

Talking about high voltages. I once was given instruction to wipe clean a electronic vacuum valve in a plastic welding machine that was used for manufacturing waterbeds. The DC bus was some thousands of volts. It had a lot of series diodes in the rectifier! The valve wouldn't have fit inside a kitchen oven.

Anyway the circuit breaker had been tripping so my instructions was turn it all off and just carefully use some meths and a rag to clean the whole glass surface of this valve. Ensure it was dry before powering up again.

Voila, it worked a dream. The operators were blasting them sheets of plastic no problem. Gave me the willies to be honest.

• Posts: 5,113

@cgracey said:
I found a way to make a time-halving, resolution-doubling N-stage filter that takes almost no memory and a constant amount of time to operate. It outputs 17 stages of samples, from the raw base sample to the average of 64K samples.

The idea is that you don't need to specify a sample rate and quality. You just pick the sample stream that gives the best tradeoff between rate and resolution. The ADC is running full speed all the time, generating fast low-res samples.

If you can dedicate a COG this seems a rather useful way to generate clean/filtered analog results at whatever sample rate you need. I've not messed about with ADCs and DACs on the P2 as yet so having something like this is pretty handy.

With 6 IO pins needed it might be good to build a 2 channel ADC P2 breakout board that leverages this concept. You could put a voltage reference on it for calibration, and you might be able to use the two spare pins in an 8 bit group with an i2c expander to control an analog input mux or FETs to switch in series resistors and capacitors for voltage range extending or AC coupling or to select the voltage reference. Or to keep it simpler, maybe these 2 spare IO pins could just be 2 DAC channel outputs. This could then become a simple 2 channel analog IO P2 breakout with a nominal 0-3.3V voltage range that also has the extra headroom to detect under/over voltage conditions. Might be good to add some bulkier input protection in that case to help protect P2 inputs.

• Posts: 14,124

@rogloh said:

@cgracey said:
I found a way to make a time-halving, resolution-doubling N-stage filter that takes almost no memory and a constant amount of time to operate. It outputs 17 stages of samples, from the raw base sample to the average of 64K samples.

The idea is that you don't need to specify a sample rate and quality. You just pick the sample stream that gives the best tradeoff between rate and resolution. The ADC is running full speed all the time, generating fast low-res samples.

If you can dedicate a COG this seems a rather useful way to generate clean/filtered analog results at whatever sample rate you need. I've not messed about with ADCs and DACs on the P2 as yet so having something like this is pretty handy.

With 6 IO pins needed it might be good to build a 2 channel ADC P2 breakout board that leverages this concept. You could put a voltage reference on it for calibration, and you might be able to use the two spare pins in an 8 bit group with an i2c expander to control an analog input mux or FETs to switch in series resistors and capacitors for voltage range extending or AC coupling or to select the voltage reference. Or to keep it simpler, maybe these 2 spare IO pins could just be 2 DAC channel outputs. This could then become a simple 2 channel analog IO P2 breakout with a nominal 0-3.3V voltage range that also has the extra headroom to detect under/over voltage conditions. Might be good to add some bulkier input protection in that case to help protect P2 inputs.

A board like that would be nice.

I started breaking apart the sections of code needed to perform each step of the ADC conversion, in order to make a configurable system that could handle any number of ADCs. When I started putting the state code around it, it got really ugly. Then I had a realization that there was a better way to do it. I could make a bytecode interpreter that could contain all the needed code, kind of like the Spin2 interpreter. Then, rather than put all this stateful code around the core ADC code sections, I could just call them out via bytecodes with very little memory and execution overhead. Plus, configuration becomes super flexible this way.

• Posts: 1,073

@cgracey said:

@rogloh said:

@cgracey said:
I found a way to make a time-halving, resolution-doubling N-stage filter that takes almost no memory and a constant amount of time to operate. It outputs 17 stages of samples, from the raw base sample to the average of 64K samples.

The idea is that you don't need to specify a sample rate and quality. You just pick the sample stream that gives the best tradeoff between rate and resolution. The ADC is running full speed all the time, generating fast low-res samples.

If you can dedicate a COG this seems a rather useful way to generate clean/filtered analog results at whatever sample rate you need. I've not messed about with ADCs and DACs on the P2 as yet so having something like this is pretty handy.

With 6 IO pins needed it might be good to build a 2 channel ADC P2 breakout board that leverages this concept. You could put a voltage reference on it for calibration, and you might be able to use the two spare pins in an 8 bit group with an i2c expander to control an analog input mux or FETs to switch in series resistors and capacitors for voltage range extending or AC coupling or to select the voltage reference. Or to keep it simpler, maybe these 2 spare IO pins could just be 2 DAC channel outputs. This could then become a simple 2 channel analog IO P2 breakout with a nominal 0-3.3V voltage range that also has the extra headroom to detect under/over voltage conditions. Might be good to add some bulkier input protection in that case to help protect P2 inputs.

A board like that would be nice.

I started breaking apart the sections of code needed to perform each step of the ADC conversion, in order to make a configurable system that could handle any number of ADCs. When I started putting the state code around it, it got really ugly. Then I had a realization that there was a better way to do it. I could make a bytecode interpreter that could contain all the needed code, kind of like the Spin2 interpreter. Then, rather than put all this stateful code around the core ADC code sections, I could just call them out via bytecodes with very little memory and execution overhead. Plus, configuration becomes super flexible this way.

Sounds like doing it with Forth....

• Posts: 14,124
edited 2023-12-14 00:55

Here is my current working file on ADC stuff with a bunch of ideas in comments. Martin Montague on the Propeller Live Forum today wanted me to post this. It requires PNut_v43 to run.

• Posts: 1,748
edited 2023-12-28 11:41

@cgracey
chip,
Can the single Pin version be modified to run two adc channels at the same time or should it be run in two cogs?
Jim

• Posts: 14,124

Eight ADC pins at once with bytecode interpreter.

• Posts: 13,721

@cgracey Is there supposed to be a plot in the scope window? Mine is blank. Just see what looks like text values for the ADCs in the regular debug window....

• Posts: 14,124

@Rayman said:
@cgracey Is there supposed to be a plot in the scope window? Mine is blank. Just see what looks like text values for the ADCs in the regular debug window....

Ah, I think it's because you'll need the latest version of PNut and I'm not sure if it's in PropellerTool, yet.

I added an auto-scale function to the SCOPE mode that will confuse older versions of DEBUG.