Definitions p2
pilot0315
Posts: 913
in Propeller 2
I have been struggling to read through all of the documentation about the P2.
First is there a more defined "dictionary" of the commands and what do they do in a more simple explanation of what they really mean and what they do?
Example:
WRPIN # D # S SP
WXPIN # D # S SP
WYPIN # D # S SP
SETDACS # D
What is the X and the Y? I know that they are acronyms but what are the long version of the acronyms mean.
Thank you in advance.
Martin
Comments
The smartpins are very flexible but also a bit complex...
Maybe the Hardware Manual describes them best?
https://www.parallax.com/propeller-2/documentation/
Anyway, the main command is "WRPIN" for Write Pin, which sets the main mode.
X and Y are parameters of the main mode, set by WXPIN and WYPIN.
SETDACS is to set the Digital to Analog Converters (DACS).
This is a normally unrelated thing, but probably connected in some cases...
The three instructions load the smartpin's three write-only registers:
There is also one read-only data register in each smartpin. RDPIN is used to get its data. This one is named Z.
SETDACS is a little oddball. Thrown in as a bonus because it was easy to add I suspect. SETDACS writes to the streamer's four DAC data pipes when the streamer isn't doing so. But it's generally easier to just use a WRPIN instead for simple setting of a DAC.
There can be naming confusion in the docs also with the low level pin A/B verses smartpin A/B inputs. I've personally been separating the naming with SmartA/SmartB and PinA/PinB (or APin/BPin). This helps me keep them distinct in my source code.
Rayman uses my naming here - https://forums.parallax.com/discussion/171420/smartpin-diagram-now-with-p-p-bit-mode-table/p1
He updated the chart again on last page - https://forums.parallax.com/discussion/comment/1530931/#Comment_1530931
WRPIN's mode register performs many jobs:
The low-level %DDDDDDDD bit-field acts as a DAC databus and is optionally piped from any streamer/cog without using the smartpin.
PS: There is a number of possible combinations that are not available due to limit of 32 mode bits in WRPIN.
@evanh
@Rayman
Thanks I will study these and try to tease out the examples. I am presently trying to understand the pwm routines.
Martin
Keep in mind that the PWM smart pins sub-divide the X register into two elements. I think it's easier to start with the sawtooth version. Sawtooth and Triangle have to do with the behavior of an internal counter, and nothing to do with the shape of the output waveform. Both will give a variable duty-cycle, fixed-frequency square wave. This is from the docs
The X register setup is tricky at first. X.word[1] (high 16 bits) is the number of units in your PWM period. I do a lot of LED control and use 255 here because DMX lighting control uses 0 to 255 for 0 to 100%. You could make things easy and have 1% resolution by setting X.word[1] to 100. The lower 16 bits of X tell the P2 how many system ticks are in one of your units at your desired PWM frequency. This is calculated by dividing your system clock frequency by your desired PWM frequency (e.g., 20kHz), and then dividing that by the units in 100%. Once you have that sorted and the smart pin is running, changing the Y register will change the PWM duty cycle. Keep in mind that your ticks/unit value (X.word[1]) must fit into 16 bits, so this can have an affect on your low side of your PWM frequency. For very low frequencies you'll want to use high ticks/units and high units values.
In Spin, I do this:
...where hz is my target PWM frequency, units is the 100% value, and duty is the initial PWM setting. The PWM smart pin has an internal counter that goes from 1 to your 100% setting. If your duty value is at or above this counter, the output is high. As soon as the counter value goes past your duty setting, the output goes low. Graphically, it looks like this:
In Triangle mode, the counter counts down and then back up, which will cut your PWM frequency in half with the same X register settings. In my Spin driver when Triangle mode is specified, I make this adjustment to keep the PWM frequency matched to the value passed to the start method:
Dividing the ticks/unit value by 2 would double the frequency in Sawtooth mode; in Triangle mode (witch doubles the output) this adjustment keeps the target PWM frequency.
Here's a dirt-simple example of making a slow (0.5Hz) LED blinker with a duty cycle of 0 (off) to 100%. Note how I had to scale the units and duty (x 100) to get the ticks/unit value to fit into 16 bits while running a 200MHz.
Remember, if you want to use wypin() to set the duty cycle of this blinker, that value must be scaled into the range of 0..100_00 to get the expected results.
This exercise got me thinking about how slow one could go. The highest ticks/unit setting is $FFFF, and the highest units setting is $FFFF. For me, the PWM frequency works out to be 200_000_000 / ($FFFF * $FFFF) which is 0.04656Hz, which is a period of 21.474 seconds. I knocked together this bit of code to verify:
wrpin(55, P_PLUS1_A) ' use P55 to watch P56 state := pinread(55) ' get initial state pinstart(56, P_OE | P_PWM_SAWTOOTH, $FFFF_FFFF, $7FFF) ' very slow pwm on P56 t0 := getms() ' start timing repeat ' report ms between states if (pinread(55) <> state) t1 := getms() term.fstr1(@"State change at: %dms\r", t1-t0) t0 := t1 state := state ^ 1Confirmed. Time between state changes is 10.737 seconds.
A few minutes later...
Changing the PWM mode to triangle doubles the PWM period.
@JonTitus
Howdy.
Where is "here". The link does not work for me. Maybe it is me.
Rayman sent me to this document.
This is a line from it:
You may download all software examples in this section from the URL here...
On page one.
Thanks in advance.
Martin.
I still have a question about PWM/DAC 16bit via dithering.
Right now I have a trade-off between PWM frequency and resolution (normal).
Is dithering some form of trickery where I can achieve 16 bit resolution at a higher frequency?
Craig
Yes - you get higher frequencies at the expense of more noise, even somewhat at lower frequencies.
Random mode does what's called noise shaping: instead of all the frequency content above the Nyquist rate being a 1/256 triangle wave (noise), plus maybe a little bit of your signal with aliasing if you try feeding it samples too quickly, it "spreads out" the Nyquist rate, letting you control the frequency content at higher frequencies in a meaningful, but still noisy, way, at the expense of more noise in frequencies below the original Nyquist rate.
@Electrodude
Not sure if that is a yes/no/maybe
Craig
If you need the higher frequencies and don't mind reduced resolution at the extra frequencies and more noise in frequencies near the previous limit, it's a yes. Read up on "noise shaping" - this should be the first-order kind. I edited my previous post a few times - sorry.
@JohnnyMac,
Thank you! I thought I understood these, but your walkthrough made the details much clearer. (Especially the functions of the words in X) I haven't needed PWM from the P2 yet, But now I MUST go try it..
After my recent experience using the "Duty Mode" in the Prop1 counters, which is also known as Pulse Density Modulation, I get the feeling Chip probably should have used that instead of PWM dithering in the Prop2.
I hadn't twigged just how much better PDM is for DACs until I saw it in action. The modulation frequency ramps up in mid voltage thereby keeping the ripple very low. PWM gets noisy in this region - needing larger smoothing capacitor which slows response.
Now that you say it, yeah. PDM also has the advantage that it doesn't have a sample period. The target value can be changed at any time without glitches. PWM-dithered DAC only works quite right if the period is a multiple of 256 cycles.
On P1 I think the DAC quality is limited by the fact that the modulator is behind all these gates (OR with OUTA/other counter/video, AND with DIRA, OR with up to 7 other cogs), which seem to distort the signal (rise/fall time difference?). There are noticable artifacts when the cog running the DAC is behind more of these. I guess if they were clocked gates that wouldn't be an issue, but they aren't (PLL/video hardware says hello).
This is for my multi-axis motion controller and admittedly, from a practical standpoint, I'm being a bit silly but I have the data sheets on all of the "big player" products and darn-it, I want to meet or exceed their specifications just to prove that the P2 is the ultimate solution.
The only stickler is that one product has a 16-bit, filtered PWM, 10v / -10v at something in excess of 30KHz.
Kinda moot, actually because AFAIK, The ADC input of pretty much every servo amplifier resolves to 12-bit.
This is a PID output that is constantly updated @ 1/2/4/8 KHz to regulate motor velocity....even a "real" DAC appears crazy noisy in this application.
I guess, when all's said and done, we're dealing with a LPF that is the motor itself.
Craig
Would someone please tell me what the DIR means. Is this similar to DIRA?
Thanks.
INSTART(PinField, Mode, Xval, Yval) Start PinField smart pin(s): DIR=0, then WRPIN=Mode, WXPIN=Xval, WYPIN=Yval, then DIR=1
PINCLEAR(PinField) Clear PinField smart pin(s): DIR=0, then WRPIN=0
Each logic level pin has three internal logic signals: An IN signal, an OUT signal, and a DIR signal.
IN always shows the level of the pin.
When DIR is high, the pin is driven with the level of OUT.
INA contains 32 bits for the first 32 of those pins.
OUTA contains 32 bits for the same 32 pins.
DIRA contains 32 bits for the same 32 pins.
Yes, in normal mode. But in smart mode the three signals have diferent meanings. Please refer to the section "Smart pins" in the silicon docs:
DIR enables the smartpin. When DIR is low, the smartpin (Dark-red box in attached diagram) is held in reset state. Further reading - https://forums.parallax.com/discussion/171420/smartpin-diagram/p1
When smartpin is configured, then
P_OEbit (%TT=01) of pin mode performs the DIR control for the pin itself.