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P2 for readout the HAMAMATSU S13774 linear image sensor — Parallax Forums

P2 for readout the HAMAMATSU S13774 linear image sensor

Can I use the P2 for readout the HAMAMATSU S13774 linear image sensor. Does anyone have experience ?

Comments

  • evanhevanh Posts: 13,106

    The video stream is 32-bit (after converting to single-ended) x 180 MHz. I think its needs are a tad on the high-end side of things.

  • evanhevanh Posts: 13,106

    The 180 MHz PCLK is mastered from the S13774. That will be a struggle also. Prop2 doesn't have true synchronous I/O. It generally relies on being the master clock source so the slave then runs synchronous. There has been success with a 50 MHz external mastering clock that worked by the Prop2 oversampling at 150 MHz but that was only a couple of smartpins in serial mode. The I/O can do it but 32 of them will just swamp the Prop2.

  • Tanks for you comment!!!

  • RaymanRayman Posts: 12,650
    edited 2022-06-15 16:36

    Looks like the 30 MHz master clock is an input to the chip.

    Maybe run p2 at 180 MHz and use streamer to input?

    Don’t know if that would work or not…
    Maybe better if p2 and sensor both driven by some 30 MHz clock source?

    The P2 could generate the 30 MHz clock, but not sure that'd be good enough...

  • YanomaniYanomani Posts: 1,419
    edited 2022-06-15 15:02

    After taking a closer look at these sensors datasheet, they seem to be a "little" more complex than I initially supposed...

    Internally, they have 16-pairs of single-ended "column" serializer-channels (A[1:0] thru P[1:0]), and each element of a pair is responsible for sending-out 6 bits, so each "pixel" has 12 bit of information, which exactly matches the maximum number of possible detectable "levels" at the "low-speed"-mode (25 klines/S).

    The "high-speed"-mode (100 klines/S) seems to use just the topmost ten bits of each 12-bit-long "sample-word".

    Each internal pair is output as two LVDS-differential-pairs, thus a total of 64 lanes that must be converted back to 32 single-ended Lvcmos signals, just to be received (@ SDR-180 MHz or DDR-90 MHz).

    Just to complete the "bunch", 256 sampled "pixels" are sent thru each of the 16-internal pairs, for a total of 4096 "pixels" per frame.

    Ouch... :smile:

    P.S. Detail: the above talk is just about pixel data; there are also other signals to be considered (clocks, pixel-data-sync, frame-sync. ...)...

  • RaymanRayman Posts: 12,650

    There's probably a quad LVDS receiver chip you'd have to use.

    I've used SN65LVDS32PW, but it looks to only be good up to 100 or maybe 150 mbps...

  • evanhevanh Posts: 13,106
    edited 2022-06-15 21:38

    @Rayman said:
    Looks like the 30 MHz master clock is an input to the chip.
    Maybe run p2 at 180 MHz and use streamer to input?

    True, that'll likely work for the I/O. S13774 will have PLL for 6 x 30 MHz.

    However, resulting serial-as-parallel data arrangement in hubRAM would then need processing power of all Cogs just to deinterleave it fast enough.

    Pixel rate is 16 x 30 MHz = 480 MP/s, so 60 MP/s per cog, so three sysclock ticks per pixel for deinterleaving ... that ain't gonna work.

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