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P1V on ULX3S FPGA board -> It works! — Parallax Forums

P1V on ULX3S FPGA board -> It works!

RaymanRayman Posts: 12,366
edited 2021-12-24 19:38 in Propeller 1

By chance, has anybody gotten the P1V to work on a ULX3S FPGA?

Seems I missed the boat when P1V was first here, ~5 years ago...

I'm starting from this repo:

Think I have the FTDI chip connected to virtual P30, P31 and reset, but no luck getting it to identify with Prop Tool yet...

Update: See post #15 for working design files. See Post #20 for a better version.


  • RaymanRayman Posts: 12,366

    Got it to Identify with Prop Tool today. But, only in ~1 out of every 8 tries...

    Also, brought program counter of cog up to the top level, so I could see what it was doing...
    Added this code to the top of rambooter for testing:

    PUB x
    DAT                     org
                            mov     dira,#$FF
                            add     outa,#1
                            test    mask_rx,ina     wc
            if_nc           jmp     #start
                            jmp     #noboot

    Then, from View Info in Prop tool added the binary to rambooter.hex and could see what it is doing...
    The port A I/O is also brought out to the ULX3S header, so I could verify what the cog was doing.

    Seems what I was missing was the bit of code that stretches the DTR reset signal.
    After adding that was when I first got it to identify.

    But, something must still be wrong for it to only occasionally identify.
    Was also able to load a program, but it didn't run... Guess that's next on the agenda...

  • RaymanRayman Posts: 12,366
    edited 2021-12-11 22:34

    Here's my current project files.
    It identifies to Prop Tool, but only occasionally.
    It loads RAM from Prop Tool occasionally also, but doesn't run for some reason.

    Think one could preload the cogs with what you want and maybe preload HUB too.
    Might try that soon if can't get load RAM from Prop Tool to work...

    ULX3S.v is the top file. There is a project file here for Lattice Diamond.
    Using the LSE synthesis tool.

    The program counter is mostly attached to the LEDs although LED7 is the reset signal and LED6 is cog clock.
    Main clock is rigged with PLL via Clarity Designer (the .sbx file) for 200 MHz.
    This gives the cog a 12.5 MHz frequency.
    Maybe this needs to be adjusted to be recognized better by Prop Tool.

    It does give a timing error message. Not sure if that has anything to do with the problems though...

    Update: Something is very wrong with the design... When I switched the hub memory files back to the original, it doesn't work right...
    But, I don't think HUB memory is involved in the Prop Tool Identify process, so it doesn't make sense...
    Think it might be the ~160 MHz PLL clock that is the problem... Think just need 12.5 MHz cog clock to identify...
    Or, maybe 12.5 MHz and 25 MHz...

  • Cluso99Cluso99 Posts: 18,037

    The fpga versions for P2 only ran at 80MHz. Cannot recall the P1V speeds.

  • RaymanRayman Posts: 12,366

    I tried rigging the clock so that it stays always at 12.5 MHz, but same result...

    It's a bit frustrating to troubleshoot when it takes so long to synthesize...

    I think @rogloh got it working on a ECP5, so I have hope it can work for me too...

  • Do you have an EEPROM that you could hook up? EEPROM boot doesn't rely on any particular timing.

  • @Rayman said:
    I tried rigging the clock so that it stays always at 12.5 MHz, but same result...

    It's a bit frustrating to troubleshoot when it takes so long to synthesize...

    I think @rogloh got it working on a ECP5, so I have hope it can work for me too...

    Yes I was able to get it working on an ECP5 so it is doable. It's been ages since I looked at any P1V stuff so not sure I'd be of much help right now. Maybe your HUB memory files being changed to the original changed the encryption. Remember that the original P1 ROM is "encrypted" with some XOR thing. This got stripped out in some versions of the Verilog code and the ROM code could be in the clear. Maybe by running original ROM it is now incompatible with the P1V...not sure but just a thought.

  • RaymanRayman Posts: 12,366
    edited 2021-12-17 22:55

    Ok, I decided to dig up the DE0-nano as there are existing projects for that.
    What I'm seeing is that the Parallax version works, but the SaucySoliton version doesn't work.

    The project from here:
    Won't compile out of the box with Quartus. It seems the feature settings in features.v do not get to the lower level Verilog files. But, I just put an include "features.v" in these files and then it compiles. But, it isn't recognized by Prop Tool.
    Maybe I just don't know what I'm doing, but it looks like something has become broke there.

    Anyway, I'll start over now from the Parallax version and see if that will run on ULX3S.

    No luck so far..
    But, I found a version from Cluso that works with Quartus Lite and DE0-nano:

    Found some old fpga source for P123 V9. This still works.
    But, reducing HUB RAM and/or preloading cog RAM the SaucySoliton way doesn't work. Not sure why yet...

  • RaymanRayman Posts: 12,366

    Ok, think I've figured out that for some reason (that I don't understand) reducing hub ram and/or preloading cog ram no longer works.

    The @SaucySoliton way (commented out below) doesn't run tiny loaded programs. I don't get it...

    // 8192 x 32 ram with byte-write enables ($0000..$7FFF)  // <=- hub ram size (32k)
    // *RJA This was original way
    reg [7:0] ram3 [8191:0];  // <=- hub ram size (32k)
    reg [7:0] ram2 [8191:0];  // <=- hub ram size (32k)
    reg [7:0] ram1 [8191:0];  // <=- hub ram size (32k)
    reg [7:0] ram0 [8191:0];  // <=- hub ram size (32k)
    // * / 
    //RJA This is featured way
    reg [7:0] ram3 [HUB_RAM_KL*1024-1:0];
    reg [7:0] ram2 [HUB_RAM_KL*1024-1:0];
    reg [7:0] ram1 [HUB_RAM_KL*1024-1:0];
    reg [7:0] ram0 [HUB_RAM_KL*1024-1:0];
  • RaymanRayman Posts: 12,366
    edited 2021-12-19 00:26

    Finally some success with P123 board with all Verilog files.

    Figured out that couldn't load from Prop Tool when memory was <32k because the memory check was failing.
    I think it must checksum all of hub ram and not having all of it was messing that up.
    Fixed that by adding some if statements in hub_mem.v so nothing gets written to non-existing ram and reads from non-existing ram give zeros, like this:

    always @(posedge clk_cog)
    if (a[12:0]<HUB_RAM_KL*1024-1)
        if (ena_bus && !rom && w && wb[3])  // <=- rom/ram decode
            ram3[a[12:0]] <= d[31:24];  // <=- rom/ram decode
        if (ena_bus && !rom)  // <=- rom/ram decode
            if (a[12:0]<HUB_RAM_KL*1024-1)
            ram_q3 <= ram3[a[12:0]];  // <=- rom/ram decode
              ram_q3 <= 0;

    Also figured out that the cogledtest.spin was failing because it was trying to start cogs with stack space that doesn't exist.
    Fixed that like this:

      long stack[8*40]
    pub Start | i
      repeat i from 1 to 1'7
        coginit(i, donothing, @stack + i * 40)
        waitcnt(10_000_000 + cnt)
      repeat i from 1 to 1'7
      waitcnt(10_000_000 + cnt)

    So, think now have all Verilog source (although some system verilog may still be there) with variable cogs and variable hub ram.
    Next, want to get the @SaucySoliton variable ROM working with this.
    I'm starting to think the @SaucySoliton github repo only works with preloaded hum ram (and not via Prop Tool), but might be wrong...

  • AribaAriba Posts: 2,567

    What size of ECP5 has your ULX3S ? Can you not implement the full 64kB HubRAM?


  • RaymanRayman Posts: 12,366

    @ariba I've just got the 12k... But, I'm also interested in making it small so it might fit on a Xyloni.

    Think I have all the @SaucySoliton features working in this version for the P123 board with Quartus 21.1.0.
    Except for preloading cog ram. Preloading hub ram may or may not be working, but doesn't matter if can't preload cog ram.
    I think something must have changed between Quartus 15 and Quartus 21 that broke it.

    Anyway, at least there is now this version that works with Prop Tool.

  • RaymanRayman Posts: 12,366

    Uh oh, seems the "improvements" I made to hub_mem.v actually made the design too big to fit in DE0-nano.

    It seems those extra "if" statements cause the logical element usage to balloon.

    Seems need to find another way to use less hub memory...

  • RaymanRayman Posts: 12,366
    edited 2021-12-20 15:45

    Think finally have version on DE0-nano that has variable cogs, variable hub ram, and variable hub rom.
    Runs up to 80 MHz and works with Prop Tool. Works with Quartus Prime 21.1

    With 2 cogs, 2 kB hub RAM, and minimal ROM, uses on 4,532 of 22,320 LEs and 131,072 of 608,256 memory bits.
    This should allow it to also work easily on ECP5 of ULX3S (.
    Should also work on this low cost Xyloni board.

    Took me a while to get hum_mem.v working with less than 32 kB of RAM in a way that works and doesn't use a bunch of LEs to do it.

  • RaymanRayman Posts: 12,366
    edited 2021-12-23 20:48

    Finally got it working on ULX3S!
    Design files attached. Needs some cleaning up, but works.

    After reading forum posts from @Ariba and @rogloh realized that I needed to start from the Pipistrello version here:

    But, it was too big to fit into my 12F version of ULX3S.
    So, went back to the DE0-nano and got this working with less hub ram and fewer cogs.
    Took that back to ULX3S and it works, finally!

    There is a timing error message window that pops up during place and route, but telling it to continue flow and it seems to work.
    Seems to only work with LSE synthesis tool. Just tried with Synplify and it didn't work...

  • AribaAriba Posts: 2,567

    @Rayman said:
    After reading forum posts from @Ariba and @rogloh realized that I needed to start from the Pipistrello version ...

    Sorry, I thought you know this, and the SaucySoliton version was based on that.

    What is your reason to deal with the P1V again?
    I thought the P1V might be a solution for the unavailable P1 (Q44), but then I saw that the ECP5s are also unavailable.

    The T8 FPGA in the Xyloni is a bit small, especially the RAM. With 12 kByte Block RAM you don't get very far.


  • RaymanRayman Posts: 12,366
    edited 2021-12-23 00:41

    Interesting... Maybe I'll do WinDiff to see why my SaucySoliton version doesn't work...

    I'm just taking some time to learn FPGA. This seemed like a good thing to get feet wet with...

    The Trion FPGAs are interesting as the sorta free tool works with all their chips.
    Xyloni seemed a good way to check it out.
    Plus, it's just $35.

    It looks like 2 cogs and a bit of hub ram with fit easily.

    The ULX3S board is nice for learning because there are a ton of examples...
    Seems sold out for now, but more on the way...

  • RaymanRayman Posts: 12,366

    Also, from what I'm seeing, people generally want some kind of soft core in their designs.
    Looks like RISC-V is popular for bigger chips and Lattice has IP for an 8-bit.
    Nice because they come with IDE's and compiler chains.

    I guess I'm wondering how P1V matches up with RISC-V or the others...

  • RaymanRayman Posts: 12,366

    Another nice thing about ULX3S is that you don't need a prop plug and you can program RAM or flash via the USB port.

    I'm looking at the Xyloni board and don't see a way to do that as they don't bring out DTR or RTS anywhere.
    Not seeing a way to use FTProg to make it work either...

  • RaymanRayman Posts: 12,366
    edited 2021-12-24 17:04

    Reading some more from the old ECP5 P1V thread, changed clock select scheme.
    Now, limited to just RCFast and PLL16X.

    It now compiles with both LSE and Synplify. Still gives a timing error message in both, but seems to work anyway.
    Also, added in PortB option and option to omit video and counters in features.v.

  • RaymanRayman Posts: 12,366

    Next, want to see if can preload HUB RAM from hex files created from a Prop Tool binary output file.

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