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P1v Experiments — Parallax Forums

P1v Experiments

David BetzDavid Betz Posts: 14,511
in Propeller 1
I'm finally finding time to play with the FPGA boards I've accumulated over the years and would like to get P1v working on either a BeMicro CV board or a DE0-Nano. Does anyone have a recommendation as to which would be the best? Also, is there a concise description of how to setup either board for P1v. I have the docs for the boards but I'm not sure where to find the most current Verilog sources for P1v that will run on each board.

Thanks!
David

Comments

  • David BetzDavid Betz Posts: 14,511
    I found Heater's repository: https://github.com/ZiCog/P8X32A_Emulation

    That includes builds for the DE0-Nano and the DE2-115. I guess I'll use the DE0-Nano for now.
  • mindrobotsmindrobots Posts: 6,506
    David, in github, look for jacgoudsmit/p1v repo, it has latest for all boards as far as I know.
  • David BetzDavid Betz Posts: 14,511
    mindrobots wrote: »
    David, in github, look for jacgoudsmit/p1v repo, it has latest for all boards as far as I know.
    Thanks for the pointer!

  • David BetzDavid Betz Posts: 14,511
    I installed Quartus Prime Lite Edition on a Windows 10 VM and am trying to build P1v for the DE0-Nano from the jacgoudsmit/p1v repo. I followed the instructions in the DE0-Nano readme file but I got an error during the "Convert Programming Files" step. When I select DE0-Nano.cof I get an error saying that Quartus can't find DE0-Nano.sof. Where do I find that file?

    Also, has anyone had luck running Quartus under a VirtualBox VM? It seems very slow when I do it and I'm running on a fairly fast i7 desktop machine with 32gb of RAM.
  • Cluso99Cluso99 Posts: 18,069
    David,
    Do you have the P1V-master.zip file?

    Here is my last version of my clean test. It has all the various ROM codes so you can include what you need. There are all the original update fixes but IIRC there is nothing else added. It was working with Quartus 15.



    zip
    zip
    CleanTest14_20150512h.zip
    507K
  • David BetzDavid Betz Posts: 14,511
    I was successful at building Heater's DE0-Nano repository. It took 35 minutes on my Windows 10 VM. Is that an expected time? Also, it produced lots of warnings: 
    Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Warning (12125): Using design file top.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
	Info (12023): Found entity 1: top
	Info (12023): Found entity 1: top
Warning (12125): Using design file tim.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
	Info (12023): Found entity 1: tim
	Info (12023): Found entity 1: tim
Warning (12125): Using design file dig.v, which is not specified as a design file for the current project, but contains definitions for 8 design units and 8 entities in project
	Info (12023): Found entity 1: cog_ram
	Info (12023): Found entity 2: cog_alu
	Info (12023): Found entity 3: cog_ctr
	Info (12023): Found entity 4: cog_vid
	Info (12023): Found entity 5: cog
	Info (12023): Found entity 6: hub_mem
	Info (12023): Found entity 7: hub
	Info (12023): Found entity 8: dig
	Info (12023): Found entity 1: cog_ram
	Info (12023): Found entity 2: cog_alu
	Info (12023): Found entity 3: cog_ctr
	Info (12023): Found entity 4: cog_vid
	Info (12023): Found entity 5: cog
	Info (12023): Found entity 6: hub_mem
	Info (12023): Found entity 7: hub
	Info (12023): Found entity 8: dig
Warning (276027): Inferred dual-clock RAM node "dig:core|cog:coggen[0].cog_|cog_ram:cog_ram_|altsyncram:r[0][31]__1" from synchronous design logic.  The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design.
Warning (10858): Verilog HDL warning at hub_mem.v(85): object rom_low used but never assigned
Warning (10036): Verilog HDL or VHDL warning at hub_mem.v(87): object "rom_low_q" assigned a value but never read
Warning (10858): Verilog HDL warning at hub_mem.v(96): object rom_high used but never assigned
Warning (19016): Clock multiplexers are found and protected
	Warning (19017): Found clock multiplexer dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|Mux6
	Warning (19017): Found clock multiplexer dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|Mux6
	Warning (19017): Found clock multiplexer dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|Mux6
	Warning (19017): Found clock multiplexer dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|Mux6
	Warning (19017): Found clock multiplexer dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|Mux6
	Warning (19017): Found clock multiplexer dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|Mux6
	Warning (19017): Found clock multiplexer dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|Mux6
	Warning (19017): Found clock multiplexer dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|Mux6
	Warning (19017): Found clock multiplexer dig:core|cog:coggen[7].cog_|cog_ctr:cog_ctra|Mux6
	Warning (19017): Found clock multiplexer dig:core|cog:coggen[6].cog_|cog_ctr:cog_ctra|Mux6
	Warning (19017): Found clock multiplexer dig:core|cog:coggen[5].cog_|cog_ctr:cog_ctra|Mux6
	Warning (19017): Found clock multiplexer dig:core|cog:coggen[4].cog_|cog_ctr:cog_ctra|Mux6
	Warning (19017): Found clock multiplexer dig:core|cog:coggen[3].cog_|cog_ctr:cog_ctra|Mux6
	Warning (19017): Found clock multiplexer dig:core|cog:coggen[2].cog_|cog_ctr:cog_ctra|Mux6
	Warning (19017): Found clock multiplexer dig:core|cog:coggen[1].cog_|cog_ctr:cog_ctra|Mux6
	Warning (19017): Found clock multiplexer dig:core|cog:coggen[0].cog_|cog_ctr:cog_ctra|Mux6
Warning (19016): Clock multiplexers are found and protected
	Warning (19017): Found clock multiplexer tim:clkgen|clk_pll~2
	Warning (19017): Found clock multiplexer tim:clkgen|clk_pll~2
Warning (276020): Inferred RAM node "dig:core|hub:hub_|hub_mem:hub_mem_|ram0_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
Warning (276020): Inferred RAM node "dig:core|hub:hub_|hub_mem:hub_mem_|ram3_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
Warning (276020): Inferred RAM node "dig:core|hub:hub_|hub_mem:hub_mem_|ram2_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
Warning (276020): Inferred RAM node "dig:core|hub:hub_|hub_mem:hub_mem_|ram1_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
Warning (113015): Width of data items in "hub_rom_high.hex" is greater than the memory width. Wrapping data items to subsequent addresses. Found 512 warnings, reporting 10
	Warning (113009): Data at line (1) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
	Warning (113009): Data at line (2) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
	Warning (113009): Data at line (3) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
	Warning (113009): Data at line (4) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
	Warning (113009): Data at line (5) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
	Warning (113009): Data at line (6) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
	Warning (113009): Data at line (7) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
	Warning (113009): Data at line (8) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
	Warning (113009): Data at line (9) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
	Warning (113009): Data at line (10) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
	Warning (113009): Data at line (1) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
	Warning (113009): Data at line (2) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
	Warning (113009): Data at line (3) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
	Warning (113009): Data at line (4) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
	Warning (113009): Data at line (5) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
	Warning (113009): Data at line (6) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
	Warning (113009): Data at line (7) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
	Warning (113009): Data at line (8) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
	Warning (113009): Data at line (9) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
	Warning (113009): Data at line (10) of memory initialization file "hub_rom_high.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
  • David BetzDavid Betz Posts: 14,511
    warnings continued... 
    Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Critical Warning (332012): Synopsys Design Constraints File file not found: 'top.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Warning (169177): 34 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
	Info (169178): Pin io[0] uses I/O standard 3.3-V LVCMOS at J14
	Info (169178): Pin io[1] uses I/O standard 3.3-V LVCMOS at J13
	Info (169178): Pin io[2] uses I/O standard 3.3-V LVCMOS at K15
	Info (169178): Pin io[3] uses I/O standard 3.3-V LVCMOS at J16
	Info (169178): Pin io[4] uses I/O standard 3.3-V LVCMOS at L13
	Info (169178): Pin io[5] uses I/O standard 3.3-V LVCMOS at M10
	Info (169178): Pin io[6] uses I/O standard 3.3-V LVCMOS at N14
	Info (169178): Pin io[7] uses I/O standard 3.3-V LVCMOS at L14
	Info (169178): Pin io[8] uses I/O standard 3.3-V LVCMOS at P14
	Info (169178): Pin io[9] uses I/O standard 3.3-V LVCMOS at N15
	Info (169178): Pin io[10] uses I/O standard 3.3-V LVCMOS at N16
	Info (169178): Pin io[11] uses I/O standard 3.3-V LVCMOS at R14
	Info (169178): Pin io[12] uses I/O standard 3.3-V LVCMOS at P16
	Info (169178): Pin io[13] uses I/O standard 3.3-V LVCMOS at P15
	Info (169178): Pin io[14] uses I/O standard 3.3-V LVCMOS at L15
	Info (169178): Pin io[15] uses I/O standard 3.3-V LVCMOS at R16
	Info (169178): Pin io[16] uses I/O standard 3.3-V LVCMOS at K16
	Info (169178): Pin io[17] uses I/O standard 3.3-V LVCMOS at L16
	Info (169178): Pin io[18] uses I/O standard 3.3-V LVCMOS at N11
	Info (169178): Pin io[19] uses I/O standard 3.3-V LVCMOS at N9
	Info (169178): Pin io[20] uses I/O standard 3.3-V LVCMOS at P9
	Info (169178): Pin io[21] uses I/O standard 3.3-V LVCMOS at N12
	Info (169178): Pin io[22] uses I/O standard 3.3-V LVCMOS at R10
	Info (169178): Pin io[23] uses I/O standard 3.3-V LVCMOS at P11
	Info (169178): Pin io[24] uses I/O standard 3.3-V LVCMOS at R11
	Info (169178): Pin io[25] uses I/O standard 3.3-V LVCMOS at T10
	Info (169178): Pin io[26] uses I/O standard 3.3-V LVCMOS at T11
	Info (169178): Pin io[27] uses I/O standard 3.3-V LVCMOS at R12
	Info (169178): Pin io[28] uses I/O standard 3.3-V LVCMOS at T12
	Info (169178): Pin io[29] uses I/O standard 3.3-V LVCMOS at R13
	Info (169178): Pin io[30] uses I/O standard 3.3-V LVCMOS at B11
	Info (169178): Pin io[31] uses I/O standard 3.3-V LVCMOS at E10
	Info (169178): Pin inp_resn uses I/O standard 3.3-V LVCMOS at D9
	Info (169178): Pin clock_50 uses I/O standard 3.3-V LVCMOS at R8
	Info (169178): Pin io[0] uses I/O standard 3.3-V LVCMOS at J14
	Info (169178): Pin io[1] uses I/O standard 3.3-V LVCMOS at J13
	Info (169178): Pin io[2] uses I/O standard 3.3-V LVCMOS at K15
	Info (169178): Pin io[3] uses I/O standard 3.3-V LVCMOS at J16
	Info (169178): Pin io[4] uses I/O standard 3.3-V LVCMOS at L13
	Info (169178): Pin io[5] uses I/O standard 3.3-V LVCMOS at M10
	Info (169178): Pin io[6] uses I/O standard 3.3-V LVCMOS at N14
	Info (169178): Pin io[7] uses I/O standard 3.3-V LVCMOS at L14
	Info (169178): Pin io[8] uses I/O standard 3.3-V LVCMOS at P14
	Info (169178): Pin io[9] uses I/O standard 3.3-V LVCMOS at N15
	Info (169178): Pin io[10] uses I/O standard 3.3-V LVCMOS at N16
	Info (169178): Pin io[11] uses I/O standard 3.3-V LVCMOS at R14
	Info (169178): Pin io[12] uses I/O standard 3.3-V LVCMOS at P16
	Info (169178): Pin io[13] uses I/O standard 3.3-V LVCMOS at P15
	Info (169178): Pin io[14] uses I/O standard 3.3-V LVCMOS at L15
	Info (169178): Pin io[15] uses I/O standard 3.3-V LVCMOS at R16
	Info (169178): Pin io[16] uses I/O standard 3.3-V LVCMOS at K16
	Info (169178): Pin io[17] uses I/O standard 3.3-V LVCMOS at L16
	Info (169178): Pin io[18] uses I/O standard 3.3-V LVCMOS at N11
	Info (169178): Pin io[19] uses I/O standard 3.3-V LVCMOS at N9
	Info (169178): Pin io[20] uses I/O standard 3.3-V LVCMOS at P9
	Info (169178): Pin io[21] uses I/O standard 3.3-V LVCMOS at N12
	Info (169178): Pin io[22] uses I/O standard 3.3-V LVCMOS at R10
	Info (169178): Pin io[23] uses I/O standard 3.3-V LVCMOS at P11
	Info (169178): Pin io[24] uses I/O standard 3.3-V LVCMOS at R11
	Info (169178): Pin io[25] uses I/O standard 3.3-V LVCMOS at T10
	Info (169178): Pin io[26] uses I/O standard 3.3-V LVCMOS at T11
	Info (169178): Pin io[27] uses I/O standard 3.3-V LVCMOS at R12
	Info (169178): Pin io[28] uses I/O standard 3.3-V LVCMOS at T12
	Info (169178): Pin io[29] uses I/O standard 3.3-V LVCMOS at R13
	Info (169178): Pin io[30] uses I/O standard 3.3-V LVCMOS at B11
	Info (169178): Pin io[31] uses I/O standard 3.3-V LVCMOS at E10
	Info (169178): Pin inp_resn uses I/O standard 3.3-V LVCMOS at D9
	Info (169178): Pin clock_50 uses I/O standard 3.3-V LVCMOS at R8
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'top.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (332148): Timing requirements not met
	Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
	Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Critical Warning (332148): Timing requirements not met
	Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
	Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Critical Warning (332148): Timing requirements not met
	Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
	Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
  • Cluso99Cluso99 Posts: 18,069
    Yes, there are a number of errors. I tried to solve a number of them, trying to get a clean compile.
    I don't recall how long it took to compile. If you enable sending info Quartus works faster.
  • jac_goudsmitjac_goudsmit Posts: 418
    edited 2016-08-01 23:01
    David Betz wrote: »
    I found Heater's repository: https://github.com/ZiCog/P8X32A_Emulation

    That includes builds for the DE0-Nano and the DE2-115. I guess I'll use the DE0-Nano for now.

    This is the old repo from before the time that Parallax created their own P1V repo. My branch in that repo has a number of improvements including the possibility to compile it for Spartan (I haven't tested this myself) but it's not "sanctioned" by Parallax and it's pretty much abandoned now that Parallax has a repo.
    mindrobots wrote: »
    David, in github, look for jacgoudsmit/p1v repo, it has latest for all boards as far as I know.

    This is the most recent P1V repo. The exact URL is https://github.com/jacgoudsmit/P1V.

    The master branch in that repo is closest to what Parallax put online, but I don't work in that branch anymore because I've moved further and further away from the original Parallax directory structure: I combined the source code for all targets into one directory, and instead of having small variations (e.g. to change the ROM emulation on the DE0-Nano) are now done with conditional expressions and a super-top-module that has all the hardware specific stuff in it such as DIP switches and LEDs. There is now a "rel" branch that has the most stable version, and the "dev" branch which has the latest and greatest features. That includes builds for the BeMicroCV-A9 and the FPGA1-2-3 boards from Parallax. If you're just trying stuff out with P1V and aren't planning on making any changes to the P1V sources, the best place to work is probably the "rel" branch (which is the default). If you want to make a small change, use the "dev" branch or create your own after you fork the project.

    Unfortunately I haven't had time for this project for a while, and not all the features from the old repo have been ported to the new repo. For example, the Xilinx targets haven't been ported yet (though the AHDL modules have been replaced by Verilog modules to make this easier), and the P1V repo still has the scrambled Spin interpreter whereas the old P8X32A_Emulation repo has the option of using a descrambled Spin ROM image.

    ===Jac
  • David BetzDavid Betz Posts: 14,511
    edited 2016-07-14 02:20
    Thanks for your comments. I'd like to think I will eventually be able to make at least small changes but right now I'm just trying to get a build environment setup. I've downloaded Quartus Prime 16.0 Lite Edition. Should that work with your jacdev repo?
  • David BetzDavid Betz Posts: 14,511
    I tried the "jacdev" branch and I still get an error when trying to do "Convert Programming Files..." about not being able to find DE0-Nano.sof. This is using Quartus Prime Lite 16.0.
  • TrapperBobTrapperBob Posts: 139
    Make sure you select the DE0-Nano revision before compiling ?
  • David BetzDavid Betz Posts: 14,511
    TrapperBob wrote: »
    Make sure you select the DE0-Nano revision before compiling ?
    I thought that is what the "Convert Programming Files..." step was supposed to do. I selected that and then chose the DE0-Nano file. Shouldn't that have setup for a DE0-Nano build? I'm afraid I don't understand how Quartus works very well. I would have expected a DE0-Nano "project" that I could open that would already be configured but apparently that's not how things work.

  • Cluso99Cluso99 Posts: 18,069
    David,
    Try my files that I attached a few posts back. At least I understand those files and I can retest here if you cannot get them to work for you.
  • David BetzDavid Betz Posts: 14,511
    Cluso99 wrote: »
    David,
    Try my files that I attached a few posts back. At least I understand those files and I can retest here if you cannot get them to work for you.
    I have tried those files and they do work. I'm just wondering why I can't get Jac's files to work.

  • TrapperBobTrapperBob Posts: 139
    The cof file converts the sof file into a jic file which you then use to program the serial flash memory. It does not execute a project build to create the sof file.
  • TrapperBobTrapperBob Posts: 139
    Jacs files are setup to be able to build one of many versions by revision
  • David BetzDavid Betz Posts: 14,511
    Okay but what is the sequence of steps that I need to use to get jac's repository to build for the DE0-Nano. Clearly, I must be missing a step somewhere.
  • ozpropdevozpropdev Posts: 2,791
    David
    This might help
    https://www.parallax.com/downloads/setup-propeller-1-design-de0-nano

  • ozpropdevozpropdev Posts: 2,791
    David
    To make a .jic file from your .sof file try these settings.
    cof_jic.jpg
    814 x 657 - 130K
  • jac_goudsmitjac_goudsmit Posts: 418
    edited 2016-08-02 01:03
    Sorry David, I know I need to improve the documentation.
    David Betz wrote: »
    TrapperBob wrote: »
    Make sure you select the DE0-Nano revision before compiling ?
    I thought that is what the "Convert Programming Files..." step was supposed to do. I selected that and then chose the DE0-Nano file. Shouldn't that have setup for a DE0-Nano build? I'm afraid I don't understand how Quartus works very well. I would have expected a DE0-Nano "project" that I could open that would already be configured but apparently that's not how things work.

    Quartus makes it possible to put several targets in the same project file by using "revisions". They are similar to how you can compile a Windows or Linux program in x86 mode as well as x64 mode. I reorganized the files so there are no duplicates anymore (unlike the original Parallax P1V distro), and the various targets are now built as "revisions". Quartus remembers the last selected revision when you load the .qsf file but if you downloaded the files straight from my Github, chances are that the current revision is NOT the DE0-Nano because I don't have one of those. You'll have to change the current revision to DE0-Nano before you compile.

    The steps you need to take (including selecting the Nano as target) are here. For the other targets, there is also a readme.txt in the appropriate top level directory.

    Here's a copy-paste of the DE0-Nano readme, slightly modified for clarity:
    1) Open Quartus Prime (the Free edition will work just fine, make sure you installed Cyclone IV support)
2) File | Open Project... (or Ctrl+J)
3) Select 'P1V_Altera.qpf' file from the HDL directory
3a) Click Project | Revisions, and make sure the DE0-Nano revision is the current revision. If not, click on it, then click Set Current. Click OK to close the dialog.
4) Press the 'play' button in the icon bar (or hit Ctrl+L) to start compilation of the current revision. This takes several minutes. You don't need to "Compile All", this would compile the project for all the targets (DE0-Nano, DE2-115, BeMicroCV, BeMicroCVA9 and FPGA123-A7).

5) File | Convert Programming Files
6) Click 'Open Conversion Setup Data...'
7) Select 'DE0-Nano.cof' file
8) Click 'Generate'
8a) Note, you can leave the Convert Programming File window open while doing the rest of the steps

9) Tools | Programmer
10) Connect the DE0-Nano to your PC via USB cable
11) Click 'Hardware Setup...'
12) Select 'USB-Blaster', click 'Close'
13) Set 'Mode:' to 'JTAG'
14) Click 'Delete' to clear any files or devices
15) Click 'Add File'
16) Select 'DE0-Nano.jic' file from the output_files directory
17) Check 'Program/Configure' box
18) Click 'Start' to begin programming (takes a few minutes)
18a) Note, you can leave the Programmer window open while doing the rest of the steps

19) Unplug and replug the USB cable to cycle power (loads new configuration)
20) P8X32A should now be running on DE0-Nano, indicated by a single green LED (cog0)

21) Install your Propeller Plug into the GPIO header as shown in the P8X32A_DE0_Nano.PNG file in the P8X32_DE0_Nano directory

22) You can now use the regular Propeller Tool software to talk to the P8X32A being emulated in the DE0-Nano

    If you want to tweak something and then recompile, restart at step 4.

    If you have any questions, feel free to send me a PM. I don't come here often :)

    ===Jac

    PS on my Dell Optiplex (4-core i5 at 3.1GHz with 8GB memory and an SSD, running Windows 7) the compilation of the DE0-Nano revision takes 3 minutes and 35 seconds.
  • David BetzDavid Betz Posts: 14,511
    Thanks for the detailed instructions. I'll try them out tomorrow.
  • David BetzDavid Betz Posts: 14,511
    I just tried following your instructions and they worked fine. Thanks! Now I just have to study the Verilog code enough to learn how to change it.
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