P2 ADC noise
pic18f2550
Posts: 400
Hello,
since the P2 DAC does not have a "sample and hold circuit", the question is : how does this affect the measurement result.
- what is the noise level at constant input voltage.
- what is the noise level with a symmetrical triangular input signal.
- how large is the overshoot with a rectangular input signal.
Please no dB values I need the binary value (should/actual).
Another question is in how far does the CLK affect the noise?
What also interests me is whether two ADC inputs connected in parallel interfere with each other?
Thanks.
Comments
This is the very interesting question.
The clock over 320 MHz is not recommended for ADC, although, in my experiments, I got good results even near 360 MHz.
I also tried changing clock frequency at about 190..210 MHz and differences in noise level and spectrum at different clock frequencies were easily hearable. Maybe it is the PLL jitter.
I had no time to do more experiments.
I have already calculated that the PLL has an influence on the result.
Something must be optimized here.
Blocking capacitors alone can not solve the problem.
It would be nice if you could feed 256MHz and you bypass the PLL.
Another variant would be the use of a 16/32MHz crystal. So that the CLK is a multiple of the crystal frequency.
A SigmaDelta ADC does not need a S&H. It measures the average value over the whole sample period.
It depends on the resolution, the SINC type, the sysclock, how stable the supply voltage is, and so on. Just try it with your setup.
Depends a lot on the triangle frequency vs. sysclock. For low triangle frequencies it's the same as 1.
There should be no overshoot from the ADC, maybe from wrong terminated lines with high frequencies.
There was some crosstalk on adjacent pins with the P2 rev B version, but that should be no problem anymore with rev C.
That would be a function of source resistance.
If your source impedance << P2 input ADC resistance, the current that comes out of any Adc pin, would have minimal effect.
OK.
A small input description is due.
The purpose here is what ?
To use the DAC to calibrate the ADCs and thus (mostly) factor out the static resistor miss matches ? That still leaves temperature drifts, & DAC errors too, but periodic recalibrate could help there.
You could also use the DAC to shift the bias point for signals that are more impulse than sine.
The common 47k resistors will 'fight against' the slightly different virtual zero (50% VCC) points of the ADCs, but that should be a fixed offset effect.
You could check that by connect/disconnect of the DAC circuit, at the various gains you will use, and see the zero-movement.
Hi, Barabarus PIC18F2550us,
as you have yet got no value for your first answer, I was wondering, if you already found this thread: https://forums.parallax.com/discussion/173632/what-is-the-resolution-and-the-standard-deviation-of-values-of-the-smart-pin-adc-of-p2
So I did ask a very similar question there.
After some own measurements, I think, that if you need a better resolution than ENOB=12,4bits (with gain=1) for sound data, you will need an external adc or at least an external comparator. Those 18bits given by the datasheet are some theoretical number.
The precision of the DAC seems to be at least 12bits, but I have not been able to measure this. I have doubts, if the DAC can really reach 16bits monotony, as this would need very accurate resistors.
Best regards, Christof
I haven't done any real accuracy measurements myself but I think monotony and linearity are not the problem. You should easily get 16 bit monotony and resolution. But noise is an actual problem if you want to go beyond 12-point-something bits. You have to trade bandwidth against SNR. And self-calibration with the internal VIO/GIO multiplexer is also not 100% accurate as there is some leakage or asymetry.
Check out this: https://forums.parallax.com/discussion/171255/adc-auto-calibration/p1
Audio might be more forgiving because the low frequency noise is mostly outside the audible range and offset errors don't matter. But if you need high resolution, DC accuracy and low noise all at the same time it becomes much harder.
I think somebody has done a linearity test for the ADCs of the P2. I can't remember exactly where it was but it may be found somewhere in this old, long thread: https://forums.parallax.com/discussion/169298/adc-sampling-breakthrough/p1
" I think monotony and linearity are not the problem. You should easily get 16 bit monotony and resolution." - Are you sure?
Let's assume the previous output value was %0000.0011_1111.1111 and the following output shall be %0000.0100_0000.0000. I was thinking, that you would need a very precise step size at the upper 8 bits hardware dac?
the resolution of the DAC (8Bit) does not have to be so special it only serves to keep the signal reasonably in the middle of the working range.
The low frequencies are not the problem, rather the higher ones.
I want to check two magnetic bearings for vibrations, because there is sometimes unwanted contact with the axis.
So there are 6 measured values to 18 bits.
The AC coupling will self-center for zero-average waveforms, but the DAC could be useful to do trials.
You may want to do an external bandpass amplifier, so that the ADC has more of the useful signal and less out-of-band stuff to reject.
Selection of a low noise supply regulator could help too.
What freq band are the failure signals you want to detect ?
Errr, we are talking of ADCs, not DACs here, aren't we. R-2R ladder DACs and SAR ADCs that use a R2R ladder internally suffer from that problem with the 2^n-1 to 2^n code transition. But all that has nothing to do with the P2. The ADCs in the P2 are sigma delta converters. There output is a result of counting ones and zeroes in a bitstream. All the ones have equal weight instead of powers of two. So the transition between 2^n-1 and 2^n is just one step equal to any other step between consecutive counts.
Same for DACs. The DACs in the P2 don't use R2R ladders but instead 256 255 CMOS outputs with equal series resistance to the output. If you output a number, say 127, then 127 outputs are on and 128 are off. They all have the same resistance, e.g. weight. Every value n+1 is not exactly the same distance above the previous value as the resitors have tolerances. But is is by design monotonically and quaranteed to be above the n value because one more resistor is switched to supply instead of ground.
So linearity depends on the tolerances and drift of the resistors and on the clock jitter for the ADCs. But monotonity is guaranteed by design. (Strictly speaking, as long as the LSB step size is above the noise level for very low frequencies = drift. If it's not then "higher" or "lower" makes no sense anymore)
"The DACs in the P2 don't use R2R ladders but instead 255 CMOS outputs with equal series resistance to the output."
Since the inherent noise is also reflected in the measured values, I wonder how this is reflected in the limit values.
What happens when the value becomes <0 or >$3FFFF?
We discussed this here: https://forums.parallax.com/discussion/173804/adc-sinc2-sinc3-mode-overflow-question-is-there-a-better-way#latest
For my purpose I did go back to sinc1 mode with saturation instead of overflow.
DAC raw data and curve plots here,
https://forums.parallax.com/discussion/169269/accurate-dac-reference-data-voltages-from-p2-silicon
What influence should the liearity of a DAC have on the noise level of an ADC?
The comments are not related to the topic.
Sorry.