Adc Sinc2 Sinc3 Mode Overflow Question - Is there a better way?
Christof Eb.
Posts: 1,197
in Propeller 2
.loop WAITSE1 'wait for sample period done
RDPIN x,#adcpin 'get SINC2 accumulator
SUB x,diff 'compute sample
ADD diff,x 'update diff value
SHR x,#6 'justify 8-bit sample
ZEROX x,#7 'trim 8-bit sample
'use x here 'use sample somehow
JMP #.loop 'loop for next period
x RES 1 'sample value
diff RES 1 'diff value
This is the Sinc2 code taken from P2 Documentation.
As far as I understand, due to the zerox instruction, this code leads to the effect, that if there is an overflow (which can happen with higher gain modes) the value will not saturate to a maximum but will overflow to some very wrong value. For many applications this might be a severe problem. (Imagine a temperature controller....)
So I would like to ask, if there is a better way, which saturates at maximum?
Comments
Not due to the ZEROX, but yes there is a minor numerical complication to avoid. When using a full two-to-the-N exponent for the sample/decimation period, it contains 2^N bitstream bits from the ADC. Lets say 2^4=16 bits total. If all bits are a high, then that's a value of 16. And we all now what happens to 16 in a 4-bit register - It becomes 0. The ZEROX may appear to be removing the top most bit that would let it be 16 but it's actually doing another job. At any rate, no matter how many bits there are, if you try to use a matching decimation period like that and also saturate the ADC then you've got yourself a gremlin.
Aside from not saturating, the fix is to not use X[3..0] for setting the decimation period. Use the Y register instead, and set it to a lower period. 2^N - 1 is fine.
PS: It's likely the "sinc2 sampling" mode also has this gremlin. Since it can only do full exponent sampling periods. I haven't tested myself.
Maybe that's another improvement tweak to make to future designs of Prop2+. Update the quick to set 2^N periods to be 2^N - 1 instead.
Thanks for that input!
At least this method "Use the Y register instead, and set it to a lower period. 2^N - 1 is fine." should be included into the "hardware manual"!
At the moment I did go back to Sinc2 Sampling. With this mode there is saturation as far as I have seen.
If there is a Prop2+, I think it should be made cheaper: Prop2-. Sinc2 filter and Sinc3 filter mode seem to be senseless at this moment for me. Also I have "discovered" the skip and skipf instructions, which can be replaced by jmp and jmprel. And there is mul16, which can be replaced by cordic multiply. ....
You need Sinc3 filtering for good audio quality (18bit/384 kHz). Sync2 filter allows an exact sampling rate, outside 2^n clocks, can be important if you need o sample in sync to generated signal (PWM for example).
You seem not to undestand the skip/f instructions.
MUL16 (and SCA/S) execute in 2 clocks, while cordic needs more than 50. The fast multiplier is the key to many DSP applications, like music synthesis.
I also want a cheaper P2, but these small details will not make a big difference. We need a smaller P2 with fewer cogs, RAM and pins. There was once a plan for a whole P2 family. The current P2 is too big for most commercial applications.
My suggestion: 2 Cogs, 64kB Hubram, TQFP32 with 16+ Smartpins. The reduced chip size should allow a price of 3...4$.
A speculative plan but yeah, finances permitting, there is intent to expand the offerings - https://forums.parallax.com/discussion/164364/prop2-family/p1
Hi,
if you know a way to achieve 18bits for audio with P2 in reality, I would be interested very very much! Unfortunately my measurements did not show at all, that this is in reach. Enob was 12,4 bits. Not a bit better than Sinc2 Sampling. But if you have done it, I would be thankful.
Yes I think, do understand skip. If you want to shrink that chip, you must sacrify things. Pins, cogs, instructions,....
As long as you are not near the maximum sampling period you should be able to just allow another bit through the mask.
The sinc filter full scale values are N^2 for sinc2 and N^3 for sinc3 (before shifting.) The maximum period for sinc3 with aliasing is 511. For sinc2 it might be 11585, unless there are fewer bits in the sinc2 accumulator than sinc3.
It looks like you want 8 bit samples.
That means a period of 128 clocks.
128^2 = 16384 saturated value after differentiation
16384>>6 = 256 after shift
256 & 255 = 0 after mask
If you really need 8 bit samples, I suppose you could use FLE to saturate it at 255 after masking with 511.
Reducing the period to 127 will give
127^2 = 16129 saturated value after differentiation
16129>>6 = 252 after shift
252 & 255 = 252 after mask
All of this is the result of reducing the smart pin logic to the bare minimum. The sinc3 accumulator is 27 bits IIRC. Things would be easier if we had all 32 bit registers.
What I have done is to sample a music signal with the 18bit ADC, reduce it to 16bit and output it on another pin with a 16bit DAC, which I then hear on an earphone. No measurement, only my ears and they say there is no noise hearable, and the music is clear and clean.
Chip also said that the input circuit is good for about 13bits, but I'm not sure if this is also the case for dynamic signals, like music.
And also if you really don't get more bits with Sinc3, you get it at a much higher samplerate, and can further filter it. This alone improves the quality. With Sinc2 and 14 bits you only get about 25 kHz sample frequency.
"As long as you are not near the maximum sampling period you should be able to just allow another bit through the mask. "
Thank you for this hint! I had just copied the original code from the P2 Hardware Manual here.
Such Information should be included into the P2 Hardware Manual! Will you put in there?
https://docs.google.com/document/d/1MzLdvV8c1CYtyF3HwI5PZyOBhlxJAD9MHPGZuCCLzCE/edit
I did this also. Audio in->ADC (Sinc3)->DAC->audio out.
The quality is acceptable (no noise hearable on speakers in the normal environment) but using a good earphones I did notice the noise immediately. The real SNR is something between 60 and 70 dB - 11-12 bits. Good enough for everyday stuff as the best SNR on analog cassette tapes (without Dolby or DBX) is less than 60 dB and the theoretical best SNR on vinyl records is 75 dB if new and produced using DMM - but not audiophile kind of hi-fi.
After all experiments I did I think it is analog circuit noise before ADC input or introduced by ADC itself. I think so, because any trick I tried, which should work, didn't work at all - it works as if the noise is present in the input signal.
If Chip does do another die layout for a smaller package, then that is an opportunity for another shot at improving the ADC. Also, a nice feature of making changes in this area is it has no config/software changes so would be fully backwards compatible.