Unused 3.3V VIO pins
JRoark
Posts: 1,215
in Propeller 2
I am REALLY boxed into a corner on a controller design using the P2. I cant increase the size of the board as it is a hard limit, and I cant stack anything. I’ve spent the day on my 4th reroute and came to the realization that there are several groups of pins that are unneeded. Can I get by without having to supply 3.3V power to these unused groups? If 3.3Visnt needed, do I have to ground them or can I float them (preferred, saves traces and space)?
Thoughts?
Comments
Can you add more layers ?
If the pins really are not needed, you could route 3v3 and skip those decoupling caps, which are what consume the most PCB space anyway.
The Rev.A eval board would tell you if that works or not... There were jumpers for the power.
But, the manual says this:
To use the smart pins in each pin group, power must be provided to the center pin, Vxxxx, for
that group. The voltage selection headers provide a convenient way to connect the power
source by attaching a shunt-jumper in either of the positions shown.
I'd take that to mean that if you don't need the pins, you don't need to apply power
Only two of the eight VIO supply pins are required to be connected for powering up - Opposite corners: V2831 (for the clock circuits), and V6063 (for the reset and boot I/O circuits). All others are optional and only needed if the associated I/O group is to be used.
Is the layout really "crowded" to a point those "unused" VIOs can't be connected to VDD, at least?
Perhaps it's only my POV, but, there is the "Old Good Times" rule of totally avoiding any unconnected (unbiased) pins when dealing with Cmos logic (even if you need to resort to "ugly" wire-jumpers, or tiny smt 0-Ohm resistors, used as such).
The "then-faked" (1.8V) VIOs-fed pins will not react/switch at any meaningful/useful speeds or even have waranted waveforms, but they'll also won't be turned into "wild antennas", ready to catch any surounding noise, feeding it right thru into sensible silicon areas.
Any zapping event can ever be worsened by exposing high-impedance, unbiased cmos structures.
If possible, and in order to avoid unnecessary rf-pickup, include at least one extra .01 uF ceramic capacitor per such consecutively-grouped VIOs.
Just one last advice: in operation, just after any Reset, ensure all other unused pins are forcefully biased towards GND, even thru resorting to the configurable 150 kOhms pull-down resistors.
Be happy!
Henrique
After doing some Googling and considering the posts above, I’m inclined to ground the unused VIO 3.3V and the unused pins. Its a straight shot from the pins to the ground plane / heat sink on the P2 and it shouldnt draw any additional power. Workable? Or is there something in the pins/smartpins that would cause an issue with this workaround?
Refering to the Rev.A eval board schematic, there are two 4.7 uF x 6.3V and one 1 uF x 25V capacitors per VIO pin, even in case all the corresponding option jumpers are out, so their effective series AC resistance to GND is very near zero. No positive bias, but still ensures not any bigger zapping can find its way thru.
What are your boards outer dimensions, can you post your artwork?
I really wish I could, but cant for all the usual reasons.
The board is irregular shaped but basically it can be enclosed by a 80x120 mm rectangle. Its a good sized board, but it has MOSFETs and a couple of linear devices taking up real estate and those need thermal consideration. It has to live in a variable velocity blast of hot air followed by “hot soaks” between cycles where no significant flow occurs… which makes things even more fun.
Ok, would a smaller Footprint P1 do the job.
I'm really not sure about grounding the unused supply pins, you could get current flowing from the 1v8<>3v3 level translators if you did that (i think?)
Perhaps connecting them to 1v8 might be better than floating. These are really good questions for Chip
I've just plugged in my old revA Eval Board and then, without loading any program, attached a scope probe to V0815 and removed the VIO supply jumper and watched the rail slowly discharge over the next few minutes. It got down to about 300 mV when I decided to apply a 470 ohm resistor to GND. Removing the resistor again the now fully discharged rail now stayed at less than 1.0 mV. Scope can't really show any finer.
Now 10 minutes gone by and V0815 is still at zero volts with no load holding it down. The power is still applied to all other VIO and VDD is at 1.8 Volts.
Conclusion: No problem tying whole pin groups, including the respective VIO pin, to GND.
PS: And subsequent power cycling of whole Eval Board has no impact. The unplugged V0815 rail didn't even get a slight bump. Totally flat and silent scope trace. Very good result!
@evanh You are THE MAN! I owe you an adult beverage! Thank you for that effort. I dont know yet if it saved me, but I’ll know tonight, and its good info for everyone to have. This should probably be suggested as an addition to the P2 docs.
@DigitalBob Unfortunately the P1 isnt well suited to this task. I need smart pins running in “set and forget” mode. If I had something like dev time, I might try the P1, but I’m in a crunch.
@Yanomani You’re on the list of Parallaxians that I want to clone.
Every time you post I learn something.
@Tubular I have a knee-jerk response (probably not based on reality) that says putting 1.8 on the 3.3s is a bad idea. Its at that magical halfway point that we are told to avoid. I do hope Chip opines on this someday once his current task list gets whittled down a bit.
To all: thank you for your help and ideas. This is why I love Parallax: peer support! Yay!
Just because it works for you doesn't mean it's correct, nor will it cause problems in the future. Chip is the only one who can answer this!
IIRC the I/O pin groups were specifically designed to have supplies from 1V8 to 3V3. However, Chip did some testing and advised against using 1V8 for some reason which I think was about connecting 1V8 peripheral chips, not the fact of using 1V8. Again, only Chip can answer this.
The thing i remember Chip saying that if you have VIO less than 3v3 (eg 2v5) the level translators to the 1v8 domain slow right now. However if you're not using those pins at all this hardly matters. I'm kind of curious what current does flow down to ground
Yes, it was a speed degradation. Possibly just the cumulative effect of every transistor's R-C curve in the chain. EDIT: Ah... compounded by the lowered gate voltage increasing the channel resistance.
I remember Chip even waning against use of 3.0 Volts for VIO. So not really designed for anything less than 3.3 Volts.
It's ever a two-way road, for all of us.
Worths to notice that such kind of "magical" midway point (e.g.: 1.8V, as related to 3.6V) is only valid IF the VIOs where set to... 3.6V.
IOW, when it comes to supply voltages, cmos is known to be extremely forgiving; in fact, it becames such a mainstream option for integrated circuits exactly due to that characteristic.
And it just scales realy nice; voltage versus geometric-proportions-wise.
My main concern is about the protection structures that souround most of the devices placed at the pad ring (aka N-wells and guard-rings), that rely on multiple-stacked semiconductor junctions (both vertically and horizontally) and their proper biasing, in order to ensure noise and voltage-spikes can't be injected into sensitive nodes, but, if the unused I/O pins themselves are grounded, there are far less chances for something weird to happen.
Some three weeks ago, ManAtWork did found new operational limits, and way much is left to be discovered, elsewhere, everywhere.
https://forums.parallax.com/discussion/comment/1530153/#Comment_1530153
So, please, just keep Star-Treking P2, you and everyone!