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I/O Pins — Parallax Forums

I/O Pins

Most interested in finding how the I/O pins are interfaced to the internal bus, and whether or not they have internal pull-up’s. If anyone has a simple schematic or can point to it, it would be much appreciated. They seem to drive a lot of current (40 mA.) so I would imagine there is a transistor, or something like CMOS except faster.

I was thinking of what is the best thing to do with unused pins, although it seems to work if the pins are left unconnected, is it better to ground or pull them high?

Comments

  • VonSzarvasVonSzarvas Posts: 2,453
    edited 2021-09-06 14:41

    Propeller 1 :

    There's a bunch of docs here (in case you've not seen them yet) : https://www.parallax.com/download/propeller-1-documentation/

    Propeller 1 was Open Sourced, so you'll find the complete verilog sources in the forum somewhere if you want to get into the exact details about the IO structure.

    There are no internal pullups in Propeller 1- same rules apply as for typical microcontrollers in commercial applications; that you'd want to consider either grounding or pulling high, or leave them unconnected and drive the unused pins low in your code file. For experimenting you'd either leave them unconnected, or else use a resistor to ground, so that if the pin is driven high in code during development you don't have a sudden failure by shorting power to gnd!

  • PublisonPublison Posts: 12,058

    Since you posted in the P1 forum, are you looking for info on the P1 or P2?

  • Good catch Publison. I thought the Q was showing in the P2 category. I'll get that reply above edited to include P1 links.

  • evanhevanh Posts: 11,672

    Both Prop1 and Prop2 I/O are custom CMOS by Parallax. I don't know of Chip ever published any schematics for the Prop1.

    Prop2 is here - https://forums.parallax.com/discussion/comment/1494131/#Comment_1494131
    And 3D layout viewer - https://forums.parallax.com/discussion/164113/prop2-layout-viewer-try-it-out
    And its floorplan before HDL synthesis - https://forums.parallax.com/discussion/download/129402/DIE_100.PNG

  • evanhevanh Posts: 11,672
    edited 2021-09-06 17:34

    @NickMikhay said:
    I was thinking of what is the best thing to do with unused pins, although it seems to work if the pins are left unconnected, is it better to ground or pull them high?

    Drive the unused pins high if you like. I doubt there's any advantage in tying unused I/O pins outside the chip.

  • JonnyMacJonnyMac Posts: 7,706

    Most interested in finding how the I/O pins are interfaced to the internal bus, and whether or not they have internal pull-up’s.

    Not on the P1. The P2 has configurable pull-ups and pull-downs.

    One thing that is important to grasp with the Propeller family is that outputs are OR'd together for the final output. What this means is that if any cog makes that pin an output and high, it cannot be pulled back low by another cog. The PI docs have a great diagram that shows this.

  • evanhevanh Posts: 11,672

    Oh, yeah, that's a good point. The I/O is direct signalling between the pins and the cogs. Asynchronous even. There is a path for each pin input and another path for each pin output. No intermediary databus.

  • It's better to set unused I/O pins to OUTPUT mode, either HIGH or LOW. INPUT pins have very high impedance and will float if unconnected taking more power than if you use a pull-up or pull-down resistor.

    There was some testing done of the I/O pins shortly after the Prop 1 was available in silicon. The Prop 1's I/O structures appear to indefinitely tolerate shorting to the opposite polarity. They're not spec'd for this, but Chip designed them to be very robust.

  • RaymanRayman Posts: 12,185

    I never did anything special with unused pins and never saw an issue...

    That said, it probably is better to drive them high or low as @"Mike Green" says.

  • Where do you get unused pins from. I never have enough pins.

    But joke aside. If you are concerned about your free pins the easiest way is to configure them as outputs and set them to 0.
    But this is trap: If you later modify your project this gets easily overlooked when you want to use this pin for input, especially if this happens in another cog.

    Reinhardt

  • If I ever run out I can go to the P2. I hope it will be a smooth transition.

  • I take it you are looking at a two mos transistors, joined at drain and source and one is always enabled to determine if the pin is high or low by pulling to the voltage rail or to ground.

  • evanhevanh Posts: 11,672

    Yes. That's the C in CMOS.

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