@Wuerfel_21 said:
It's not like I need to look at more than a few packets. They all seem to come out just fine.
Did you end up capturing the actual data to solve the issue you found (couldn't exactly tell by your 2nd post if you did), or did you figure it out by examining the logic of the decoder software etc...?
I added a DEBUG line next to the WRLUT that writes the encoded data. Then i wrote a script to convert that to binary data and fed it into your program.
Looks something like this (I think this is the regen test branch, after the fix):
Ugg, still same RGB colors with your latest build and this one line change to NeoVGA.spin2. Are you sure this is the correct bit pattern for the YUV change?
EDIT: YUV select bit position seems okay but I just read this:
"When the IT content bit is set to 1 and the Graphics type is indicated, downstream processors should pass Pixel Data unfiltered and without analog reconstruction."
You seem to be setting this bit and graphics type is 00 in data byte 5 if that is zeroed. So it may be preventing the conversion into YUV. I'll try to set this IT bit to 0 to see if that helps.
EDIT2: Nope no help. Still same RGB colours being presented.
EDIT3: Also tested on the projector and it didn't switch into YUV mode either.
Actually I just built that with MODE_DVI_VGA , because I was messing with that, but normally I do set it to HDMI. I will update the above in a sec. Done.
I've got Version 7.0.0-alpha-v6.9.7-52-gada40c8f Compiled on: Jul 2 2024 or Version 6.9.8-HEAD-v6.9.8 Compiled on: Aug 7 2024
Though if your machine has 32 bit longs, this might also be one of our favorite platform dependent oopsies.
Maybe I should take another full clean update from your regen branch to make sure it is fully up to date? I've mainly been updating NeoVGA.spin2 and vgatest.spin2 in the last two days since they seem to be the only files you are committing recently. Will do that and then re-diff the listing files of both builds of vgatest.spin2 locally.
No, only difference in the build is this single line which is the YUV change vs fresh tree. Ugh can't format it nicely.
`
❯ diff vgatest.lst ../NeoYume-hdmi-clock-regen-test
2347,2348c2347,2348
< 01a00 00 44 44 FF
I've made progress in the capture to PSRAM code but seem to be having a problem with the IO pins and the streamer. For some reason I can't seem to read back the upper nibble of the HDMI pins with the streamer (with or without readback remapping). Just coded it all up today and its not working correctly if I read the HDMI pins but at one point it seemed to sample pins ok if I chose another uncommitted IO nibble on pins 0..3 which has some incrementing numbers being written to them as a test pattern, so I know the overall capture logic should be working. I also modified your NeoVGA code to ensure it only setup the Repo mode mailbox on the bottom pin of the 8 pin group (DIGITAL_BASEPIN) in case that had any effect, no help.
I'm starting to wonder if you can't read back correctly the input pin states of pins being streamed to in another COG and I'm trying to remember what @cgracey said about this.
Hacked code attached. You might have more luck than me @Wuerfel_21 . It's very close to working IMO. Right now it messes with P0-P3 so disable that spew() routine if you have boards fitted on those pins.
Serial port console controls capture @115200.
Enter starts capture - it automatically stops after 2MB is captured to PSRAM.
Space reads a screenful of nibble data from the capture start buffer and increments read address by 64 samples.
ESC resets read pointer back to 0 in PSRAM
Obviously still needs a file writer to SD or bulk upload of data to serial port.
Comments
I added a DEBUG line next to the WRLUT that writes the encoded data. Then i wrote a script to convert that to binary data and fed it into your program.
Looks something like this (I think this is the regen test branch, after the fix):
Decoding TMDS bits on 10b triplets per int: sample bits Type Red(ch2) Green(ch1) Blue(ch0) Clock 1 10 :-> TERC4 0001_0000_0010 +V H- 1001100011 1010011100 1011100100 0000011111 2 10 :-> TERC4 0001_0001_1110 +V H- 1001100011 1001100011 0101100011 0000011111 3 10 :-> TERC4 0000_0001_1010 +V H- 1010011100 1001100011 0110011100 0000011111 4 10 :-> TERC4 0000_0000_1010 +V H- 1010011100 1010011100 0110011100 0000011111 5 10 :-> TERC4 0000_0001_1010 +V H- 1010011100 1001100011 0110011100 0000011111 6 10 :-> TERC4 0000_0000_1010 +V H- 1010011100 1010011100 0110011100 0000011111 7 10 :-> TERC4 0000_0000_1010 +V H- 1010011100 1010011100 0110011100 0000011111 8 10 :-> TERC4 0000_0001_1110 +V H- 1010011100 1001100011 0101100011 0000011111 9 10 :-> TERC4 0000_0000_1010 +V H- 1010011100 1010011100 0110011100 0000011111 10 10 :-> TERC4 0001_0000_1110 +V H- 1001100011 1010011100 0101100011 0000011111 11 10 :-> TERC4 0000_0000_1010 +V H- 1010011100 1010011100 0110011100 0000011111 12 10 :-> TERC4 0001_0000_1010 +V H- 1001100011 1010011100 0110011100 0000011111 13 10 :-> TERC4 0000_0000_1010 +V H- 1010011100 1010011100 0110011100 0000011111 14 10 :-> TERC4 0001_0000_1010 +V H- 1001100011 1010011100 0110011100 0000011111 15 10 :-> TERC4 0000_0000_1010 +V H- 1010011100 1010011100 0110011100 0000011111 16 10 :-> TERC4 0001_0000_1010 +V H- 1001100011 1010011100 0110011100 0000011111 17 10 :-> TERC4 0000_0000_1110 +V H- 1010011100 1010011100 0101100011 0000011111 18 10 :-> TERC4 0000_0000_1010 +V H- 1010011100 1010011100 0110011100 0000011111 19 10 :-> TERC4 0000_0000_1110 +V H- 1010011100 1010011100 0101100011 0000011111 20 10 :-> TERC4 0000_0000_1110 +V H- 1010011100 1010011100 0101100011 0000011111 21 10 :-> TERC4 0000_0000_1010 +V H- 1010011100 1010011100 0110011100 0000011111 22 10 :-> TERC4 0000_0000_1010 +V H- 1010011100 1010011100 0110011100 0000011111 23 10 :-> TERC4 0000_0000_1010 +V H- 1010011100 1010011100 0110011100 0000011111 24 10 :-> TERC4 0000_0000_1010 +V H- 1010011100 1010011100 0110011100 0000011111 25 10 :-> TERC4 0000_0000_1010 +V H- 1010011100 1010011100 0110011100 0000011111 26 10 :-> TERC4 0000_0000_1010 +V H- 1010011100 1010011100 0110011100 0000011111 27 10 :-> TERC4 0000_0000_1110 +V H- 1010011100 1010011100 0101100011 0000011111 28 10 :-> TERC4 0000_0000_1010 +V H- 1010011100 1010011100 0110011100 0000011111 29 10 :-> TERC4 0000_0001_1010 +V H- 1010011100 1001100011 0110011100 0000011111 30 10 :-> TERC4 0000_0000_1110 +V H- 1010011100 1010011100 0101100011 0000011111 31 10 :-> TERC4 0000_0000_1110 +V H- 1010011100 1010011100 0101100011 0000011111 32 10 :-> TERC4 0000_0001_1110 +V H- 1010011100 1001100011 0101100011 0000011111 TERC4 Packet Decoded: Pkthdr: 0D0282 ECC=E4 ComputedECC=E4 Subpkt0: 0000008888411E ECC=41 ComputedECC=41 Subpkt1: 00000000000000 ECC=00 ComputedECC=00 Subpkt2: 00000000000000 ECC=00 ComputedECC=00 Subpkt3: 00000000000000 ECC=00 ComputedECC=00 Video Infoframe packet Version:2 Length :13 Chksum :1E Data: (LSB First) 41 88 88 00 00 00 00 00 00 00 00 00 00 33 10 :-> TERC4 0000_0000_1101 V- +H 1010011100 1010011100 1001110001 0000011111 34 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 35 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 36 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 37 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 38 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 39 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 40 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 41 10 :-> TERC4 0000_1111_1001 V- +H 1010011100 1011000011 0100111001 0000011111 42 10 :-> TERC4 1111_0000_1001 V- +H 1011000011 1010011100 0100111001 0000011111 43 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 44 10 :-> TERC4 1111_0000_1001 V- +H 1011000011 1010011100 0100111001 0000011111 45 10 :-> TERC4 0000_1111_1001 V- +H 1010011100 1011000011 0100111001 0000011111 46 10 :-> TERC4 1111_1111_1001 V- +H 1011000011 1011000011 0100111001 0000011111 47 10 :-> TERC4 1111_0000_1001 V- +H 1011000011 1010011100 0100111001 0000011111 48 10 :-> TERC4 1111_0000_1001 V- +H 1011000011 1010011100 0100111001 0000011111 49 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 50 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 51 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 52 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 53 10 :-> TERC4 0000_1111_1001 V- +H 1010011100 1011000011 0100111001 0000011111 54 10 :-> TERC4 1111_0000_1001 V- +H 1011000011 1010011100 0100111001 0000011111 55 10 :-> TERC4 0000_1111_1001 V- +H 1010011100 1011000011 0100111001 0000011111 56 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 57 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 58 10 :-> TERC4 0000_0000_1101 V- +H 1010011100 1010011100 1001110001 0000011111 59 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 60 10 :-> TERC4 0000_0000_1101 V- +H 1010011100 1010011100 1001110001 0000011111 61 10 :-> TERC4 1111_0000_1001 V- +H 1011000011 1010011100 0100111001 0000011111 62 10 :-> TERC4 1111_1111_1001 V- +H 1011000011 1011000011 0100111001 0000011111 63 10 :-> TERC4 1111_1111_1101 V- +H 1011000011 1011000011 1001110001 0000011111 64 10 :-> TERC4 1111_1111_1001 V- +H 1011000011 1011000011 0100111001 0000011111 TERC4 Packet Decoded: Pkthdr: 000001 ECC=4A ComputedECC=4A Subpkt0: 001900AD890000 ECC=FE ComputedECC=FE Subpkt1: 001900AD890000 ECC=FE ComputedECC=FE Subpkt2: 001900AD890000 ECC=FE ComputedECC=FE Subpkt3: 001900AD890000 ECC=FE ComputedECC=FE Clock regen packet SubPkt0 N = 6400 CTS = 35245 SubPkt1 N = 6400 CTS = 35245 SubPkt2 N = 6400 CTS = 35245 SubPkt3 N = 6400 CTS = 35245 65 10 :-> TERC4 0000_0000_1111 +V +H 1010011100 1010011100 1011000011 0000011111 66 10 :-> TERC4 0000_0000_1011 +V +H 1010011100 1010011100 1011000110 0000011111 67 10 :-> TERC4 0000_0000_1011 +V +H 1010011100 1010011100 1011000110 0000011111 68 10 :-> TERC4 0000_0000_1011 +V +H 1010011100 1010011100 1011000110 0000011111 69 10 :-> TERC4 0000_0000_1011 +V +H 1010011100 1010011100 1011000110 0000011111 70 10 :-> TERC4 0000_0000_1011 +V +H 1010011100 1010011100 1011000110 0000011111 71 10 :-> TERC4 0000_0000_1011 +V +H 1010011100 1010011100 1011000110 0000011111 72 10 :-> TERC4 0000_0000_1011 +V +H 1010011100 1010011100 1011000110 0000011111 73 10 :-> TERC4 0000_1111_1011 +V +H 1010011100 1011000011 1011000110 0000011111 74 10 :-> TERC4 1111_0000_1011 +V +H 1011000011 1010011100 1011000110 0000011111 75 10 :-> TERC4 0000_0000_1011 +V +H 1010011100 1010011100 1011000110 0000011111 76 10 :-> TERC4 1111_0000_1011 +V +H 1011000011 1010011100 1011000110 0000011111 77 10 :-> TERC4 0000_1111_1011 +V +H 1010011100 1011000011 1011000110 0000011111 78 10 :-> TERC4 1111_1111_1011 +V +H 1011000011 1011000011 1011000110 0000011111 79 10 :-> TERC4 1111_0000_1011 +V +H 1011000011 1010011100 1011000110 0000011111 80 10 :-> TERC4 1111_0000_1011 +V +H 1011000011 1010011100 1011000110 0000011111 81 10 :-> TERC4 0000_0000_1011 +V +H 1010011100 1010011100 1011000110 0000011111 82 10 :-> TERC4 0000_0000_1011 +V +H 1010011100 1010011100 1011000110 0000011111 83 10 :-> TERC4 0000_0000_1011 +V +H 1010011100 1010011100 1011000110 0000011111 84 10 :-> TERC4 0000_0000_1011 +V +H 1010011100 1010011100 1011000110 0000011111 85 10 :-> TERC4 0000_1111_1011 +V +H 1010011100 1011000011 1011000110 0000011111 86 10 :-> TERC4 1111_0000_1011 +V +H 1011000011 1010011100 1011000110 0000011111 87 10 :-> TERC4 0000_1111_1011 +V +H 1010011100 1011000011 1011000110 0000011111 88 10 :-> TERC4 0000_0000_1011 +V +H 1010011100 1010011100 1011000110 0000011111 89 10 :-> TERC4 0000_0000_1011 +V +H 1010011100 1010011100 1011000110 0000011111 90 10 :-> TERC4 0000_0000_1111 +V +H 1010011100 1010011100 1011000011 0000011111 91 10 :-> TERC4 0000_0000_1011 +V +H 1010011100 1010011100 1011000110 0000011111 92 10 :-> TERC4 0000_0000_1111 +V +H 1010011100 1010011100 1011000011 0000011111 93 10 :-> TERC4 1111_0000_1011 +V +H 1011000011 1010011100 1011000110 0000011111 94 10 :-> TERC4 1111_1111_1011 +V +H 1011000011 1011000011 1011000110 0000011111 95 10 :-> TERC4 1111_1111_1111 +V +H 1011000011 1011000011 1011000011 0000011111 96 10 :-> TERC4 1111_1111_1011 +V +H 1011000011 1011000011 1011000110 0000011111 TERC4 Packet Decoded: Pkthdr: 000001 ECC=4A ComputedECC=4A Subpkt0: 001900AD890000 ECC=FE ComputedECC=FE Subpkt1: 001900AD890000 ECC=FE ComputedECC=FE Subpkt2: 001900AD890000 ECC=FE ComputedECC=FE Subpkt3: 001900AD890000 ECC=FE ComputedECC=FE Clock regen packet SubPkt0 N = 6400 CTS = 35245 SubPkt1 N = 6400 CTS = 35245 SubPkt2 N = 6400 CTS = 35245 SubPkt3 N = 6400 CTS = 35245 97 10 :-> TERC4 0000_0000_0001 V- +H 1010011100 1010011100 1001100011 0000011111 98 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 99 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 100 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 101 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 102 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 103 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 104 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 105 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 106 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 107 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 108 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 109 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 110 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 111 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 112 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 113 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 114 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 115 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 116 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 117 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 118 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 119 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 120 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 121 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 122 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 123 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 124 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 125 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 126 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 127 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 128 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 TERC4 Packet Decoded: Pkthdr: 000000 ECC=00 ComputedECC=00 Subpkt0: 00000000000000 ECC=00 ComputedECC=00 Subpkt1: 00000000000000 ECC=00 ComputedECC=00 Subpkt2: 00000000000000 ECC=00 ComputedECC=00 Subpkt3: 00000000000000 ECC=00 ComputedECC=00 129 10 :-> TERC4 0000_0000_0001 V- +H 1010011100 1010011100 1001100011 0000011111 130 10 :-> TERC4 0000_0000_1101 V- +H 1010011100 1010011100 1001110001 0000011111 131 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 132 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 133 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 134 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 135 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 136 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 137 10 :-> TERC4 0000_0000_1101 V- +H 1010011100 1010011100 1001110001 0000011111 138 10 :-> TERC4 0000_0000_1101 V- +H 1010011100 1010011100 1001110001 0000011111 139 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 140 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 141 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 142 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 143 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 144 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 145 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 146 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 147 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 148 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 149 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 150 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 151 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 152 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 153 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 154 10 :-> TERC4 0010_0010_1001 V- +H 1011100100 1011100100 0100111001 0000011111 155 10 :-> TERC4 0000_0000_1001 V- +H 1010011100 1010011100 0100111001 0000011111 156 10 :-> TERC4 0010_0010_1001 V- +H 1011100100 1011100100 0100111001 0000011111 157 10 :-> TERC4 0010_0000_1001 V- +H 1011100100 1010011100 0100111001 0000011111 158 10 :-> TERC4 0000_0010_1001 V- +H 1010011100 1011100100 0100111001 0000011111 159 10 :-> TERC4 0010_0010_1001 V- +H 1011100100 1011100100 0100111001 0000011111 160 10 :-> TERC4 0010_0010_1101 V- +H 1011100100 1011100100 1001110001 0000011111 TERC4 Packet Decoded: Pkthdr: 000302 ECC=80 ComputedECC=80 Subpkt0: 00000000000000 ECC=00 ComputedECC=00 Subpkt1: CC000000000000 ECC=F6 ComputedECC=F6 Subpkt2: 00000000000000 ECC=00 ComputedECC=00 Subpkt3: 00000000000000 ECC=00 ComputedECC=00 Audio packet Sample 0 right = 000000, left = 000000, flags=00 Pr=0 Cr=0, Pl=0 Cl=0 ParityR=0 ParityL=0 Channel status count=0 Sample 1 right = 000000, left = 000000, flags=CC Pr=1 Cr=1, Pl=1 Cl=1 ParityR=0 ParityL=0 Channel status count=1Channel status also seems to read OK (very far into the file).
Also, attached my hastily 64 bit fixed version of your program.
Ugg, still same RGB colors with your latest build and this one line change to NeoVGA.spin2. Are you sure this is the correct bit pattern for the YUV change?
' mov packet_data0,##%1_000_10_00___10_00_1000___0_10_0_00_01 << 8'
EDIT: YUV select bit position seems okay but I just read this:
"When the IT content bit is set to 1 and the Graphics type is indicated, downstream processors should pass Pixel Data unfiltered and without analog reconstruction."
You seem to be setting this bit and graphics type is 00 in data byte 5 if that is zeroed. So it may be preventing the conversion into YUV. I'll try to set this IT bit to 0 to see if that helps.
EDIT2: Nope no help. Still same RGB colours being presented.
EDIT3: Also tested on the projector and it didn't switch into YUV mode either.
Can you build vgatest with listing enabled(-l)? Just to make sure we're actually running the same thing.
Ok, do you want the listing file posted somehow?
Which file do you want? I modified the ./build.sh to add -l to each step.
Yea, just attach it
Here were the output files...
Actually I just built that with MODE_DVI_VGA , because I was messing with that, but normally I do set it to HDMI. I will update the above in a sec. Done.
Here's the vgatest listing file too. Sorry did full NeoYume first.
??? Yeah this is what I wanted(?) to see, random 1 bit difference in output.
What the hell is that?
I think that's the branch offset for the callpa being off by one. How does that happen?
Different compiler version? I'm using:
Version 7.0.0-beta-v6.9.7-31-g7643e936 Compiled on: May 18 2024
I've got
Version 7.0.0-alpha-v6.9.7-52-gada40c8f Compiled on: Jul 2 2024orVersion 6.9.8-HEAD-v6.9.8 Compiled on: Aug 7 2024Though if your machine has 32 bit longs, this might also be one of our favorite platform dependent oopsies.
No this is a newer 64 bit machine, MacMini M2 Pro
Maybe I should take another full clean update from your regen branch to make sure it is fully up to date? I've mainly been updating NeoVGA.spin2 and vgatest.spin2 in the last two days since they seem to be the only files you are committing recently. Will do that and then re-diff the listing files of both builds of vgatest.spin2 locally.
No, only difference in the build is this single line which is the YUV change vs fresh tree. Ugh can't format it nicely.
`
❯ diff vgatest.lst ../NeoYume-hdmi-clock-regen-test
2347,2348c2347,2348
< 01a00 00 44 44 FF
< 01a04 00 69 07 F6 | mov packet_data0,##%1_000_10_00___10_00_1000___0_00_0_00_01 << 8
`
Update flexspin. Bug was fixed in b08d41bee0581a7b0b2a67eb36e27f746b371b21
Okay, pulled in latest spin2cpp and made flexspin again:
Version 7.0.0-beta-v6.9.7-65-g3914edfd Compiled on: Sep 9 2024
Here's the listing of vgatest.lst with the YUV change back in.
Yes, code now matches.
Ok, this is what the YUV change seems to be showing on the plasma. EDIT: Still no audio though disappointingly.
Yea that's about right for that.
Can you try the plain video-nextgen branch again? That has a lot more of those CALLPAs
Yeah that branch also works in the video test, without audio. Here it is running in RGB mode this time.
Well that's back to square one.
It also works okay in YUV mode on the next-gen branch when I patched that in just now.
Try this (in either branch, but the regen test one has a slightly higher chance of working ig):
Add this just before
call #util_infoframe_chksum' HACK: No, actually do an Audio Infoframe mov packet_header,##$0A_01_84 mov packet_data0,##%00000000___0000_00_00___0000_0_001 << 8Apparently most of the values need to be zero, anyways.
I've made progress in the capture to PSRAM code but seem to be having a problem with the IO pins and the streamer. For some reason I can't seem to read back the upper nibble of the HDMI pins with the streamer (with or without readback remapping). Just coded it all up today and its not working correctly if I read the HDMI pins but at one point it seemed to sample pins ok if I chose another uncommitted IO nibble on pins 0..3 which has some incrementing numbers being written to them as a test pattern, so I know the overall capture logic should be working. I also modified your NeoVGA code to ensure it only setup the Repo mode mailbox on the bottom pin of the 8 pin group (DIGITAL_BASEPIN) in case that had any effect, no help.
I'm starting to wonder if you can't read back correctly the input pin states of pins being streamed to in another COG and I'm trying to remember what @cgracey said about this.
Hacked code attached. You might have more luck than me @Wuerfel_21 . It's very close to working IMO. Right now it messes with P0-P3 so disable that spew() routine if you have boards fitted on those pins.
Serial port console controls capture @115200.
Enter starts capture - it automatically stops after 2MB is captured to PSRAM.
Space reads a screenful of nibble data from the capture start buffer and increments read address by 64 samples.
ESC resets read pointer back to 0 in PSRAM
Obviously still needs a file writer to SD or bulk upload of data to serial port.
You probably want to use these modes:
TMDS_DRIVE_MODE = P_REPOSITORY|P_OE|P_LOW_FAST|P_HIGH_FAST|P_SYNC_IO TMDS_DRIVE_MODE2 = P_LOW_FAST|P_HIGH_FAST|P_SYNC_IO(I think P_OE is nonsense in non-smart modes?)
Tried. Didn't help. Something weird is going on, maybe with the streamer or FIFO, can't tell.
Did you run this yet?
Hadn't but just tried it now. No improvement on sound on Plasma.