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P2 PASM SIN 16Bit

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  • pic18f2550pic18f2550 Posts: 169
    edited 2021-04-14 10:58

    OK now I understand.
    I have adjusted my example accordingly.
    I just have to test it.

    I have to think about a runtime measurement.

  • @evanh said:

    Each cog has a 34-bit bus to each smart pin for write data and acknowledgment signalling. Each smart pin OR's all incoming 34-bit buses from the cogs in the same way DIR and OUT bits are OR'd before going to the pins. Therefore, if you intend to have multiple cogs execute WRPIN / WXPIN / WYPIN / RDPIN / AKPIN instructions on the same smart pin, you must be sure that they do so at different times, in order to avoid clobbering each other's bus data. Any number of cogs can read a smart pin simultaneously, without bus conflict, though, by using RQPIN ('read quiet'), since it does not utilize the 34-bit cog-to-smart-pin bus for acknowledgement signalling, like RDPIN does.

    Each smart pin has an outgoing 33-bit bus which conveys its Z result and a special flag. RDPIN and RQPIN are used to multiplex and read these buses, so that a pin's Z result is read into D and its special flag can be read into C. C will be either a mode-related flag or the MSB of the Z result.

    The first paragraph indicates RDPIN will mess with any coinciding writes ...

    Because RDPIN isn't read-only. It writes to the write bus - it uses the write bus to acknowledge the read.

    but the second paragraph also states there is a separate read bus for RDPIN/RQPIN.

    There is one read bus per smart pin, and that one bus is used by both RDPIN and RQPIN. In terms of reading, both instructions do the same thing and are equivalent. But RDPIN additionally acknowledges the read, using the write bus. RQPIN does not acknowledge, and thus is "quiet" and the smart pin cannot even tell that some cog is reading anything.

  • evanhevanh Posts: 10,918

    That was like five weeks back! O_o

    That now begs the question of how the write bus works? It looks like there is 32 bits for data plus 2 bits for register select. With one of the four combinations, %00, being no action. So three register selects: Mode, X and Y. That leaves a question mark on how ACK is achieved.

  • The runtime measurement brought it to light.
    I had to reduce the number of generators from 32 to 30.

    1st block
    244 with fastread 164 without fastread
    2. block
    234

    With this I have enough reserves to 250 clocks

  • How can I synchronize my DACs?

    I know that the y-value is reloaded into the DAC after 256 clocs and the conversion starts.

    I am looking for a way that all start converting at the same time.

  • evanhevanh Posts: 10,918
    edited 2021-04-17 23:58

    DIR signal is the control for resetting a smartpin to initial state. So bashing the 32-bit DIRA/B registers, or DIRL/H instructions with "addpins", (N-1)<<6, also can reset them in parallel. FLT/DRV instructions do the same, respectively.

    Eg: This code resets DIR for a group of four pins, together. Then sets up the same smartpin mode in all four, together. Then finally enables all four smartpins, together. The smartpins have the the same timing so will stay in phase with each other.

    CON
        pllpins     = 28 | 3<<6
    
    DAT
            ...
            fltl    #pllpins
            wrpin   #P_NCO_FREQ | P_OE, #pllpins
            wxpin   #1, #pllpins
            wypin   ##$8000_0000, #pllpins
            dirh    #pllpins
            ...
    
  • Sounds good only which pinns are they?
    For now, I'm only breaking from pin 0 to 5.

    Where are the pins in "pllpins = 28 | 3<<6 ".

    Can I also use any pins e.g. 3, 5, 7, 12, ...

  • evanhevanh Posts: 10,918
    edited 2021-04-19 12:57

    pllpins is P[31..28]. Same as "28 addpins 3" in Spin2.

  • evanhevanh Posts: 10,918
    edited 2021-04-19 13:01

    @pic18f2550 said:
    Can I also use any pins e.g. 3, 5, 7, 12, ...

    Not with ADDPINS, a bitmask can be used instead. Eg: OR DIRA, ##%1_0000_1010_1000

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