Peter, it seems like 1.1" row spacing with 0.1" pin spacing could be achieved based on what you've done with the P2D2. I believe your 0.05" pin spacing has 2 rows 1" apart, correct? So how were you able to achieve this when Cluso says it's not possible? Yes, I understand that the solder pads for 0.05" spacing are smaller than for 0.1", but it seems like 1.1" row spacing could be achieved.
The inner 0.050" pins are 1.0" pitch. because you now need to run 8 tracks past the IC down to their new location below the diagonal of the chip, you will need 8 tracks at 0.005" minimum, plus 8 isolation between tracks at 0.005", and these are needed on both sides, so multply by 2. Now you save the 0.050" pin pads of say 0.044" but then add back 0.1" pads of say 0.070". Now add this up.
1.0 + 2*(8*(0.005+0.005)) - 0.044 + 0.070 = 1.186" between pad centers, and this is provided you use 5mil spacing which can be more expensive to manufacture. There is a few extra clearances you need to obey too. But you wouldn't want your pins on 1.186" centers would you? So 1.2" is going to be the minimum then! Just because you can remove some components is not going to magically give you width.
The P2 body is 0.55" sq so if I were to reform the pins to press flat against the body and bend under a bit like a PLCC pack, then it might be possible to make a standard DIP40 version. I've got some old Rev A chips I can try this technique on. It's an idea.
Inventing a new package is certainly a new idea from left-field
Smallest PCB area real packages for 'Future P2' package choices could be BGA or QFN parts.
because you now need to run 8 tracks past the IC down to their new location below the diagonal of the chip, you will need 8 tracks at 0.005" minimum, plus 8 isolation between tracks at 0.005", and these are needed on both sides, so multply by 2. Now you save the 0.050" pin pads of say 0.044" but then add back 0.1" pads of say 0.070".
So the solution is to eliminate the 8 tracks. So how about just bringing out P0-P7, P16-P23, P32-P39 and P48-P55. Wouldn't that solve the problem?
Sorry, that's what I meant by a grouping. This solution provides up to 4 groups of 8 pins. For a particular application, if more groups are needed, or more than eight is needed, then this isn't the solution for that. However, I believe there are many applications where the proposed solution will work just fine.
I've been playing with KiCad, and I'm starting to figure it out. I'm hoping in a week or so I'll have something I can post. Maybe I'll name it after your description of the design -- NCD.
Sorry, that's what I meant by a grouping. This solution provides up to 4 groups of 8 pins. For a particular application, if more groups are needed, or more than eight is needed, then this isn't the solution for that. However, I believe there are many applications where the proposed solution will work just fine.
I've been playing with KiCad, and I'm starting to figure it out. I'm hoping in a week or so I'll have something I can post. Maybe I'll name it after your description of the design -- NCD.
Sorry this got so sidetracked. I'd like one.
Just about everything else I could build myself. The only other thing I could think of that I wouldn't do myself is a pair of HyperRam chips or maybe an SDRAM, where they are BGA and short traces are probably important.
I like to make production easy. Any failures become an expensive exercise as the faulty boards and parts are usually written off. Add to this, I personally am not a believer in hyperram on the P2 either.
Anyway, there’s no interest in this board anyway, so I’ll just save the cost of having pcbs made. While the actual pcbs are cheap, the screen, freight, ENIG, and full testing make up around 70% of the bare pcb cost.
IMO P2 doesn’t have a requirement for external memory, apart from loadable which can be served either by flash or sd. There are way better chips to use if 512KB SRAM (hub) is not enough.
The P1 was a different animal, at a different time. Back then, 32KB SRAM was unheard of, and for some uses, external memory (besides eeprom/flash/sd) was useful for some requirements. But back then it took almost all IO to support it (my RamBlade and derivatives). Multi-core micros were unheard of. Now they are quite common. And, peripherals are plenty in modern micros.
For example, if I wanted a large VGA and there wasn’t enough RAM in my total solution, I would add a second P2 just for the video. BTW I’m also unconvinced HDMI works on P2 yet. There are of course other chips which are also likely cheaper solutions.
The heartache to get the hyperram working on P2 just doesn’t make sense to me. You’re forcing a square peg into a round hole. If the P2 supported QSPI as a hardware peripheral then perhaps it may be a solution. But IMHO it’s a poor design wanting an application - way better chips out there that will do this way better and cheaper.
It’s just my opinion, and I reserve the right to change my opinion later.
I'm thinking how much memory is required to port FlexProp to the propeller itself, as well as having a 1080p desktop that is a joy to work on without most of the bloat and distractions.
It also bothers me that most of the processors I use have small cores that I can't control, but can spy on anything the computer is doing.
Did you want to sell me your prototype? Don't give up on this until after you present it. There was a paper that described how to pare down a protoboard into a little square, which many of us did, even though there was a DIP-40 available. I can see your NanoBlade being a hit considering that there isn't a DIP alternative.
Comments
The inner 0.050" pins are 1.0" pitch. because you now need to run 8 tracks past the IC down to their new location below the diagonal of the chip, you will need 8 tracks at 0.005" minimum, plus 8 isolation between tracks at 0.005", and these are needed on both sides, so multply by 2. Now you save the 0.050" pin pads of say 0.044" but then add back 0.1" pads of say 0.070". Now add this up.
1.0 + 2*(8*(0.005+0.005)) - 0.044 + 0.070 = 1.186" between pad centers, and this is provided you use 5mil spacing which can be more expensive to manufacture. There is a few extra clearances you need to obey too. But you wouldn't want your pins on 1.186" centers would you? So 1.2" is going to be the minimum then! Just because you can remove some components is not going to magically give you width.
Smallest PCB area real packages for 'Future P2' package choices could be BGA or QFN parts.
I've been playing with KiCad, and I'm starting to figure it out. I'm hoping in a week or so I'll have something I can post. Maybe I'll name it after your description of the design -- NCD.
There is also this work : - has a subset of DIP40 and also targets a USB case, which is more deployment friendly.
Personally, I prefer deployment to prototype, as test-bench wiring does not have to be neat.
https://forums.parallax.com/discussion/comment/1509555/#Comment_1509555
Just about everything else I could build myself. The only other thing I could think of that I wouldn't do myself is a pair of HyperRam chips or maybe an SDRAM, where they are BGA and short traces are probably important.
I like to make production easy. Any failures become an expensive exercise as the faulty boards and parts are usually written off. Add to this, I personally am not a believer in hyperram on the P2 either.
Anyway, there’s no interest in this board anyway, so I’ll just save the cost of having pcbs made. While the actual pcbs are cheap, the screen, freight, ENIG, and full testing make up around 70% of the bare pcb cost.
The P1 was a different animal, at a different time. Back then, 32KB SRAM was unheard of, and for some uses, external memory (besides eeprom/flash/sd) was useful for some requirements. But back then it took almost all IO to support it (my RamBlade and derivatives). Multi-core micros were unheard of. Now they are quite common. And, peripherals are plenty in modern micros.
For example, if I wanted a large VGA and there wasn’t enough RAM in my total solution, I would add a second P2 just for the video. BTW I’m also unconvinced HDMI works on P2 yet. There are of course other chips which are also likely cheaper solutions.
The heartache to get the hyperram working on P2 just doesn’t make sense to me. You’re forcing a square peg into a round hole. If the P2 supported QSPI as a hardware peripheral then perhaps it may be a solution. But IMHO it’s a poor design wanting an application - way better chips out there that will do this way better and cheaper.
It’s just my opinion, and I reserve the right to change my opinion later.
It also bothers me that most of the processors I use have small cores that I can't control, but can spy on anything the computer is doing.
Did you want to sell me your prototype? Don't give up on this until after you present it. There was a paper that described how to pare down a protoboard into a little square, which many of us did, even though there was a DIP-40 available. I can see your NanoBlade being a hit considering that there isn't a DIP alternative.