KiCad uses a default size of 0.4mm with an annular ring diameter of 0.8. If I change the hole size to 0.3mm can I use 0.6mm for the ring diameter?
You need to check the capabilities of your pcb manufacturer, and if they charge extra for tighter specs.
The pad dia is partially moot on the ground pad.
That's true if there's a copper pour around it. However, there are many cases where neighboring traces prevent a copper pour. It appears that you and Peter are using 0.3mm via holes, and I'm just wondering what you use for the annular ring diameter.
I also having an issue with the bypass caps. I switched to caps with a 0603 footprint size, and the DRC is complaining that the pads are too close. This was in the KiCad library, so I'm surprised that it would have a device that doesn't meet the DRC specs. To resolve this do I just need to adjust the specs? How do you and Peter handle this?
Go into your board setup under the file menu and specify these rules. My 0.3mm via has an annular ring of 0.6mm. Set your clearances to 0.127mm. https://jlcpcb.com/capabilities/Capabilities
@"Dave Hein" if you go to kicad site/forum (don't remember where exactly, IIRC the former) they have many templates for the various PCB manufacturers with all the rules already setup accordingly, for two and multilayer boards.
I thus still suggest to verify them.
I use:
Vias of 0.3mm with pad 0.6mm
Tracks 0.13mm (5.12mils), 0.15mm(5.91mils), 0.25mm(9.84mils), 0.35mm(13.78mils), 0.4mm(15.75mils), 0.5mm(19.69mils)
Clearance 0.13mm(5.12mils)
Grid mostly 0.025mm(0.98mils). Connectors are placed using imperial and 0.1" or 0.5"
I use my own 0603 pad size which is slightly smaller than the KiCad 0603 just to tweek the bypass layout around the P2 to make the layout just that little bit smaller. Unless you know what you're doing I wouldn't recommend this and for this reason I'm not going to put it up here. While it does not breach design rules, nor function, it would breach manufacturer rules because the caps are too close to the P2 for the robots to assemble. It's not a problem for me since I assemble by hand using tweezers. Once placed on the pcb the reflow oven doesn't care.
Cluso, thanks for the info. When I looked at your and Peter's designs I realized I wasn't using the same design rules as you guys. I had trouble squeezing in the bypass caps and vias between traces going to the P2. However, since I'm only using half of the I/O pins I was able to work around it by fanning out the traces. So far I'm only using 0.25mm for the signal traces, and 0.75mm and 1mm for the 3.3V and 1.8V traces feeding the P2. I use 1mm for the 1.8V because it has several vias centered in the trace. I felt that I needed more copper around the vias.
I have used 8mil tracks and clearance for years. I went to move to 6mil for the P2 (when I migrated to KiCad) but found that didn't work.
I also took the opportunity to move to metric grids and thus the 0.13mm track/clearance choice because I didn't like 0.127mm and to go lower meant manufacturing restrictions.
I have caps on every 1V8 and 3V3 P2 pin. While one on every pin may not ultimately be required, I wanted the option to place one there. That's really only 4 per chip side (being 4 sets for each of 1V8 and 3V3). In addition to that, I have one bulk capacitor on each of 3 sides (not one at the xtal corner) for each 1V8 and 3V3. This should result in one of the quietest P2 boards while still retaining single component side and 2 layers. Four layers could improve any noise but my design does make full use of the ground planes on both sides of the pcb. And I'm not using noisy switchers either.
That's why I continually state there is a minimum width possible for the pcb while still having the bypass caps properly placed and on the component side only.
@Cluso99 I read that KiCAD uses the STEP file for the MCAD functions while using the VRML file for coloring. So, both a STEP and a WRL file must be used if you don't won't the part to appear gray. I'm assuming that if a PNG image can be used, it would have to be integrated somehow in the VRML file. I've been working on this using TurboCAD and although I can generate a VRML file it renders like a ghost in KiCAD. Top is invisible but the edges look fine. What I have seen done [with KiCAD] and what I've successfully done on other projects is using a "subtraction" process to embed Text into a facet of the object.
@Cluso99 I read that KiCAD uses the STEP file for the MCAD functions while using the VRML file for coloring. So, both a STEP and a WRL file must be used if you don't won't the part to appear gray. I'm assuming that if a PNG image can be used, it would have to be integrated somehow in the VRML file. I've been working on this using TurboCAD and although I can generate a VRML file it renders like a ghost in KiCAD. Top is invisible but the edges look fine. What I have seen done [with KiCAD] and what I've successfully done on other projects is using a "subtraction" process to embed Text into a facet of the object.
I have not been able to combine the image to the qfp into one object, then save as a step file
I do have them combined in a freecad file tho. I've posted it here in case anyone can work it out.
I having problems using the bypass capacitor footprints on VDD [pin2] and V0003 [pin3] with .13 mm clearance and .13 mm traces on P00 and P01 with .13 mm clearance and I can't get the traces between the capacitors. If I use 0402 footprints, no problem. Any advice? Why are you using the 0603 footprints over the 0402 footprints? Just easier to handle?
That makes sense. I was thinking of doing something similar like putting a GND via directly under the GND pad. Sometimes I think too far outside the box. I'll stick with the 0402 for now. Thanks.
I would not place a via in the pad because it can wick the solder paste away while reflowing. You may see this done under BGA but they are very tiny vias.
It may also provide a thermal path preventing proper reflow. I know these days they do not always provide a relief around a pad, but connecting within the solder footprint is IMHO bad practice.
Working on my P2 reference design. Adding the voltage regulators today. The SMD pin headers are temporary so I can work with the traces. Just learned how to use APNG to create an animated PNG file but it doesn't seem to work in the forum. The uploader must strip out the first image. @"Moderator Monkey" would you please remove this comment. Sorry.
Speaking about the renders, I know a guy that made several contributions to the KiCAD 3D engine (I think he is actually one of the main contributors, if not the top one= His name is Mário Luzeiro. Amazing work he did!
As for the library itself, I would separate the banks in blocks, as you did. However, my doubt is, should each block have its own dedicated GND pin, or should be those tied together, as you did? I was to do the same for Eagle but never started. I would need to know how the chip is bond wired internally.
@JonnyMac thanks. KiCAD does excellent renderings. @samuell I've wondered that myself and I just realized I didn't add the GND vias to the VDD pins. I had to use GND vias to a large GND plane on the back side because the bypass capacitors are isolated from each other by the signal traces. All caps will be tied to a large ground plane on the back side. The 3V3 pins will get 3.3v through the vias under the P2 from a backside 3V3 plane as well. The VDD pins will be tied together by a VDD plane under the P2 which is fed by the source.
@CJMJ Well, I wanted to be faithful to how the chip is wired internally. I would guess that the GND pins are all bonded together, and in that sense it makes sense to tie them together on the symbol as well.
@samuell said:
@CJMJ Well, I wanted to be faithful to how the chip is wired internally. I would guess that the GND pins are all bonded together, and in that sense it makes sense to tie them together on the symbol as well.
To answer that year-old unanswered question: Obviously all GNDs are bonded to the one exposed pad. So, in that sense, they are all commoned together. But presumably the question is about the on-die internals ... There is four large metal rings in the outer custom pad-ring of the die:
First one is VSS and runs, continuously, the full circuit around the pad-ring. All 16 VSS bonding wires are evenly spaced and connect immediately to it, from the exposed pad.
Second one is VDD and runs, continuously, the full circuit around the pad-ring. All 16 VDD bonding wires are evenly spaced and connect immediately to it, from the 16 VDD pins.
Third one is GIO and runs in broken segments powering each group of four I/O pins. These are evenly space on all four sides of the die so forming a 360 degree segmented ring. One bonding wire halfway along each segment, from the exposed pad. 16 in total.
Fourth one is VIO and runs in broken segments powering each group of four I/O pins. These are evenly space on all four sides of the die so forming a 360 degree segmented ring. One bonding wire halfway along each segment, from respective VIO pin. 16 in total.
The two opposing corners containing global clock oscillators and reset circuits are also powered by the associated GIO/VIO pairs in those respective corners.
I've lost track of where I got these photos but they are dated September 2019 and May 2017: (EDIT: The 2017 ones might have been April 2016 originally)
Comments
0.3mm for double sided, or 0.2mm for multilayer.
The pad dia is partially moot on the ground pad.
I also having an issue with the bypass caps. I switched to caps with a 0603 footprint size, and the DRC is complaining that the pads are too close. This was in the KiCad library, so I'm surprised that it would have a device that doesn't meet the DRC specs. To resolve this do I just need to adjust the specs? How do you and Peter handle this?
https://jlcpcb.com/capabilities/Capabilities
I thus still suggest to verify them.
Vias of 0.3mm with pad 0.6mm
Tracks 0.13mm (5.12mils), 0.15mm(5.91mils), 0.25mm(9.84mils), 0.35mm(13.78mils), 0.4mm(15.75mils), 0.5mm(19.69mils)
Clearance 0.13mm(5.12mils)
Grid mostly 0.025mm(0.98mils). Connectors are placed using imperial and 0.1" or 0.5"
I use my own 0603 pad size which is slightly smaller than the KiCad 0603 just to tweek the bypass layout around the P2 to make the layout just that little bit smaller. Unless you know what you're doing I wouldn't recommend this and for this reason I'm not going to put it up here. While it does not breach design rules, nor function, it would breach manufacturer rules because the caps are too close to the P2 for the robots to assemble. It's not a problem for me since I assemble by hand using tweezers. Once placed on the pcb the reflow oven doesn't care.
I also took the opportunity to move to metric grids and thus the 0.13mm track/clearance choice because I didn't like 0.127mm and to go lower meant manufacturing restrictions.
I have caps on every 1V8 and 3V3 P2 pin. While one on every pin may not ultimately be required, I wanted the option to place one there. That's really only 4 per chip side (being 4 sets for each of 1V8 and 3V3). In addition to that, I have one bulk capacitor on each of 3 sides (not one at the xtal corner) for each 1V8 and 3V3. This should result in one of the quietest P2 boards while still retaining single component side and 2 layers. Four layers could improve any noise but my design does make full use of the ground planes on both sides of the pcb. And I'm not using noisy switchers either.
That's why I continually state there is a minimum width possible for the pcb while still having the bypass caps properly placed and on the component side only.
I do have them combined in a freecad file tho. I've posted it here in case anyone can work it out.
It may also provide a thermal path preventing proper reflow. I know these days they do not always provide a relief around a pad, but connecting within the solder footprint is IMHO bad practice.
As for the library itself, I would separate the banks in blocks, as you did. However, my doubt is, should each block have its own dedicated GND pin, or should be those tied together, as you did? I was to do the same for Eagle but never started. I would need to know how the chip is bond wired internally.
Kind regards, Samuel Lourenço
@cgracey Can you confirm this?
Kind regards, Samuel Lourenço
To compliment / contribute projects: a 3D cad file.
https://grabcad.com/library/parallax-propeller-p2-p2x8c4m64p-1
To answer that year-old unanswered question: Obviously all GNDs are bonded to the one exposed pad. So, in that sense, they are all commoned together. But presumably the question is about the on-die internals ... There is four large metal rings in the outer custom pad-ring of the die:
The two opposing corners containing global clock oscillators and reset circuits are also powered by the associated GIO/VIO pairs in those respective corners.
I've lost track of where I got these photos but they are dated September 2019 and May 2017: (EDIT: The 2017 ones might have been April 2016 originally)
Found the 2016 ones - https://forums.parallax.com/discussion/comment/1372050/#Comment_1372050
Oh, hehe, and the 3D stuff too - https://forums.parallax.com/discussion/164113/prop2-layout-viewer-try-it-out/p1