Kwinn,
We're throwing out names for replacing ambiguous A and B names. Either for the custom ring's PinA/B, or for the smartpins's two A/B inputs. Neither these locations are the +-1,2,3 at the input selector mux.
That said, PinA/B is closely associated to even/odd but has two distinct differences:
- Firstly, even/odd covers the whole I/O pair, it refers to P## pin numbering and it refers to smartpin functionality.
- Secondly, PinA/B are not locked as even or odd. PinA is itself, whatever pin is being addressed, even or odd, while PinB is the partnering pin of the even/odd pair.
SmartA/B exist equally in all I/O. There is no even/odd association.
Thanks to everyone. I appreciate your help. I go by what I see in the block diagram (SmartpinDiagram3m.png) that shows a pair of SmartPins, "Physical Even # Pin" and a "Physical Odd # Pin." The block diagram shows a difference between the Physical Even pins and the Physical Odd pins:
1. The "Physical Even# Pins" receive an RND signal that connects to the "Other" signal at its (orange) Logic Output block. The "Physical Odd# Pins" do not have this connection.
2. The "Physical Even# Pins" produce an "Output" signal from that orange block. That signal goes to the Logic Output block for the "Physical Odd# Pins," where it has the label "Other."
Unless the diagram is wrong, it shows a connection between the "Physical Even# Pin" circuit and to the "Physical Odd# Pin" circuit. (I realize pins connect to other nearby I/O pins, too.)
So it looks--again, from the diagram--like we have an even# pin internally linked to an odd# pin.
I'm trying to understand how the pins work so I can describe operations in the Propeller-2 manual. I realize Smart-Pin circuits can connect to other pins nearby, but for now, let's concentrate on those shown in the diagram--again, I assume it is correct.
1. Is there a difference between the even# and the odd# Smart Pins? If so, what is it? And why is it there? If not, why the difference in signals that connect to the even# and odd# pins?
2. Would programmers use the two types of pins in different ways?
3. I am also confused by the %AAAA and %BBBB fields in the WRPIN instruction. Can someone clarify why one Smart Pin requires two input selectors? The sentence above the table of choices on page 65 of the draft manual notes:
"For the WRPIN instruction, which establishes both the low-level and Smart-Pin configuration for each I/O pin, the D operand is composed as:"
Does this sentence mean the %AAAA bits configure the low-level port action and the %BBBB bits configure the Smart-Pin actions? What is the difference and how is it determined? How would a program switch from low-level to Smart-Pin functions?
Again, thanks for your help. I appreciate the time it takes to think about my queries and to answer them. --Jon
Very briefly...
1) Yes there is a difference between even and odd pin capabilities. You found one of them. It extends the capabilities and probably saves duplicating internal logic in cases where it may have been prohibitive to do so.
2) They could yes, because of these differences in 1).
3) Some Smartpin modes use two inputs A, and B (eg. quadrature encoder mode). The %AAAA and %BBBB fields control the input muxes feeding signals to each A and B input of a Smartpin logic block respectively.
"For the WRPIN instruction, which establishes both the low-level and Smart-Pin configuration for each I/O pin, the D operand is composed as:"
Does this sentence mean the %AAAA bits configure the low-level port action and the %BBBB bits configure the Smart-Pin actions? What is the difference and how is it determined? How would a program switch from low-level to Smart-Pin functions?
No, %AAAA and %BBBB are selectors for the two inputs to the smartpin.
The low level config is all within the %P...P field - Which aligns with M[12:0] of the schematic for the pad ring.
EDIT: The smartpin counter modes in particular use both inputs. I've started calling these two inputs SmartA and SmartB so as to make it clearer they are not the low level PInA and PInB.
Maybe we should also draw a simplyfied block diagram for a single pin and just left out the differences of Even/Odd pins. For most Smartpin application, they really don't matter.
But also a the blocks for a single pin might be still too complex. If you for example use a pin as DAC output, all the ADC, Comparator, Logic Input blocks are not relevant.
So we would need a diagram for every Smartpin mode with only the most important blocks and connections for this mode.
evanh: Thanks for the link to your logic diagram. It answers many questions. Of course I have a few more...
1. Do the eight points shown on the left side of your logic diagram represent connections to the physical pins, say a connection to P20 (IC pin 33), with "in+1" a connection to P21 (IC pin 34)? Is all this logic implemented for each of the 64 "metal" I/O pins?
2. Is the "OUTin" a bidirectional input/output for, say, a 1-Wire interface? I assume the "in" connection would be solely for an input signal.
3. What do the smartA and smartB outputs connect to? How would a cog determine which of these outputs to use?
4. Where do the E0..E3 and L0..L3 bits come from? Does a program control these? I just want to ensure I haven't missed an instruction or operation that controls these inputs.
5. Where is the q version of the block diagrams saved? Have I missed a resource page other than propeller.parallax.com?
Thank you! --Jon
1. .. 3. See the Ray's block diagramm. Evan's logic diagramm shows the details of the dark gray 'Logic input' block. This Block also contains the Glitch-Filters.
4. These come from the 4 Filter settings, described in the chapter 'HUB Configuration' in the
'Propeller 2 Rev B Documentation' document. This document describes it all.
E means "enable", it's the shift enable pulse, per the timing tap rate, for storing each input sample in the shift register.
L means "length", for filter length selection: 2, 3, 5 or 8 samples.
Comments
We're throwing out names for replacing ambiguous A and B names. Either for the custom ring's PinA/B, or for the smartpins's two A/B inputs. Neither these locations are the +-1,2,3 at the input selector mux.
In addition the roles within a coupled pair are different - teh even pin is always D- and odd pin D+
There are some other minor differences around outputting a random noise signal from memory
- Firstly, even/odd covers the whole I/O pair, it refers to P## pin numbering and it refers to smartpin functionality.
- Secondly, PinA/B are not locked as even or odd. PinA is itself, whatever pin is being addressed, even or odd, while PinB is the partnering pin of the even/odd pair.
SmartA/B exist equally in all I/O. There is no even/odd association.
1. The "Physical Even# Pins" receive an RND signal that connects to the "Other" signal at its (orange) Logic Output block. The "Physical Odd# Pins" do not have this connection.
2. The "Physical Even# Pins" produce an "Output" signal from that orange block. That signal goes to the Logic Output block for the "Physical Odd# Pins," where it has the label "Other."
Unless the diagram is wrong, it shows a connection between the "Physical Even# Pin" circuit and to the "Physical Odd# Pin" circuit. (I realize pins connect to other nearby I/O pins, too.)
So it looks--again, from the diagram--like we have an even# pin internally linked to an odd# pin.
I'm trying to understand how the pins work so I can describe operations in the Propeller-2 manual. I realize Smart-Pin circuits can connect to other pins nearby, but for now, let's concentrate on those shown in the diagram--again, I assume it is correct.
1. Is there a difference between the even# and the odd# Smart Pins? If so, what is it? And why is it there? If not, why the difference in signals that connect to the even# and odd# pins?
2. Would programmers use the two types of pins in different ways?
3. I am also confused by the %AAAA and %BBBB fields in the WRPIN instruction. Can someone clarify why one Smart Pin requires two input selectors? The sentence above the table of choices on page 65 of the draft manual notes:
"For the WRPIN instruction, which establishes both the low-level and Smart-Pin configuration for each I/O pin, the D operand is composed as:"
Does this sentence mean the %AAAA bits configure the low-level port action and the %BBBB bits configure the Smart-Pin actions? What is the difference and how is it determined? How would a program switch from low-level to Smart-Pin functions?
Again, thanks for your help. I appreciate the time it takes to think about my queries and to answer them. --Jon
1) Yes there is a difference between even and odd pin capabilities. You found one of them. It extends the capabilities and probably saves duplicating internal logic in cases where it may have been prohibitive to do so.
2) They could yes, because of these differences in 1).
3) Some Smartpin modes use two inputs A, and B (eg. quadrature encoder mode). The %AAAA and %BBBB fields control the input muxes feeding signals to each A and B input of a Smartpin logic block respectively.
The low level config is all within the %P...P field - Which aligns with M[12:0] of the schematic for the pad ring.
EDIT: The smartpin counter modes in particular use both inputs. I've started calling these two inputs SmartA and SmartB so as to make it clearer they are not the low level PInA and PInB.
Grab the latest "q" revision of the block diagram. It has the clearer naming.
EDIT: Also, see what you can make of logic simulator schematic I've posted - https://forums.parallax.com/discussion/comment/1495075/#Comment_1495075
But also a the blocks for a single pin might be still too complex. If you for example use a pin as DAC output, all the ADC, Comparator, Logic Input blocks are not relevant.
So we would need a diagram for every Smartpin mode with only the most important blocks and connections for this mode.
Andy
1. Do the eight points shown on the left side of your logic diagram represent connections to the physical pins, say a connection to P20 (IC pin 33), with "in+1" a connection to P21 (IC pin 34)? Is all this logic implemented for each of the 64 "metal" I/O pins?
2. Is the "OUTin" a bidirectional input/output for, say, a 1-Wire interface? I assume the "in" connection would be solely for an input signal.
3. What do the smartA and smartB outputs connect to? How would a cog determine which of these outputs to use?
4. Where do the E0..E3 and L0..L3 bits come from? Does a program control these? I just want to ensure I haven't missed an instruction or operation that controls these inputs.
5. Where is the q version of the block diagrams saved? Have I missed a resource page other than propeller.parallax.com?
Thank you! --Jon
I think he was referring to Ray's diagram:
https://forums.parallax.com/discussion/171420/smartpin-diagram/p6
4. These come from the 4 Filter settings, described in the chapter 'HUB Configuration' in the
'Propeller 2 Rev B Documentation' document. This document describes it all.
Andy
L means "length", for filter length selection: 2, 3, 5 or 8 samples.