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Propeller 2 I/O Pin-Pair Diagram error — Parallax Forums

Propeller 2 I/O Pin-Pair Diagram error

JonTitusJonTitus Posts: 193
in Propeller 2
The version of the Propeller 2 I/O Pin Pair Diagram I have includes two mistakes:

1. At the bottom (odd-pin) Comparator & Logic & Schmitt.., the labels for the Pin A and Pin B need to be swapped.

2. At the bottom (odd pin) Sigma-Delta ADC, the input should be "Pin B" rather than "Pin A"

It might help to have a version number and its date within the figure area.
--Jon
«1

Comments

  • RaymanRayman Posts: 14,646
    Can you put this comment in that thread?
  • RaymanRayman Posts: 14,646
    here: http://forums.parallax.com/discussion/171420/smartpin-diagram/p6
  • RaymanRayman Posts: 14,646
    Actually, never mind. The diagram is correct. PinA is always the pins own input and PinB is the other one. This is for both even and odd pins.

    The sigma-delta input doesn't actually need a label since there is now only one option. But, there used to be an option for the other pin, but that was removed in the Rev.C silicon to reduce cross-talk between pins...
  • JonTitusJonTitus Posts: 193
    Thanks, Rayman. I saw a signal from the brown "Physical Even # Pin" block and figured--based on labels lower down--that this was a PinA signal.
    Likewise the brown line from the brown "Physical Odd # Pin" near the bottom. It seems that's not true.

    I'm baffled by the even-odd; Pin-A, Pin-B; and %AAAA and %BBBB portion of the circuit and the assembly-language code. I might just leave the assembly-language details to experts and wait for a SPIN library. The circuit and assembly-language constructs seem difficult to understand.

    I appreciate your help. --Jon
  • RaymanRayman Posts: 14,646
    edited 2020-04-22 21:21
    I think those are two separate things...
    AAAA is for that pin selector with range relative -3 to +3

    Which is why four A to represent the four bits...
  • RaymanRayman Posts: 14,646
    The pina pinb thing is a bit confusing though... maybe there’s a way to clear that up... maybe put text inside the box or something
  • evanhevanh Posts: 15,916
    We need a change of naming. Having two different meanings for 'A' in the I/O section is going to keep confusing those reading the docs. The custom circuit naming of 'A' is used as a 'self' like meaning. And 'B' means the pair partner.

    Maybe eliminate both cases and change the smartpin input selector naming as well. I've given the smartpin digital output a name already, SmartOUT. How about SmartA and SmartB? It's more wordy than A and B but does create the separation needed.

  • JonTitusJonTitus Posts: 193
    Good idea. You've got my vote. --Jon
  • evanhevanh Posts: 15,916
    Here's my first attempt. SmartA/B is in place. I've retained PinA/B in the custom pad ring area but commented with self/pair because Chip has multiple docs supporting the PinA/B naming. 
                .......................                      :               ..........................
            : Custom I/O Pad Ring :                      :               : Synthesised Core Logic :
            '''''''''''''''''''''''                      :               ''''''''''''''''''''''''''
                                                         :
                                                         :                             CogDAC (Streamers/Cogs)
                                                         :          [%%%%%%%%%%%%%]<============================= cog0
                                                         :          [             ]<============================= cog1
                       [%%%%%%%%%%%%%]                   :          [   DAC bus   ]<============================= cog2
                |      [  Flash DAC  ]<=============================[   select    ]<============================= cog3
                |<-----[   Network   ]                   :          [             ]<============================= cog4
                |      [   (%P...P)  ]                   :          [   (%P...P)  ]<============================= cog5
                |      [             ]<-                 :          [             ]<============================= cog6
                |      [%%%%%%%%%%%%%]  |                :          [             ]<============================= cog7
                |                       |                :          [%%%%%%%%%%%%%]<===\\
                |                       |                :               ^             ||
                |      [%%%%%%%%%%%%%]  |                :               |   ------------------------------------- RND
                |      [ Logic Drive ]<-+-------------   :        BitDAC |  | Other    ||
[%%%%%%%%]      |<-----[   (%P...P)  ]                |  :               |  v          ||SmartDAC
[        ]      |      [             ]<-------------  |  :          [%%%%%%%%%%%%%]    ||
[Physical]      |      [%%%%%%%%%%%%%]              | |  :   Enable [             ]<------------------------------ OUT
[ Even # ]------+            ^                      |  -------------[    Logic    ]    ||
[ Pin Pad]      |            |                      |    :   Output [    Output   ]<---------------------------+-- DIR
[        ]      |             -----------            --------+------[             ]    ||                      |
[%%%%%%%%]      |                        |               :   |      [    (%TT)    ]    ||    [%%%%%%%%%%%%]    |
                |                        |               :   |      [  (%MMMMM_0) ]    \\====[            ]    |
                |                        |               :   |  OUT [             ]          [   Even #   ]<---
                |      [%%%%%%%%%%%%%]   |               :   |   ---[             ]<---------[  Smartpin  ]
       (Self)   | PinA [  Comparator ]   |               :   |  |   [%%%%%%%%%%%%%] SmartOUT [ (%MMMMM_0) ]
                +----->[   & Logic   ]   |               :   |  |                            [            ]
       (Pair)   | PinB [  & Schmitt  ]   |               :   |  |                            [  (X reg)===]<==== WXPIN
              -------->[  (%P...P)   ]---+ Input         :   |  |     -1  -2  -3             [  (Y reg)===]<==== WYPIN
             |  |      [             ]   |               :   |  |      |   |   |             [  (Z reg)===]====> RDPIN
             |  |      [%%%%%%%%%%%%%]   |               :   |  |      v   v   v             [            ]
             |  |                        |               :   |  |   [%%%%%%%%%%%%%]  SmartA  [            ]
             |  |                        |   [%%%%%%%%]  :   |   -->[    Mux &    ]--------->[---o----o---]-------> IN
             |  |      [%%%%%%%%%%%%%]    -->[   Mux  ]  :   |      [  De-glitch  ]  SmartB  [  (M == 0)  ]
             |  |      [ Sigma-Delta ]       [(%P...P)]------------>[   (A_B_F)   ]--------->[            ]
             |  +----->[     ADC     ]------>[        ]  :   |      [%%%%%%%%%%%%%]          [            ]<------ ACK
             |  |      [  (%P...P)   ]       [%%%%%%%%]  :   |         ^   ^   ^             [  USB brain ]
             |  |      [%%%%%%%%%%%%%]                   :   |         |   |   |             [%%%%%%%%%%%%]
             |  |                                        :   |        +1  +2  +3
             |  |                                        :   |
             |  |                                        :   |
             |  |                                        :   |                         CogDAC (Streamers/Cogs)
             |  |                                        :   |      [%%%%%%%%%%%%%]<============================= cog0
             |  |                                        :   |      [             ]<============================= cog1
             |  |      [%%%%%%%%%%%%%]                   :   |      [   DAC bus   ]<============================= cog2
             |  |      [  Flash DAC  ]<=============================[   select    ]<============================= cog3
             |<--------[   Network   ]                   :   |      [             ]<============================= cog4
             |  |      [   (%P...P)  ]                   :   |      [   (%P...P)  ]<============================= cog5
             |  |      [             ]<-                 :   |      [             ]<============================= cog6
             |  |      [%%%%%%%%%%%%%]  |                :   |      [             ]<============================= cog7
             |  |                       |                :   |      [%%%%%%%%%%%%%]<===\\
             |  |                       |                :   |              ^          ||
             |  |      [%%%%%%%%%%%%%]  |                :    -----------   |          ||
             |  |      [ Logic Drive ]<-+-------------   :         Other |  |BitDAC    || SmartDAC
[%%%%%%%%]   |<--------[   (%P...P)  ]                |  :               v  |          ||
[        ]   |  |      [             ]<-------------  |  :          [%%%%%%%%%%%%%]    ||
[Physical]   |  |      [%%%%%%%%%%%%%]              | |  :   Enable [             ]<------------------------------ OUT
[ Odd #  ]---+  |            ^                      |  -------------[    Logic    ]    ||
[ Pin Pad]   |  |            |                      |    :   Output [    Output   ]<---------------------------+-- DIR
[        ]   |  |             -----------            ---------------[             ]    ||                      |
[%%%%%%%%]   |  |                        |               :          [    (%TT)    ]    ||    [%%%%%%%%%%%%]    |
             |  |                        |               :          [  (%MMMMM_0) ]    \\====[            ]    |
             |  |                        |               :      OUT [             ]          [   Odd #    ]<---
             |  |      [%%%%%%%%%%%%%]   |               :       ---[             ]<---------[  Smartpin  ]
       (Pair)|  | PinB [  Comparator ]   |               :      |   [%%%%%%%%%%%%%] SmartOUT [ (%MMMMM_0) ]
             |   ----->[   & Logic   ]   |               :      |                            [            ]
       (Self)|    PinA [  & Schmitt  ]   |               :      |                            [  (X reg)===]<==== WXPIN
             +-------->[  (%P...P)   ]---+ Input         :      |     -1  -2  -3             [  (Y reg)===]<==== WYPIN
             |         [             ]   |               :      |      |   |   |             [  (Z reg)===]====> RDPIN
             |         [%%%%%%%%%%%%%]   |               :      |      v   v   v             [            ]
             |                           |               :      |   [%%%%%%%%%%%%%]  SmartA  [            ]
             |                           |   [%%%%%%%%]  :       -->[    Mux &    ]--------->[---o----o---]-------> IN
             |         [%%%%%%%%%%%%%]    -->[   Mux  ]  :          [  De-glitch  ]  SmartB  [  (M == 0)  ]
             |         [ Sigma-Delta ]       [(%P...P)]------------>[   (A_B_F)   ]--------->[            ]
              -------->[     ADC     ]------>[        ]  :          [%%%%%%%%%%%%%]          [            ]<------ ACK
                       [  (%P...P)   ]       [%%%%%%%%]  :             ^   ^   ^             [ USB passive]
                       [%%%%%%%%%%%%%]                   :             |   |   |             [%%%%%%%%%%%%]
                                                         :            +1  +2  +3
                                                         :
            .......................                      :               ..........................
            : Custom I/O Pad Ring :                      :               : Synthesised Core Logic :
            '''''''''''''''''''''''                      :               ''''''''''''''''''''''''''
  • evanhevanh Posts: 15,916
    And here's an updated %AAAA_BBBB_FFF brief to match: 
    %AAAA:   SmartA input selector
	0xxx = true (default)
	1xxx = inverted
	x000 = this pin’s read state (default)
	x001 = relative +1 pin’s read state
	x010 = relative +2 pin’s read state
	x011 = relative +3 pin’s read state
	x100 = this pin’s OUT bit from cogs
	x101 = relative -3 pin’s read state
	x110 = relative -2 pin’s read state
	x111 = relative -1 pin’s read state

%BBBB:   SmartB input selector
	0xxx = true (default)
	1xxx = inverted
	x000 = this pin’s read state (default)
	x001 = relative +1 pin’s read state
	x010 = relative +2 pin’s read state
	x011 = relative +3 pin’s read state
	x100 = this pin’s OUT bit from cogs
	x101 = relative -3 pin’s read state
	x110 = relative -2 pin’s read state
	x111 = relative -1 pin’s read state

%FFF:    SmartA and SmartB input logic/filtering (after input selectors)
	000 = SmartA, SmartB (default)
	001 = SmartA AND SmartB, SmartB
	010 = SmartA OR SmartB, SmartB
	011 = SmartA XOR SmartB, SmartB
	100 = SmartA, SmartB, both filtered using global filt0 settings
	101 = SmartA, SmartB, both filtered using global filt1 settings
	110 = SmartA, SmartB, both filtered using global filt2 settings
	111 = SmartA, SmartB, both filtered using global filt3 settings

	The resultant SmartA will drive the IN signal in non-smart-pin modes.
  • evanhevanh Posts: 15,916
    Actually, I note Chip has a logical flaw in the description of %FFF. You kind of have to use common sense to know that it's not A = A XOR B for example. But rather A = Asel XOR Bsel.
  • JonTitusJonTitus Posts: 193
    Good clarification. Why would a programmer want to use one of those operations?

    As to figures... I use a Mac desktop and run NeoOffice, which has a nice block-diagram flow-chart set of objects in its drawing program. Object connectors "rubber band" and remain connected when you move something.
    I think OpenOffice has something similar for Windows PCs. I also used ExpressPCB's schematic capture for line drawings in my Parallax book.
  • AJLAJL Posts: 517
    edited 2020-04-22 23:31
    Maybe the PinA and PinB in the Custom I/O ring should simply be called Self and Pair.
  • evanhevanh Posts: 15,916
    AJL wrote: »
    Maybe the PinA and PinB in the Custom I/O ring should simply be called Self and Pair.
    Having one set as comments helps with matching up to to Chip's documents without needing a lot of edits to other documents, including rewording of some sentences. PinA/B could be the ones in brackets instead.


  • evanhevanh Posts: 15,916
    JonTitus wrote: »
    Why would a programmer want to use one of those operations?
    Can't say I've had a reason but one explanation might be that that predated the smartpins and just stayed there because it's so tiny.

  • JonTitusJonTitus Posts: 193
    People might think "pair" indicates an exact duplicate. How about EvenPin and OddPin?
  • whickerwhicker Posts: 749
    Self and partner, then?
  • JonTitusJonTitus Posts: 193
    That sounds good, too.
  • Cluso99Cluso99 Posts: 18,069
    edited 2020-04-23 20:49
    Just remember when naming pin pairs, that there are also cog pairs too. These have nothing to do with the pin pairs tho'.
    Cog pairs are the even cogs and its' next odd partner. They can share the LUT RAM as dual-port between the cogs.
  • TubularTubular Posts: 4,702
    JonTitus wrote: »
    People might think "pair" indicates an exact duplicate. How about EvenPin and OddPin?

    What about "coupled pair". The "couples" perhaps implies the elements of the pair need not be considered identical
  • JonTitusJonTitus Posts: 193
    OK, if you have a "coupled pair," users need a way to tell them apart. Maybe EvenCog and OddCog and EvenPin and OddPin? Finding the best identifier in this situation presents a challenge.
  • TubularTubular Posts: 4,702
    Yes it is a challenge, it's really good that you're thinking about this

    Unless you go to the bother of explaining EvenPin and OddPin near their usage, you would likely need to say
    "the odd pin of the coupled pair"
    "the even pin of the coupled pair"

    "the odd cog of the coupled pair"
    "the even cog of the coupled pair"

    that's somewhat cumbersome, but it is precise.
  • evanhevanh Posts: 15,916
    The use of odd and even is two type definitions. Whereas self and pair is relative referencing and both can be either odd or even but exclusive, ie: When self is even then pair is odd, and vis-à-vis, when self is odd then pair is even.

  • msrobotsmsrobots Posts: 3,709
    maybe I am wrong, but odd and even is just relevant when using USB, else we have +3 to-3 pins available, why call them odd/even?

    In fact a smartpin 10 could use pins 8 and 11 as a and b right?

    mike
  • evanhevanh Posts: 15,916
    Interestingly, thinking about it, all the functional odd/even differences are in the synthesised logic alone. Namely, USB and Other. I had Other placed on the other side of the dotted line in my block diagram for a long time though.

    Fact is, the naming is needed to say that, of each pair of pins, there is two almost identical functions sets that are ordered on odd and even P## pin numbers.
    msrobots wrote: »
    In fact a smartpin 10 could use pins 8 and 11 as a and b right?
    That's SmartA and SmartB now. Don't want to be confused with PinA and PinB. :)

  • evanhevanh Posts: 15,916
    Or you can call em SMART_A and SMART_B if you like.
  • JonTitusJonTitus Posts: 193
    If we want to use letters, how about W and V. Why? A "W" looks like two Vs, so it could be assigned to PinA and a single V assigned to PinB. By the symbol itself people would know the difference. PinW or Pin_W and PinV or Pin_V. I'm not looking at alphabetic order, just the "double V" and the "single V" symbols. Just a thought... --Jon
  • TubularTubular Posts: 4,702
    The trouble with W is that its commonly associated with "write" on the P2

  • JonTitusJonTitus Posts: 193
    Darn. I guess Pin++ and Pin+ wouldn't work, either. Other ideas: Red-Green, Hot-Cold, Gold-Silver, Mother-Daughter, North-South, Dog-Cat, Batman-Robin? ;-)
  • AJLAJL Posts: 517
    ϴ & Φ, α & Ω?
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