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Memory drivers for P2 - PSRAM/SRAM/HyperRAM (was HyperRAM driver for P2)

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Comments

  • YanomaniYanomani Posts: 1,507

    @rogloh said:

    @evanh said:
    You brought up the read-modify-write topic as I was finishing up my demo code - That's something that is new because of the EC32MB wiring isn't it. Because it can only be written 32-bit at a time, right?

    Yes. If it's wired as a 16 bit bus then with two cycles per write, only a complete 32 bit long should be written at a time. So to avoid data corruption in the memory both upper and lower 16 bits need to be written whenever a write is performed, and this necessitates a read first. You can't start writing half way into the long, you need to start from the beginning after CE is brought low, and there is no data qualifier brought out (unlike the OPI PSRAM).

    As for any of the possible multiple PSRam configurations based on single (and commom to all devices) /CE and SCLK signals, the most atractive way to achieve Selective Write operations (either Overwrtie or Read-Modify_Write ones), would be to rely on the reservation of either the first or the last row, of each and every memory chip involved, in order to serve as a "dummy" scratchpad area.

    Obviouslly, only the targeted chip within each group would receive the proper addressing information, while the other ones would be directed to proceed the "dummy" write operation at the scratchpad row.

    Also the requested addressing information to be accessed would always need to be incremented by one (in case "Row Zero" was selected to be the "trash-blender"), or limited to the maximum available row number of each PSRam chip minus one (otherwise).

    I did also considered the option of putting the non-targeted chips into Fast Read mode, but this would only complicate things, due to the forcefully interveining Wait-period, and the unnavoidable "noisy and power-hungry" other PSRam databuses, agressivelly-whipping into P2 inputs, that, sure, would need to be also reprogrammed to act as so.

  • roglohrogloh Posts: 4,461
    edited 2022-08-05 02:38

    @Yanomani The problem is not that we want to stop a write to a single chip, we want a way to stop the paired nibble in the same chip from needing to be re-written each time we update its partner nibble's contents. Without RWDS we can't do that and have to do a RMW. And a RMW of a data bus subset saves no time vs RMW of the full bus width (streamer has same performance in both cases), so no need to try to filter writes to individual chips.

  • YanomaniYanomani Posts: 1,507
    edited 2022-08-05 02:56

    Then I missed the point (as usual... :smile: ); PSRam R/W operations are byte-granular by definition. Similarly, Hyper's (and Xccela OPI's) R/W operations are word-granular.

  • evanhevanh Posts: 13,424
    edited 2022-08-05 03:18

    @rogloh said:
    Are you planning on a pair of OPI PSRAMs, or a pair of HyperRAMs?

    I'm thinking in terms of a revB EC32MB. RevA was so close to getting DDR I was surprised disappointed it never happened at the time. Maybe it was the awkward FBGA package that was the deciding factor.

    EDIT: OPI is the clear preference for Prop2. HyperRAMs are more suited to a hardware memory controller.

  • RaymanRayman Posts: 12,734
    edited 2022-08-05 19:41

    @evanh I think I put a place for an extra capacitor on one of these boards to delay the clock signal (at your request ?).
    Get a chance to try that?

    Oops, remembered wrongly... It's the 8bit chip boards that have that...

  • evanhevanh Posts: 13,424
    edited 2022-08-06 10:13

    I could try hacking a capacitor in, it should work at low frequencies at least, ...

    EDIT: 6.8 pF is not enough. It works 100% for only the best case config of last chip of the 48 MB add-on when plugged into P8..P15.

    EDIT2: 8.2 pF improves all ... And just changed, from glob-top, to my newer production packaged ES revB Eval Board and it is a little better even. But still need better ...

  • roglohrogloh Posts: 4,461

    @Yanomani said:
    Then I missed the point (as usual... :smile: ); PSRam R/W operations are byte-granular by definition. Similarly, Hyper's (and Xccela OPI's) R/W operations are word-granular.

    They are byte granular and use two 4 bit transfers to write them in their 4 bit bus arrangement. However when you combine them with multiple devices ganged together to widen the bus, then the second nibble in the pair (traditionally storing that single byte in a single chip) actually stores a different byte in the long now so you need a RMW operation if you want to preserve it whenever writing to either nibble portion independently for smaller than long sized elements (in 4x4 bit PSRAM widths), or for any unaligned longs at start and end of transfers.

  • YanomaniYanomani Posts: 1,507

    Thanks @rogloh !

    Sometimes it seems necessary to perform many "head-shakes", before things can settle deep enough into my head (without having to resort to a hammer)... :lol:

  • evanhevanh Posts: 13,424

    Check this out - same Eval Board, production ES revB, same 48 MB 1x4-bit add-on board, same accessory header, same 22 pF capacitor on the clock pin, code the same except for the chip-select. Each of the three chips:

     DATA_PIN = 32 addpins 3
      CLK_PIN = 36 addpins 0
       CE_PIN = 37 addpins 0
    SPI cmode3  TX_REGD = 1  CLK_REGD = 0  CLK_ADV = 1
    SPI clock ratio = 2 (sysclock/2)
     bus[3:0] Chip ID:  0d 5d 52 f6 08 37 b5 6c
    
     200 MHz     0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0%   0% 
     202 MHz     0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0%   0% 
     204 MHz     0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0%   0% 
     206 MHz     0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0%   0% 
     208 MHz     0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0%   0% 
     210 MHz     0%   0%   0%   0%  99%  99%  99%   0%   0%   0%   0%   0% 
     212 MHz     0%   0%   0%   0%  98%  98%  98%   0%   0%   0%   0%   0% 
     214 MHz     0%   0%   0%   0%  97%  97%  97%   0%   0%   0%   0%   0% 
     216 MHz     0%   0%   0%   0%  96%  96%  96%   0%   0%   0%   0%   0% 
     218 MHz     0%   0%   0%   0%  96%  96%  96%   0%   0%   0%   0%   0% 
     220 MHz     0%   0%   0%   0%  97%  97%  97%   0%   0%   0%   0%   0% 
     222 MHz     0%   0%   0%   0%  97%  98%  97%   0%   0%   0%   0%   0% 
     224 MHz     0%   0%   0%   0%  97%  98%  98%   5%   0%   0%   0%   0% 
     226 MHz     0%   0%   0%   0%  93%  98%  98%  18%   0%   0%   0%   0% 
     228 MHz     0%   0%   0%   0%  85%  98%  98%  42%   0%   0%   0%   0% 
     230 MHz     0%   0%   0%   0%  73%  98%  98%  70%   0%   0%   0%   0% 
     232 MHz     0%   0%   0%   0%  60%  99%  99%  90%   0%   0%   0%   0% 
     234 MHz     0%   0%   0%   0%  46%  99%  99%  97%   0%   0%   0%   0% 
     236 MHz     0%   0%   0%   0%  33%  99%  99%  99%   0%   0%   0%   0% 
     238 MHz     0%   0%   0%   0%  22%  99%  99%  99%   0%   0%   0%   0% 
     240 MHz     0%   0%   0%   0%  14%  99%  99%  99%   0%   0%   0%   0% 
     242 MHz     0%   0%   0%   0%   9%  99%  99%  99%   0%   0%   0%   0% 
     244 MHz     0%   0%   0%   0%   5%  99%  99%  99%   0%   0%   0%   0% 
     246 MHz     0%   0%   0%   0%   3%  99%  99%  99%   0%   0%   0%   0% 
     248 MHz     0%   0%   0%   0%   1%  99%  99%  99%   0%   0%   0%   0% 
     250 MHz     0%   0%   0%   0%   0%  99%  99%  99%   0%   0%   0%   0% 
     252 MHz     0%   0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0% 
     254 MHz     0%   0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0% 
     256 MHz     0%   0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0% 
     258 MHz     0%   0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0% 
     260 MHz     0%   0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0% 
     262 MHz     0%   0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0% 
     264 MHz     0%   0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0% 
     266 MHz     0%   0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0% 
     268 MHz     0%   0%   0%   0%   0% 100% 100% 100%   9%   0%   0%   0% 
     270 MHz     0%   0%   0%   0%   0% 100% 100% 100%  91%   0%   0%   0% 
    
     DATA_PIN = 32 addpins 3
      CLK_PIN = 36 addpins 0
       CE_PIN = 38 addpins 0
    SPI cmode3  TX_REGD = 1  CLK_REGD = 0  CLK_ADV = 1
    SPI clock ratio = 2 (sysclock/2)
     bus[3:0] Chip ID:  0d 5d 52 f6 08 39 52 30
    
     200 MHz     0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0%   0% 
     202 MHz     0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0%   0% 
     204 MHz     0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0%   0% 
     206 MHz     0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0%   0% 
     208 MHz     0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0%   0% 
     210 MHz     0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0%   0% 
     212 MHz     0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0%   0% 
     214 MHz     0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0%   0% 
     216 MHz     0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0%   0% 
     218 MHz     0%   0%   0%   0%  99% 100%  99%   0%   0%   0%   0%   0% 
     220 MHz    12%  13%  11%   0%  24%  30%  26%   0%   0%   0%   7%   0% 
     222 MHz     0%   4%   5%   0%   7%   6%   6%   0%   1%   0%   0%   0% 
     224 MHz     0%   7%   0%   1%  16%  13%  12%   2%   0%   0%   0%   0% 
     226 MHz     0%   0%   3%   0%  51%  56%  61%  12%   0%   0%   0%   0% 
     228 MHz     0%   0%   0%   0%  74%  94%  93%  16%   0%   0%   0%   0% 
     230 MHz     0%   0%   0%   0%  71% 100% 100%  20%   0%   0%   0%   0% 
     232 MHz     0%   0%   0%   0%  62% 100% 100%  35%   0%   0%   0%   0% 
     234 MHz     0%   0%   0%   0%  51% 100% 100%  54%   0%   0%   0%   0% 
     236 MHz     0%   0%   0%   0%  38% 100% 100%  71%   0%   0%   0%   0% 
     238 MHz     0%   0%   0%   0%  25% 100% 100%  83%   0%   0%   0%   0% 
     240 MHz     0%   0%   0%   0%  15% 100% 100%  92%   0%   0%   0%   0% 
     242 MHz     0%   0%   0%   0%  10% 100% 100%  97%   0%   0%   0%   0% 
     244 MHz     0%   0%   0%   0%   7% 100% 100%  99%   0%   0%   0%   0% 
     246 MHz     0%   0%   0%   0%   5% 100% 100% 100%   0%   0%   0%   0% 
     248 MHz     0%   0%   0%   0%   3% 100% 100% 100%   0%   0%   0%   0% 
     250 MHz     0%   0%   0%   0%   2% 100% 100% 100%   0%   0%   0%   0% 
     252 MHz     0%   0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0% 
     254 MHz     0%   0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0% 
     256 MHz     0%   0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0% 
     258 MHz     0%   0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0% 
     260 MHz     0%   0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0% 
     262 MHz     0%   0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0% 
     264 MHz     0%   0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0% 
     266 MHz     0%   0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0% 
     268 MHz     0%   0%   0%   0%   0% 100% 100% 100%   3%   0%   0%   0% 
     270 MHz     0%   0%   0%   0%   0% 100% 100% 100%   9%   0%   0%   0% 
    
     DATA_PIN = 32 addpins 3
      CLK_PIN = 36 addpins 0
       CE_PIN = 39 addpins 0
    SPI cmode3  TX_REGD = 1  CLK_REGD = 0  CLK_ADV = 1
    SPI clock ratio = 2 (sysclock/2)
     bus[3:0] Chip ID:  0d 5d 52 f6 08 39 da 84
    
     200 MHz     0%   0%   0%  15% 100% 100% 100%   0%   0%   0%   0%   0% 
     202 MHz     0%   0%   0%   7%  93%  96%  94%   0%   0%   0%   0%   0% 
     204 MHz     0%   0%   0%   1%  56%  54%  54%   1%  41%  46%  44%   0% 
     206 MHz     0%   0%   0%   0%  37%  37%  38%   0%  37%  38%  35%   0% 
     208 MHz     0%   0%   8%   0%  29%  28%  30%   0%  29%  31%  27%   0% 
     210 MHz     0%   0%   0%   0%  68%  73%  73%   0%  16%  15%   0%   0% 
     212 MHz     0%   0%   0%   0%  83%  81%  83%   0%   0%   0%   0%   0% 
     214 MHz     0%   0%   0%   0%  14%  15%  13%   0%  24%  22%   0%   0% 
     216 MHz     0%   1%   1%   0%   2%   2%   2%   0%   0%   0%   1%   0% 
     218 MHz     0%   0%   0%   0%   0%   0%   0%   0%   0%   0%   0%   0% 
     220 MHz     0%   0%   0%   0%   0%   0%   0%   0%   0%   0%   0%   0% 
     222 MHz     1%   0%   1%   0%   0%   1%   0%   0%   0%   0%   1%   0% 
     224 MHz     0%   0%   0%   0%   5%   6%   5%   0%   0%   0%   0%   0% 
     226 MHz     0%   0%   0%   0%  52%  48%  46%   0%   0%   6%   6%   0% 
     228 MHz     0%   0%   0%   0%  96%  98%  96%   0%   0%   0%   0%   0% 
     230 MHz     0%   0%   0%   0%  98%  98%  96%   0%   0%   0%   0%   0% 
     232 MHz     0%   0%   0%   0%  95%  97%  97%   0%   0%   0%   0%   0% 
     234 MHz     0%   0%   0%   0%  97%  97%  99%   0%   0%   0%   0%   0% 
     236 MHz     0%   0%   0%   0%  98%  99% 100%   0%   0%   0%   0%   0% 
     238 MHz     0%   0%   0%   0%  97% 100%  99%  11%   0%   0%   0%   0% 
     240 MHz     0%   0%   0%   0%  95% 100%  99%  37%   0%   0%   0%   0% 
     242 MHz     0%   0%   0%   0%  91% 100% 100%  62%   0%   0%   0%   0% 
     244 MHz     0%   0%   0%   0%  84% 100% 100%  79%   0%   0%   0%   0% 
     246 MHz     0%   0%   0%   0%  78% 100% 100%  91%   0%   0%   0%   0% 
     248 MHz     0%   0%   0%   0%  73% 100% 100%  98%   0%   0%   0%   0% 
     250 MHz     0%   0%   0%   0%  70% 100% 100%  99%   0%   0%   0%   0% 
     252 MHz     0%   0%   0%   0%  68% 100% 100% 100%   0%   0%   0%   0% 
     254 MHz     0%   0%   0%   0%  63% 100% 100% 100%   0%   0%   0%   0% 
     256 MHz     0%   0%   0%   0%  47% 100% 100% 100%   0%   0%   0%   0% 
     258 MHz     0%   0%   0%   0%  22% 100% 100% 100%   0%   0%   0%   0% 
     260 MHz     0%   0%   0%   0%   5% 100% 100% 100%   0%   0%   0%   0% 
     262 MHz     0%   0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0% 
     264 MHz     0%   0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0% 
     266 MHz     0%   0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0% 
     268 MHz     0%   0%   0%   0%   0% 100% 100% 100%   0%   0%   0%   0% 
     270 MHz     0%   0%   0%   0%   0%  96%  97%  99%   2%   0%   0%   0% 
    

    What blows me away is the spread of percentages across single lines. It's just falling to pieces. The lower capacitor values were better.

  • evanhevanh Posts: 13,424
    edited 2022-08-06 13:07

    Basically want to avoid using a capacitor. It's a hack workaround that stops working above 10 pF.

    Here's the reports I gathered for the worse case accessory header - P32..P39. And what I thought was the worst case chip, but may not have been correct on that count. Chip select P39 is breaking up much worse at larger capacitor values.

  • roglohrogloh Posts: 4,461
    edited 2022-08-06 20:02

    Forget the capacitor, it's useless and you are better off without it. The problem I think is the total load on the data bus with too many chips in parallel is distorting the data signals too much. Workaround is to clock at sysclk/3. A tighter layout might also be helpful to eliminate some skew differences between devices but is not guaranteed to resolve the underlying issue which is that we have too many devices in parallel (6 chips!).

    There's possibly lots of reflections going on too. I imagine the bus voltage waveform is quite messy.

  • evanhevanh Posts: 13,424
    edited 2022-08-06 23:49

    Oh, it's not as bad as that seemed, that particular test was for simulating sysclock/1 as if they were DDR parts. The CLK_ADV = 1 made the TX timing very tight. Ie: 1.0 ns tight. So, in one sense I was seeing if that 24 MB board layout could be tuned to fit. I wasn't surprised that it can't. There is likely a number of layout limitations for why ... but, yeah, reaching for the capacitor is poor fix. And certainly limited.

    EDIT: Err, it's the 24 MB add-on. There is no 48 MB add-on. Duh, sorry, hadn't thought much on that detail.

    I didn't bother testing the 96 MB add-on with this CLK_ADV = 1 partly because it needed two capacitors of each value fitted, and partly because the 24 MB was poorly performing anyway.

  • There's something to be said about series resistors on high speed transmission lines. I didn't believe it myself until in a hail Mary I added one on the CS signal on my rats nest hyperram a few years ago.

    From time to time, the old gray beards say that adding capacitance never solves the timing issue, but I can't seem to get an explanation of why, other than "it just doesn't work."

  • evanhevanh Posts: 13,424

    Hmm, yeah, ground bounce is a likely candidate. Resistors would soften the switching edges. I'm not happy with the tiny track a single via for the header's ground pins of the 24 MB add-on. All the more reason to do a fresh layout with OPI parts.

  • evanhevanh Posts: 13,424
    edited 2022-08-07 03:30

    That's a valid argument for having those header drill holes with pads. I think it was Vons that suggested doing that. It provides a substantial increase in the surface width of ground conductors. They act as an oversized via, which provides a lot more vertical surface through the PCB.

    EDIT: Ah, and Roger's add-ons did exactly that with great results - https://forums.parallax.com/discussion/comment/1540379/#Comment_1540379

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