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What to do with my FPGA boards? — Parallax Forums

What to do with my FPGA boards?

RaymanRayman Posts: 14,646
in Propeller 2
Ok, my P2V FPGA boards are completely worthless to me now...
What to do with them?

Should I save them for P3?

Comments

  • samuellsamuell Posts: 554
    Hi,

    You should do projects of your own. An FPGA is never worthless. :)

    Kind regards, Samuel Lourenço
  • RaymanRayman Posts: 14,646
    Well, when P2 was taking forever to complete, I actually did start to learn FPGA.
    But, I found it to be very tedious...
    I'm glad P2 saved me from that...
  • TubularTubular Posts: 4,702
    P3...
  • evanhevanh Posts: 15,916
    A hobby is all about the community. That never dawned on me for a long time.

    Doing a FPGA design without a specific job for it to do would be a very lonely exercise.

  • cgraceycgracey Posts: 14,153
    Hold onto those boards. They should be getting some more use in the future.
  • jmgjmg Posts: 15,173
    cgracey wrote: »
    Hold onto those boards. They should be getting some more use in the future.

    That sounds ominous !!

  • David BetzDavid Betz Posts: 14,516
    Rayman wrote: »
    Ok, my P2V FPGA boards are completely worthless to me now...
    What to do with them?

    Should I save them for P3?
    Isn't the Parallax FPGA board called the P123? I think that was intended to mean it could be used for P1, P2, and P3. Keep your board!

  • evanhevanh Posts: 15,916
    Lol, I don't Chip is implying a prop3 just yet. I'm guessing more models of the prop2 once the money is rolling in. Namely smaller ones and maybe without a thermal pad.
  • TonyB_TonyB_ Posts: 2,178
    After more urgent matters have been dealt with, an enhanced version of XORO32 with a new option for 32-bit equidistribution is one of the things that could be tested on the FPGA boards.
  • cgraceycgracey Posts: 14,153
    TonyB_ wrote: »
    After more urgent matters have been dealt with, an enhanced version of XORO32 with a new option for 32-bit equidistribution is one of the things that could be tested on the FPGA boards.

    Super!
  • potatoheadpotatohead Posts: 10,261
    This "keep hold of boards" makes me happy.

    Best visit Ken and stock up on goodies. Looks like the ride is not over.

    And how awesome will it be to have P2 chips while making derivative ones?

    Thanks Chip. Ken. Seriously. Tonight, I am banging on what we believe to be viable production. I have been telling everyone I can.

    Now... I forgot stuff. Lol. There may be questions needed to backfill brain cells overtaxed as of late.

  • TubularTubular Posts: 4,702
    Chip made a 2 cog image that we couldn't quite get to work at the time, and didn't want to bug him given the critical path.

    The theory was that this image would run native micropython (or erics micropython) significantly faster, due to the more frequency hub accesses
  • evanhevanh Posts: 15,916
    edited 2019-11-21 11:40
    There is a fixed minimum of 9 clocks to fetch from hubram. The only part that changes is the variable 7 extra becomes variable 3 extra for a 4-cog prop2.

    EDIT: Although, maybe that could be a focus of optimisation for the smaller models.

  • TonyB_TonyB_ Posts: 2,178
    edited 2019-11-21 14:46
    evanh wrote: »
    There is a fixed minimum of 9 clocks to fetch from hubram. The only part that changes is the variable 7 extra becomes variable 3 extra for a 4-cog prop2.

    EDIT: Although, maybe that could be a focus of optimisation for the smaller models.

    Is a delay of 9 clocks really needed for a random read, when no further read * is wanted from the next address?

    * excluding extra read cycle when crossing hub long
  • evanhevanh Posts: 15,916
    Yep, that's the design as it stands. Just like all the stages for I/O, to get good sys-clock speeds required many stages into and out of hubRAM too. There is 16 processing blocks (8 cogs and 8 FIFOs) that can each address hubRAM for either reading or writing. And in the middle is the eggbeater that can feed all 8 hubRAM buses in parallel on every sys-clock.

    Maybe it's possible to be improved upon, dunno.
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